This paper describes a design methodology, a library of reusable VHDL descriptions and a VHDL generation tool used in the application area of digital signal processing, particularly digital receivers for communication links. The tool and the library interact with commercial system simulation and logic synthesis tools. The support of joint optimization of algorithm and architecture as well as the concept for design reuse are explained. The algorithms for generating VHDL code according to different user specifications are described. An application example is used to show the benefits and current limitations of the proposed methodology.
{"title":"Digital Receiver Design Using VHDL Generation From Data Flow Graphs","authors":"Peter Zepter, Thorsten Grötker, H. Meyr","doi":"10.1145/217474.217534","DOIUrl":"https://doi.org/10.1145/217474.217534","url":null,"abstract":"This paper describes a design methodology, a library of reusable VHDL descriptions and a VHDL generation tool used in the application area of digital signal processing, particularly digital receivers for communication links. The tool and the library interact with commercial system simulation and logic synthesis tools. The support of joint optimization of algorithm and architecture as well as the concept for design reuse are explained. The algorithms for generating VHDL code according to different user specifications are described. An application example is used to show the benefits and current limitations of the proposed methodology.","PeriodicalId":422297,"journal":{"name":"32nd Design Automation Conference","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122711581","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We present a new approach to event-driven simulation that does not use a centralized run-time event queue, yet is capable of handling arbitrary models, including those with unclocked feedback and nonunit delay. The elimination of the event queue significantly reduces run-time overhead, resulting in faster simulation. We have implemented our algorithm in a prototype Verilog simulator called VeriSUIF. Using this simulator we demonstrate improved performance vs. a commercial simulator on a small set of programs.
{"title":"A General Method for Compiling Event-Driven Simulations","authors":"R. French, M. Lam, J. Levitt, K. Olukotun","doi":"10.1145/217474.217522","DOIUrl":"https://doi.org/10.1145/217474.217522","url":null,"abstract":"We present a new approach to event-driven simulation that does not use a centralized run-time event queue, yet is capable of handling arbitrary models, including those with unclocked feedback and nonunit delay. The elimination of the event queue significantly reduces run-time overhead, resulting in faster simulation. We have implemented our algorithm in a prototype Verilog simulator called VeriSUIF. Using this simulator we demonstrate improved performance vs. a commercial simulator on a small set of programs.","PeriodicalId":422297,"journal":{"name":"32nd Design Automation Conference","volume":"431 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125756214","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a methodology and tool (Power-Profiler) for the optimization of average and peak power consumption in the behavioral synthesis of ASICs. It considers lowering operating voltages, disabling the clock of components not in use, and architectural trade-offs, while also keeping silicon area at reasonable sizes. By attacking the power problem from the behavioral level, it can exploit an application's inherent parallelism to meet the desired performance and compensate for slower and less power-hungry operators.
{"title":"Power-Profiler: Optimizing ASICs Power Consumption at the Behavioral Level","authors":"R. S. Martin, J. Knight","doi":"10.1145/217474.217504","DOIUrl":"https://doi.org/10.1145/217474.217504","url":null,"abstract":"This paper presents a methodology and tool (Power-Profiler) for the optimization of average and peak power consumption in the behavioral synthesis of ASICs. It considers lowering operating voltages, disabling the clock of components not in use, and architectural trade-offs, while also keeping silicon area at reasonable sizes. By attacking the power problem from the behavioral level, it can exploit an application's inherent parallelism to meet the desired performance and compensate for slower and less power-hungry operators.","PeriodicalId":422297,"journal":{"name":"32nd Design Automation Conference","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125960979","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Many asynchronous designs are naturally specified and implemented hierarchically as an interconnection of separate asynchronous modules that operate concurrently and communicate with each other. This paper is concerned with the problem of synthesizing such hierarchically defined systems. When the individual components are synthesized and implemented separately, it is desirable to take into account the degrees of freedom that arise from the interactions with the other components and from the specification. Specifically, we consider how one can find the set of implementations that can be "correctly substituted" for a component in the system while preserving the behavior of the total system. The notion of correct substitution is formally defined for a hierarchical network of possibly non-deterministic modules and a new solution framework based on trace theory is presented to compute and represent this complete set of correct substitutions. We show that the complete set can be captured by a single trace structure using the notion of a "maximal trace structure". We indicate how asynchronous synthesis methods may be applied to explore the solution space e.g. to generate a delay-insensitive implementation.
{"title":"Hierarchical Optimization of Asynchronous Circuits","authors":"Bill Lin, G. D. Jong, T. Kolks","doi":"10.1145/217474.217616","DOIUrl":"https://doi.org/10.1145/217474.217616","url":null,"abstract":"Many asynchronous designs are naturally specified and implemented hierarchically as an interconnection of separate asynchronous modules that operate concurrently and communicate with each other. This paper is concerned with the problem of synthesizing such hierarchically defined systems. When the individual components are synthesized and implemented separately, it is desirable to take into account the degrees of freedom that arise from the interactions with the other components and from the specification. Specifically, we consider how one can find the set of implementations that can be \"correctly substituted\" for a component in the system while preserving the behavior of the total system. The notion of correct substitution is formally defined for a hierarchical network of possibly non-deterministic modules and a new solution framework based on trace theory is presented to compute and represent this complete set of correct substitutions. We show that the complete set can be captured by a single trace structure using the notion of a \"maximal trace structure\". We indicate how asynchronous synthesis methods may be applied to explore the solution space e.g. to generate a delay-insensitive implementation.","PeriodicalId":422297,"journal":{"name":"32nd Design Automation Conference","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116776390","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The Elmore delay is an extremely popular delay metric, particularly for RC tree analysis. The widespread usage of this metric is mainly attributable to it being the most accurate delay measure that is a simple analytical function of the circuit parameters. The only drawbacks to this delay metric are the uncertainty as to whether it is an optimistic or a pessimistic estimate, and the restriction to step response delay estimation. In this paper, we prove that the Elmore delay is an absolute upper bound on the 50% delay of an RC tree response. Moreover, we prove that this bound holds for input signals other than steps, and that the actual delay asymptotically approaches the Elmore delay as the input signal rise time increases. A lower bound on the delay is also developed using the Elmore delay and the second moment of the impulse response. The utility of this bound is for understanding the accuracy and the limitations of the Elmore delay metric as we use it for design automation.
{"title":"The Elmore Delay as a Bound for RC Trees with Generalized Input Signals","authors":"Rohinish Gupta, B. Tutuianu, L. Pileggi","doi":"10.1145/217474.217556","DOIUrl":"https://doi.org/10.1145/217474.217556","url":null,"abstract":"The Elmore delay is an extremely popular delay metric, particularly for RC tree analysis. The widespread usage of this metric is mainly attributable to it being the most accurate delay measure that is a simple analytical function of the circuit parameters. The only drawbacks to this delay metric are the uncertainty as to whether it is an optimistic or a pessimistic estimate, and the restriction to step response delay estimation. In this paper, we prove that the Elmore delay is an absolute upper bound on the 50% delay of an RC tree response. Moreover, we prove that this bound holds for input signals other than steps, and that the actual delay asymptotically approaches the Elmore delay as the input signal rise time increases. A lower bound on the delay is also developed using the Elmore delay and the second moment of the impulse response. The utility of this bound is for understanding the accuracy and the limitations of the Elmore delay metric as we use it for design automation.","PeriodicalId":422297,"journal":{"name":"32nd Design Automation Conference","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114787957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper describes a HDL synthesis based design methodology that supports user adoption of behavioral-level synthesis into normal design practices. The use of these techniques increases understanding of the HDL descriptions before synthesis, and makes the comparison of pre- and post-synthesis design behavior through simulation much more direct. This increases user confidence that the specification does what the user wants, i.e. that the synthesized design matches the specification in the ways that are important to the user. At the same time, the methodology gives the user a powerful set of tools to specify complex interface timing, while preserving a user's ability to delegate decision-making authority to software in those cases where the user does not wish to restrict the options available to the synthesis algorithms.
{"title":"Behavioral Synthesis Methodology for HDL-Based Specification and Validation","authors":"D. Knapp, T. Ly, D. MacMillen, Ron Miller","doi":"10.1145/217474.217543","DOIUrl":"https://doi.org/10.1145/217474.217543","url":null,"abstract":"This paper describes a HDL synthesis based design methodology that supports user adoption of behavioral-level synthesis into normal design practices. The use of these techniques increases understanding of the HDL descriptions before synthesis, and makes the comparison of pre- and post-synthesis design behavior through simulation much more direct. This increases user confidence that the specification does what the user wants, i.e. that the synthesized design matches the specification in the ways that are important to the user. At the same time, the methodology gives the user a powerful set of tools to specify complex interface timing, while preserving a user's ability to delegate decision-making authority to software in those cases where the user does not wish to restrict the options available to the synthesis algorithms.","PeriodicalId":422297,"journal":{"name":"32nd Design Automation Conference","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116691657","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We propose a new problem formulation for low power clock network design that takes rise time constraints imposed by the design into account. We evaluate the utility of inserting buffers into the clock route for satisfying rise time constraints and for minimizing the area of the clock net. In particular, we show that the classical H-tree is sub-optimal in terms of both area and power dissipation when buffers may be inserted into the tree. We show that the power minimization problem is NP-hard and propose a greedy heuristic for power-optimal clock network design that utilizes the opportunities provided by buffer insertion. Our algorithm inserts buffers and designs the topology simultaneously. The results we obtain on benchmarks are significantly better than previous approaches in terms of power dissipation, wire length, rise times and buffer area. Power dissipation is typically reduced by a factor of two, rise times are four times better and buffer area requirements are an order of magnitude smaller.
{"title":"Power Optimal Buffered Clock Tree Design","authors":"Malgorzata Marek-Sadowska Ashok Vittal","doi":"10.1109/dac.1995.249998","DOIUrl":"https://doi.org/10.1109/dac.1995.249998","url":null,"abstract":"We propose a new problem formulation for low power clock network design that takes rise time constraints imposed by the design into account. We evaluate the utility of inserting buffers into the clock route for satisfying rise time constraints and for minimizing the area of the clock net. In particular, we show that the classical H-tree is sub-optimal in terms of both area and power dissipation when buffers may be inserted into the tree. We show that the power minimization problem is NP-hard and propose a greedy heuristic for power-optimal clock network design that utilizes the opportunities provided by buffer insertion. Our algorithm inserts buffers and designs the topology simultaneously. The results we obtain on benchmarks are significantly better than previous approaches in terms of power dissipation, wire length, rise times and buffer area. Power dissipation is typically reduced by a factor of two, rise times are four times better and buffer area requirements are an order of magnitude smaller.","PeriodicalId":422297,"journal":{"name":"32nd Design Automation Conference","volume":"5 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116743067","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
During system design, one or more portions of the system may be implemented with standard components that have a fixed pin structure and communication protocol. This paper described a new technique, interface process generation, for interfacing standard components that have incompatible protocols. Given an HDL description of the two protocols, we present a method to generate an interface process that allows the two protocols to communicate with each other.
{"title":"Interfacing Incompatible Protocols Using Interface Process Generation","authors":"Sanjiv Narayan, D. Gajski","doi":"10.1145/217474.217572","DOIUrl":"https://doi.org/10.1145/217474.217572","url":null,"abstract":"During system design, one or more portions of the system may be implemented with standard components that have a fixed pin structure and communication protocol. This paper described a new technique, interface process generation, for interfacing standard components that have incompatible protocols. Given an HDL description of the two protocols, we present a method to generate an interface process that allows the two protocols to communicate with each other.","PeriodicalId":422297,"journal":{"name":"32nd Design Automation Conference","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129754193","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper describes algebraic procedures for node extraction and factorization that target low power consumption. New power cost functions are introduced for the sum-of-products and factored form representations of functions. These cost functions are then used to guide the power optimization procedures. It is also shown that using the proposed SOP power cost function, all extractions resulting in a power reduction will not result in an increase in the number of literals in the network. The procedures described in this paper were implemented and results show 16% average improvement in power at the cost of 7% average increase in area.
{"title":"Logic Extraction and Factorization for Low Power","authors":"Massoud Pedram Sasan Iman","doi":"10.1109/dac.1995.250099","DOIUrl":"https://doi.org/10.1109/dac.1995.250099","url":null,"abstract":"This paper describes algebraic procedures for node extraction and factorization that target low power consumption. New power cost functions are introduced for the sum-of-products and factored form representations of functions. These cost functions are then used to guide the power optimization procedures. It is also shown that using the proposed SOP power cost function, all extractions resulting in a power reduction will not result in an increase in the number of literals in the network. The procedures described in this paper were implemented and results show 16% average improvement in power at the cost of 7% average increase in area.","PeriodicalId":422297,"journal":{"name":"32nd Design Automation Conference","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128074457","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We present a new fault simulation algorithm for realistic break faults in the p-networks and n-networks of static CMOS cells. We show that Miller effects can invalidate a test just as charge sharing can, and we present a new charge-based approach that efficiently and accurately predicts the worst case effects of Miller capacitances and charge sharing together. Results on running our fault simulator on ISCAS85 benchmark circuits are provided.
{"title":"Accurate and Efficient Fault Simulation of Realistic CMOS Network Breaks","authors":"H. Konuk, F. Ferguson, T. Larrabee","doi":"10.1145/217474.217553","DOIUrl":"https://doi.org/10.1145/217474.217553","url":null,"abstract":"We present a new fault simulation algorithm for realistic break faults in the p-networks and n-networks of static CMOS cells. We show that Miller effects can invalidate a test just as charge sharing can, and we present a new charge-based approach that efficiently and accurately predicts the worst case effects of Miller capacitances and charge sharing together. Results on running our fault simulator on ISCAS85 benchmark circuits are provided.","PeriodicalId":422297,"journal":{"name":"32nd Design Automation Conference","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130228651","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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