Pub Date : 2018-05-22DOI: 10.1109/SAPIW.2018.8401648
Jusang Park, Seung-Su Chun, Hoyong Choi, Namsoo Kim
This paper introduces a low power frequency divider in an integrated CMOS phase-locked loop (PLL). An injection-locked frequency divider (ILFD) is designed with a current-mode logic (CML) frequency divider to obtain the broad-band and high frequency operation. Ring oscillator operates at 1 GHz and ILFD is supposed to provide the operation of divide-by-2 (/2). The structure of ILFD is designed to be similar with that of oscillator in order to adjust the frequency alignment between the oscillator and ILFD. CML frequency divider is applied as the 2nd-stage divider. The proposed frequency divider is applied in the conventional PLL which is integrated with 0.18 μm CMOS process. Simulation test shows that the /2 ILFD and /16 CML frequency divider operates accurately and the total power consumption of 32 mW is obtained at the input frequency of 1 GHz.
{"title":"CMOS integrated 1 GHz ring oscillator with injection-locked frequency divider for low power PLL","authors":"Jusang Park, Seung-Su Chun, Hoyong Choi, Namsoo Kim","doi":"10.1109/SAPIW.2018.8401648","DOIUrl":"https://doi.org/10.1109/SAPIW.2018.8401648","url":null,"abstract":"This paper introduces a low power frequency divider in an integrated CMOS phase-locked loop (PLL). An injection-locked frequency divider (ILFD) is designed with a current-mode logic (CML) frequency divider to obtain the broad-band and high frequency operation. Ring oscillator operates at 1 GHz and ILFD is supposed to provide the operation of divide-by-2 (/2). The structure of ILFD is designed to be similar with that of oscillator in order to adjust the frequency alignment between the oscillator and ILFD. CML frequency divider is applied as the 2nd-stage divider. The proposed frequency divider is applied in the conventional PLL which is integrated with 0.18 μm CMOS process. Simulation test shows that the /2 ILFD and /16 CML frequency divider operates accurately and the total power consumption of 32 mW is obtained at the input frequency of 1 GHz.","PeriodicalId":423850,"journal":{"name":"2018 IEEE 22nd Workshop on Signal and Power Integrity (SPI)","volume":"97 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134092251","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-05-22DOI: 10.1109/SAPIW.2018.8401654
Y. F. Shen
The demand for connected smart cars has grown exponentially in the past few years. To meet consumer's digital lifestyle needs and take part in this emerging market, microprocessor companies, such as Intel®, are shifting a focus to automotive SoC package designs. This paper examines the differences in design specifications between automotive and mobile and the implications to Power Integrity. The automotive use case, temperature cycling, and reliability qualifications are more stringent and add to the Power Integrity challenges. Frequency and time domain simulations were performed for all Fully Integrated Voltage Regulator (FIVR) and non-FIVR rails and compared between automotive vs. mobile.
{"title":"Power integrity challenges of re-designing a mobile SoC with fully integrated voltage regulator to IoT applications","authors":"Y. F. Shen","doi":"10.1109/SAPIW.2018.8401654","DOIUrl":"https://doi.org/10.1109/SAPIW.2018.8401654","url":null,"abstract":"The demand for connected smart cars has grown exponentially in the past few years. To meet consumer's digital lifestyle needs and take part in this emerging market, microprocessor companies, such as Intel®, are shifting a focus to automotive SoC package designs. This paper examines the differences in design specifications between automotive and mobile and the implications to Power Integrity. The automotive use case, temperature cycling, and reliability qualifications are more stringent and add to the Power Integrity challenges. Frequency and time domain simulations were performed for all Fully Integrated Voltage Regulator (FIVR) and non-FIVR rails and compared between automotive vs. mobile.","PeriodicalId":423850,"journal":{"name":"2018 IEEE 22nd Workshop on Signal and Power Integrity (SPI)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132882697","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-05-22DOI: 10.1109/SAPIW.2018.8401674
A. Tsuchiya, Akitaka Hiratsuka, Toshiyuki Inoue, K. Kishine, H. Onodera
This paper discusses power/ground noise induced by on-chip multi-layered inductors. Employing multi-layered inductors instead of spiral inductors is an effective choice for area-efficient bandwidth enhancement. However the impact of the coupling between multi-layered inductors and underlying circuit is still not clear. We evaluate inductive/capacitive coupling and the impact on the power and the signal integrity. Electromagnetic simulation and circuit simulation show that dense power/ground structure makes the impact of coupling small. The peak-to-peak noise voltage becomes less than 5 mV against 1 V aggressor swing.
{"title":"Impact of on-chip multi-layered inductor on signal and power integrity of underlying power-ground net","authors":"A. Tsuchiya, Akitaka Hiratsuka, Toshiyuki Inoue, K. Kishine, H. Onodera","doi":"10.1109/SAPIW.2018.8401674","DOIUrl":"https://doi.org/10.1109/SAPIW.2018.8401674","url":null,"abstract":"This paper discusses power/ground noise induced by on-chip multi-layered inductors. Employing multi-layered inductors instead of spiral inductors is an effective choice for area-efficient bandwidth enhancement. However the impact of the coupling between multi-layered inductors and underlying circuit is still not clear. We evaluate inductive/capacitive coupling and the impact on the power and the signal integrity. Electromagnetic simulation and circuit simulation show that dense power/ground structure makes the impact of coupling small. The peak-to-peak noise voltage becomes less than 5 mV against 1 V aggressor swing.","PeriodicalId":423850,"journal":{"name":"2018 IEEE 22nd Workshop on Signal and Power Integrity (SPI)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125323723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-05-22DOI: 10.1109/SAPIW.2018.8401651
J. N. Tripathi, A. Jain, M. Marinković, R. Achar
Power supply induced jitter (PSIJ) is becoming increasingly critical in modern high-speed and lower-power designs. In this paper, a semi-analytical method is presented to estimate the PSIJ in the presence of both the transmission media as well as the ground bounce. For this purpose, recently developed EMPSIJ method is extended to include the effects of both the ground bounce and the transmission line discontinuities. Results are presented by considering a voltage mode driver circuit and are compared against the conventional simulations (commercial tools) in a 55nm technology of STMicroelectronics. The new method while providing comparable accuracy yields significant speed-up.
{"title":"Analysis of PSIJ in the presence of both ground-bounce and transmission media","authors":"J. N. Tripathi, A. Jain, M. Marinković, R. Achar","doi":"10.1109/SAPIW.2018.8401651","DOIUrl":"https://doi.org/10.1109/SAPIW.2018.8401651","url":null,"abstract":"Power supply induced jitter (PSIJ) is becoming increasingly critical in modern high-speed and lower-power designs. In this paper, a semi-analytical method is presented to estimate the PSIJ in the presence of both the transmission media as well as the ground bounce. For this purpose, recently developed EMPSIJ method is extended to include the effects of both the ground bounce and the transmission line discontinuities. Results are presented by considering a voltage mode driver circuit and are compared against the conventional simulations (commercial tools) in a 55nm technology of STMicroelectronics. The new method while providing comparable accuracy yields significant speed-up.","PeriodicalId":423850,"journal":{"name":"2018 IEEE 22nd Workshop on Signal and Power Integrity (SPI)","volume":" 14","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133020601","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-05-22DOI: 10.1109/SAPIW.2018.8401669
Josip Bačmaga, R. Blečić, R. Gillon, A. Barić
A lumped-element model of a 50-mΩ, 10-W surface-mount current-sense resistor is extracted and its parameters are presented. The model parameters are optimized to fit the measured impedance characteristics. The extracted model is valid up to 100 MHz and it consists of frequency-independent components. The model is validated by measurements and the reproduced current waveform is compared to the one obtained by a commercial large-bandwidth current sensor. The comparison of the extracted model and nominal 50-mΩ model is presented. The extracted model shows significantly better correlation to the commercial current sensor than the nominal 50-mΩ model, especially for larger currents and higher frequencies.
{"title":"Modelling and validation of high-current surface-mount current-sense resistor","authors":"Josip Bačmaga, R. Blečić, R. Gillon, A. Barić","doi":"10.1109/SAPIW.2018.8401669","DOIUrl":"https://doi.org/10.1109/SAPIW.2018.8401669","url":null,"abstract":"A lumped-element model of a 50-mΩ, 10-W surface-mount current-sense resistor is extracted and its parameters are presented. The model parameters are optimized to fit the measured impedance characteristics. The extracted model is valid up to 100 MHz and it consists of frequency-independent components. The model is validated by measurements and the reproduced current waveform is compared to the one obtained by a commercial large-bandwidth current sensor. The comparison of the extracted model and nominal 50-mΩ model is presented. The extracted model shows significantly better correlation to the commercial current sensor than the nominal 50-mΩ model, especially for larger currents and higher frequencies.","PeriodicalId":423850,"journal":{"name":"2018 IEEE 22nd Workshop on Signal and Power Integrity (SPI)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132963183","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-05-01DOI: 10.1109/SAPIW.2018.8401660
A. Maffucci, L. Ferrigno, M. Migliore, Daniele Pinchera, F. Schettino, F. Micciulla, S. Bellucci, S. Maksimenko, A. Paddubskaya
This paper deals with the electrical characterization of a graphene-based material that can be proposed for realizing novel interposers to improve the electrical performance of the electronic packages. The material is a low-cost version of the graphene, realized with commercial graphene nanoplatelets, and thus potentially suitable for a large mass production. An electrical characterization of its complex permittivity in the microwave range is here provided, by using a technique based on the measurement of the scattering parameters on a microstrip-like test vehicle. A Drude model is used to retrieve the values of the equivalent complex permittivity. The results demonstrate that this material may outperform the silicon so far used for interposers.
{"title":"Electrical properties of a graphene nanoplatelets composite as interposer for electronic packages","authors":"A. Maffucci, L. Ferrigno, M. Migliore, Daniele Pinchera, F. Schettino, F. Micciulla, S. Bellucci, S. Maksimenko, A. Paddubskaya","doi":"10.1109/SAPIW.2018.8401660","DOIUrl":"https://doi.org/10.1109/SAPIW.2018.8401660","url":null,"abstract":"This paper deals with the electrical characterization of a graphene-based material that can be proposed for realizing novel interposers to improve the electrical performance of the electronic packages. The material is a low-cost version of the graphene, realized with commercial graphene nanoplatelets, and thus potentially suitable for a large mass production. An electrical characterization of its complex permittivity in the microwave range is here provided, by using a technique based on the measurement of the scattering parameters on a microstrip-like test vehicle. A Drude model is used to retrieve the values of the equivalent complex permittivity. The results demonstrate that this material may outperform the silicon so far used for interposers.","PeriodicalId":423850,"journal":{"name":"2018 IEEE 22nd Workshop on Signal and Power Integrity (SPI)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126777405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-05-01DOI: 10.1109/SAPIW.2018.8401679
R. Trinchero, F. Canavero
This paper presents a preliminary application of the support vector machine regression to the modeling of the eye diagram heights in high speed links for design and optimization purposes. The support vector machine regression is applied to generate a compact surrogate model of the eye diagram heights at a specific node of the link from a set of randomly selected training samples. The surrogate can be suitably adopted both for design optimization and for stochastic analysis. The feasibility and accuracy of the surrogate model calculated via the support vector machine regression are investigated on a realistic high-speed communication channel.
{"title":"Modeling of eye diagram height in high-speed links via support vector machine","authors":"R. Trinchero, F. Canavero","doi":"10.1109/SAPIW.2018.8401679","DOIUrl":"https://doi.org/10.1109/SAPIW.2018.8401679","url":null,"abstract":"This paper presents a preliminary application of the support vector machine regression to the modeling of the eye diagram heights in high speed links for design and optimization purposes. The support vector machine regression is applied to generate a compact surrogate model of the eye diagram heights at a specific node of the link from a set of randomly selected training samples. The surrogate can be suitably adopted both for design optimization and for stochastic analysis. The feasibility and accuracy of the surrogate model calculated via the support vector machine regression are investigated on a realistic high-speed communication channel.","PeriodicalId":423850,"journal":{"name":"2018 IEEE 22nd Workshop on Signal and Power Integrity (SPI)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122113765","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-05-01DOI: 10.1109/SAPIW.2018.8401642
A. Menshov, V. Okhmatovski
Fast direct planar full-wave electromagnetic analysis of microstrip structures embedded in multilayered medium is demonstrated. The impedance matrix of the Moment Method is stored in compressed format of a hierarchical matrix. The matrix equation is subsequently solved using hierarchical LU decomposition. Accuracy of analysis in a broad range of frequencies is demonstrated. Compression rate and accuracy of the computed reflection loss for a microstrip structure situated in multilayered media are presented as a function of tolerance in SVD of rank-deficient blocks of the hierarchical matrix.
{"title":"Fast direct full-wave electromagnetic analysis of planar circuits embedded in multilayered media","authors":"A. Menshov, V. Okhmatovski","doi":"10.1109/SAPIW.2018.8401642","DOIUrl":"https://doi.org/10.1109/SAPIW.2018.8401642","url":null,"abstract":"Fast direct planar full-wave electromagnetic analysis of microstrip structures embedded in multilayered medium is demonstrated. The impedance matrix of the Moment Method is stored in compressed format of a hierarchical matrix. The matrix equation is subsequently solved using hierarchical LU decomposition. Accuracy of analysis in a broad range of frequencies is demonstrated. Compression rate and accuracy of the computed reflection loss for a microstrip structure situated in multilayered media are presented as a function of tolerance in SVD of rank-deficient blocks of the hierarchical matrix.","PeriodicalId":423850,"journal":{"name":"2018 IEEE 22nd Workshop on Signal and Power Integrity (SPI)","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126114078","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-05-01DOI: 10.1109/SAPIW.2018.8401657
Felipe de Jesús Leal-Romo, Jose L. Silva-Perales, Carlos López-Limón, J. Rayas-Sánchez
Every new computer server introduced to the market aims at delivering the best tradeoff between performance and power consumption. This goal is crucial in the case of servers for cloud computing hardware infrastructure. In this context, power delivery (PD) experts are adopting higher frequency switching voltage regulators (VR) to reduce platform's cost as well as total cost of ownership (TCO). Because of this fact, the real estate of components, such as voltage regulators and output inductors, is shrinking as VR frequency increases. As a consequence, achieving the best performance of the VR implies looking into phase shedding schemes, as well as EM coupled inductor design, among other techniques, to mitigate power losses. This paper focuses on the study of the best angle arrangement possible for high frequency VR applications, by exploring angle settings under light load scenarios, aiming to minimize VR's power loss and output's voltage ripple.
{"title":"Optimizing phase settings of high-frequency voltage regulators for power delivery applications","authors":"Felipe de Jesús Leal-Romo, Jose L. Silva-Perales, Carlos López-Limón, J. Rayas-Sánchez","doi":"10.1109/SAPIW.2018.8401657","DOIUrl":"https://doi.org/10.1109/SAPIW.2018.8401657","url":null,"abstract":"Every new computer server introduced to the market aims at delivering the best tradeoff between performance and power consumption. This goal is crucial in the case of servers for cloud computing hardware infrastructure. In this context, power delivery (PD) experts are adopting higher frequency switching voltage regulators (VR) to reduce platform's cost as well as total cost of ownership (TCO). Because of this fact, the real estate of components, such as voltage regulators and output inductors, is shrinking as VR frequency increases. As a consequence, achieving the best performance of the VR implies looking into phase shedding schemes, as well as EM coupled inductor design, among other techniques, to mitigate power losses. This paper focuses on the study of the best angle arrangement possible for high frequency VR applications, by exploring angle settings under light load scenarios, aiming to minimize VR's power loss and output's voltage ripple.","PeriodicalId":423850,"journal":{"name":"2018 IEEE 22nd Workshop on Signal and Power Integrity (SPI)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121030095","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-05-01DOI: 10.1109/SAPIW.2018.8401675
B. Nouri, M. Nakhla
Conventional sensitivity analysis based on model-order reduction techniques guarantee the passivity and, consequently, the stability of the reduced sensitivity circuit provided that the original circuit is passive. This excludes a large class of circuits that are stable but not necessarily passive. In this paper, an efficient model-order reduction method is presented for computing sensitivity information of active stable circuits with respect to arbitrary parameters. The proposed algorithm guarantees the asymptotic stability of the reduced sensitivity model by construction.
{"title":"Reduced-order model for time-domain sensitivity analysis of active circuits","authors":"B. Nouri, M. Nakhla","doi":"10.1109/SAPIW.2018.8401675","DOIUrl":"https://doi.org/10.1109/SAPIW.2018.8401675","url":null,"abstract":"Conventional sensitivity analysis based on model-order reduction techniques guarantee the passivity and, consequently, the stability of the reduced sensitivity circuit provided that the original circuit is passive. This excludes a large class of circuits that are stable but not necessarily passive. In this paper, an efficient model-order reduction method is presented for computing sensitivity information of active stable circuits with respect to arbitrary parameters. The proposed algorithm guarantees the asymptotic stability of the reduced sensitivity model by construction.","PeriodicalId":423850,"journal":{"name":"2018 IEEE 22nd Workshop on Signal and Power Integrity (SPI)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117145980","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：