Pub Date : 2018-03-16DOI: 10.1109/CONECCT.2018.8482376
P. Kushwaha, H. Agarwal, Chetan Kumar Dabhi, Yen-Kai Lin, J. Duarte, C. Hu, Y. Chauhan
A physics-based unified flicker noise model for FDSOI transistor is proposed. Flicker noise power spectral density (PSD) at the front and back interfaces are calculated using oxide-trap-induced carrier number (CNF) and correlated surface mobility fluctuation (CMF) mechanisms. The model predicts correct flicker noise behavior from weak inversion region to strong inversion region for a wide range of the front and backgate voltages. The proposed model is computationally efficient and implementable in any SPICE model for circuit simulations.
{"title":"A Unified Flicker Noise Model for FDSOI MOSFETs Including Back-bias Effect","authors":"P. Kushwaha, H. Agarwal, Chetan Kumar Dabhi, Yen-Kai Lin, J. Duarte, C. Hu, Y. Chauhan","doi":"10.1109/CONECCT.2018.8482376","DOIUrl":"https://doi.org/10.1109/CONECCT.2018.8482376","url":null,"abstract":"A physics-based unified flicker noise model for FDSOI transistor is proposed. Flicker noise power spectral density (PSD) at the front and back interfaces are calculated using oxide-trap-induced carrier number (CNF) and correlated surface mobility fluctuation (CMF) mechanisms. The model predicts correct flicker noise behavior from weak inversion region to strong inversion region for a wide range of the front and backgate voltages. The proposed model is computationally efficient and implementable in any SPICE model for circuit simulations.","PeriodicalId":430389,"journal":{"name":"2018 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127289090","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-16DOI: 10.1109/CONECCT.2018.8482367
I. Mahapatra, Utkarsh Agarwal, S. Nandy
As the complexity of circuit design increases, verification of these circuits through simulation also becomes extremely challenging. This creates a bottleneck in the IC design process. Distributed simulation is one way of solving this problem where the simulation workload is distributed among the parallel processors involved in the simulation. However the design has to be carefully partitioned for this purpose. In order to perform distributed simulation, many efficient partitioning algorithms have been proposed till date. These algorithms mostly partition gate level netlist or logic circuits and reduces inter-processor communication by minimizing cutsize for a given constraint of load balance. In this paper, we present two different partitioning schemes for performing distributed simulation. They are: a Discrete Particle Swarm optimization (DPSO) based partitioning algorithm (DPSO-PA) and an effective partitioning heuristic. These algorithms partitions Data Flow Graph (DFG) for a recently proposed Coarse Grained Reconfigurable Array assisted Hardware Accelerator (CGRA-HA). We also propose an improved version of the original DPSO methodology through careful selection of initial partition sets. It is found that the proposed heuristic based partitioning algorithm outperforms the modified DPSO-PA in terms of lesser cut-edges.
{"title":"DFG Partitioning Algorithms for Coarse Grained Reconfigurable Array Assisted RTL Simulation Accelerators","authors":"I. Mahapatra, Utkarsh Agarwal, S. Nandy","doi":"10.1109/CONECCT.2018.8482367","DOIUrl":"https://doi.org/10.1109/CONECCT.2018.8482367","url":null,"abstract":"As the complexity of circuit design increases, verification of these circuits through simulation also becomes extremely challenging. This creates a bottleneck in the IC design process. Distributed simulation is one way of solving this problem where the simulation workload is distributed among the parallel processors involved in the simulation. However the design has to be carefully partitioned for this purpose. In order to perform distributed simulation, many efficient partitioning algorithms have been proposed till date. These algorithms mostly partition gate level netlist or logic circuits and reduces inter-processor communication by minimizing cutsize for a given constraint of load balance. In this paper, we present two different partitioning schemes for performing distributed simulation. They are: a Discrete Particle Swarm optimization (DPSO) based partitioning algorithm (DPSO-PA) and an effective partitioning heuristic. These algorithms partitions Data Flow Graph (DFG) for a recently proposed Coarse Grained Reconfigurable Array assisted Hardware Accelerator (CGRA-HA). We also propose an improved version of the original DPSO methodology through careful selection of initial partition sets. It is found that the proposed heuristic based partitioning algorithm outperforms the modified DPSO-PA in terms of lesser cut-edges.","PeriodicalId":430389,"journal":{"name":"2018 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130661232","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-16DOI: 10.1109/CONECCT.2018.8482368
A. Gupta, R. Sankara Prasad, L. Srivani, D. Thirugnana Murthy, B. Panigrahi, G. Raghavan
A flexible and low-cost Coincidence Counting Unit (CCU) with customizable features that are software selectable is designed and developed for the use in various experiments of quantum information and quantum metrology. A digital logic-based implementation approach using Field Programmable Gate Array is followed with specific emphasis on reducing the time for coincidence events of photons and making it easily scalable. In this paper, an 8-channel CCU with software configurable features such as coincidence window selection (in increment of 0.54 ns) and 8-fold coincidences (up to 4 sets) at a time has been implemented.
{"title":"Design and Development of Flexible and Low-Cost Coincidence Counting Unit","authors":"A. Gupta, R. Sankara Prasad, L. Srivani, D. Thirugnana Murthy, B. Panigrahi, G. Raghavan","doi":"10.1109/CONECCT.2018.8482368","DOIUrl":"https://doi.org/10.1109/CONECCT.2018.8482368","url":null,"abstract":"A flexible and low-cost Coincidence Counting Unit (CCU) with customizable features that are software selectable is designed and developed for the use in various experiments of quantum information and quantum metrology. A digital logic-based implementation approach using Field Programmable Gate Array is followed with specific emphasis on reducing the time for coincidence events of photons and making it easily scalable. In this paper, an 8-channel CCU with software configurable features such as coincidence window selection (in increment of 0.54 ns) and 8-fold coincidences (up to 4 sets) at a time has been implemented.","PeriodicalId":430389,"journal":{"name":"2018 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123489286","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-16DOI: 10.1109/CONECCT.2018.8482384
Ball Mukund Mani Tripathi, Shyama P Das
In this paper, we proposed a vertical channel GaN FET without junctions particularly suitable for power application. It offers less fabrication complexity and cost with enhanced device characteristics as compared to the referenced device. GaN vertical channel junction field effect transistor (VC-JFET) of equal dimension and doping concentrations is considered as the reference device. A comprehensive simulation study of parameter variation on proposed device characteristics has been performed and studied. The study envisaged the impact of lateral and vertical dimensions and doping on various device characteristics like current, ON resistance ($R_{ON}$), breakdown voltage, trans-conductance (gm), capacitance, and unity gain frequency $(f_{T})$.The obtained results and their effect on device characteristics have been thoroughly analyzed.
{"title":"Vertical Channel GaN Field Effect Transistor Without Junction for High Power Application","authors":"Ball Mukund Mani Tripathi, Shyama P Das","doi":"10.1109/CONECCT.2018.8482384","DOIUrl":"https://doi.org/10.1109/CONECCT.2018.8482384","url":null,"abstract":"In this paper, we proposed a vertical channel GaN FET without junctions particularly suitable for power application. It offers less fabrication complexity and cost with enhanced device characteristics as compared to the referenced device. GaN vertical channel junction field effect transistor (VC-JFET) of equal dimension and doping concentrations is considered as the reference device. A comprehensive simulation study of parameter variation on proposed device characteristics has been performed and studied. The study envisaged the impact of lateral and vertical dimensions and doping on various device characteristics like current, ON resistance ($R_{ON}$), breakdown voltage, trans-conductance (gm), capacitance, and unity gain frequency $(f_{T})$.The obtained results and their effect on device characteristics have been thoroughly analyzed.","PeriodicalId":430389,"journal":{"name":"2018 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125280312","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-16DOI: 10.1109/CONECCT.2018.8482371
Md. Maksudur Rahman, M M Mahmudunnabi Shuvo, M. Zaber, Amin Masud Ali
Traffic congestion is one of the most alarming problems of Dhaka, the capital of Bangladesh. However, not much work had been done on traffic pattern modeling for Dhaka city. In this paper, we analyze traffic intensity pattern computed from GPS data. The data contains traffic intensity information for 11,769 road segments over 15 days. We analyze the impact of marketplaces, number of road intersections, and having rickshaw free roads on the traffic intensity. In order to analyze the traffic pattern at a macroscopic level, we analyze the traffic pattern of the 13 zones of the city proposed by RAJUK, the authority responsible for the development of Dhaka. For each zone we investigate the impact of a number of different factors, e.g., land use, number of bus routes, number of road intersections, on the traffic intensity.
{"title":"Traffic Pattern Analysis from GPS Data: A Case Study of Dhaka City","authors":"Md. Maksudur Rahman, M M Mahmudunnabi Shuvo, M. Zaber, Amin Masud Ali","doi":"10.1109/CONECCT.2018.8482371","DOIUrl":"https://doi.org/10.1109/CONECCT.2018.8482371","url":null,"abstract":"Traffic congestion is one of the most alarming problems of Dhaka, the capital of Bangladesh. However, not much work had been done on traffic pattern modeling for Dhaka city. In this paper, we analyze traffic intensity pattern computed from GPS data. The data contains traffic intensity information for 11,769 road segments over 15 days. We analyze the impact of marketplaces, number of road intersections, and having rickshaw free roads on the traffic intensity. In order to analyze the traffic pattern at a macroscopic level, we analyze the traffic pattern of the 13 zones of the city proposed by RAJUK, the authority responsible for the development of Dhaka. For each zone we investigate the impact of a number of different factors, e.g., land use, number of bus routes, number of road intersections, on the traffic intensity.","PeriodicalId":430389,"journal":{"name":"2018 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT)","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121494318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-01DOI: 10.1109/CONECCT.2018.8482381
Arjun Singh Chauhan, Chauhan Vineet Sahula, A. S. Mandal
The Physical Unclonable Functions have been widely used to provide software as well as hardware security for the cyber-physical systems. They are used for performing significant tasks such as generating cryptography keys, device authentication, securing against IP Piracy; and have also been used to produce root of Trust. However, they lack in reliability issues. We present a novel approach for improving the reliability of Ring Oscillator PUF with the minimum area concerning LUTs. We use variation-aware method to find out the more suitable location for PUF mapping, thus leading to enhanced the PUF reliability. We have designed and tested proposed methodology on Xilinx -7 Series FPGAs. The proposed approach achieves higher reliability of 99.7%, which is significant improvement compared to existing ROPUF methods.
{"title":"Novel Placement Bias For Realizing Highly Reliable Physical Unclonable Functions on FPGA","authors":"Arjun Singh Chauhan, Chauhan Vineet Sahula, A. S. Mandal","doi":"10.1109/CONECCT.2018.8482381","DOIUrl":"https://doi.org/10.1109/CONECCT.2018.8482381","url":null,"abstract":"The Physical Unclonable Functions have been widely used to provide software as well as hardware security for the cyber-physical systems. They are used for performing significant tasks such as generating cryptography keys, device authentication, securing against IP Piracy; and have also been used to produce root of Trust. However, they lack in reliability issues. We present a novel approach for improving the reliability of Ring Oscillator PUF with the minimum area concerning LUTs. We use variation-aware method to find out the more suitable location for PUF mapping, thus leading to enhanced the PUF reliability. We have designed and tested proposed methodology on Xilinx -7 Series FPGAs. The proposed approach achieves higher reliability of 99.7%, which is significant improvement compared to existing ROPUF methods.","PeriodicalId":430389,"journal":{"name":"2018 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122340430","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-01DOI: 10.1109/CONECCT.2018.8482399
Dev Narayan Yadav, P. L. Thangkhiew
Current von-Neumann computing technology demands high capacity storage and high communication bandwidth to access data between storage and processing units. Memristor is a promising device that has the desirable properties using which in-memory computing can be performed in the storage unit. These properties of memristors can overcome the bottleneck faced by current von-Neumann architecture. In this paper, we provide a reconfigurable implementation of a 1-bit Arithmetic Logical Unit (ALU) using the memristor crossbar array. Enabling the configuration in system hardware will provide the functionality to use the same module of the system for multiple purposes and change the functionality of the module as per the requirement. The proposed design of the ALU provides functionality to perform the operations in the single module (memristor crossbar) and it is capable to add new operations as per the requirements. For the design of such ALUs, we use the MAGIC NOT and NOR gates. To validate the design we perform SPICE simulation of a half adder using Cadence Virtuoso.
{"title":"Towards an In-Memory Reconfiguration of Arithmetic Logical Unit using Memristor Crossbar Array","authors":"Dev Narayan Yadav, P. L. Thangkhiew","doi":"10.1109/CONECCT.2018.8482399","DOIUrl":"https://doi.org/10.1109/CONECCT.2018.8482399","url":null,"abstract":"Current von-Neumann computing technology demands high capacity storage and high communication bandwidth to access data between storage and processing units. Memristor is a promising device that has the desirable properties using which in-memory computing can be performed in the storage unit. These properties of memristors can overcome the bottleneck faced by current von-Neumann architecture. In this paper, we provide a reconfigurable implementation of a 1-bit Arithmetic Logical Unit (ALU) using the memristor crossbar array. Enabling the configuration in system hardware will provide the functionality to use the same module of the system for multiple purposes and change the functionality of the module as per the requirement. The proposed design of the ALU provides functionality to perform the operations in the single module (memristor crossbar) and it is capable to add new operations as per the requirements. For the design of such ALUs, we use the MAGIC NOT and NOR gates. To validate the design we perform SPICE simulation of a half adder using Cadence Virtuoso.","PeriodicalId":430389,"journal":{"name":"2018 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT)","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128685883","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-01DOI: 10.1109/CONECCT.2018.8482397
Anurag Barthwal, D. Acharya
Constant monitoring of air quality is required in a smart city to improve human health and quality of life. Major cities of the world measure and analyze air quality and pollutant concentration with the help of few static air quality monitoring stations. Roads are arteries of a city and used by majority of the population for commuting and transportation. A low cost air quality sensing system installed in a vehicle that commutes through different routes of the city gives a finegrained real time information about the state of pollutants and air quality in different parts of the city. In this work, we have developed an environment sensing, location aware, Internet of Things system to monitor, collect and analyze the presence of different environmental parameters in real time. Pollution route map of the routes traversed by the vehicle with sensor-setup has been created which can be accessed by mobile users in other vehicles. As air pollution is highly location dependent, there is a need to predict air quality at places for which air quality information is not known. Multiple Linear Regression has been used to used to predict AQI levels from historic data for such locations.
{"title":"An Internet of Things System for Sensing, Analysis & Forecasting Urban Air Quality","authors":"Anurag Barthwal, D. Acharya","doi":"10.1109/CONECCT.2018.8482397","DOIUrl":"https://doi.org/10.1109/CONECCT.2018.8482397","url":null,"abstract":"Constant monitoring of air quality is required in a smart city to improve human health and quality of life. Major cities of the world measure and analyze air quality and pollutant concentration with the help of few static air quality monitoring stations. Roads are arteries of a city and used by majority of the population for commuting and transportation. A low cost air quality sensing system installed in a vehicle that commutes through different routes of the city gives a finegrained real time information about the state of pollutants and air quality in different parts of the city. In this work, we have developed an environment sensing, location aware, Internet of Things system to monitor, collect and analyze the presence of different environmental parameters in real time. Pollution route map of the routes traversed by the vehicle with sensor-setup has been created which can be accessed by mobile users in other vehicles. As air pollution is highly location dependent, there is a need to predict air quality at places for which air quality information is not known. Multiple Linear Regression has been used to used to predict AQI levels from historic data for such locations.","PeriodicalId":430389,"journal":{"name":"2018 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130842203","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-01DOI: 10.1109/CONECCT.2018.8482383
Bheemappa Halavar, B. Talawar
With the increase in number and complexity of cores and components in CMPs and SoCs, a highly structured and efficient on-chip communication network is required to achieve high-performance and scalability. Network on Chips(NoC) emerged as the reliable communication framework in CMPs and SoCs. Many 2-D NoC architectures have been proposed for efficient on-chip communication. In this paper, we explore the design space of 3D NoCs using floorplan driven wire lengths and link delay estimation. We analyse the performance and cost of 2D and two 3D variants of the Mesh topology by injecting two synthetic traffic pattern for varying buffer space and floorplan based delays were considered to for the experiments. Results of our experiments show that for the injection rates from 0.02 to 0.2 the average network latency of a 4layer 3D Mesh is reduced up to 54% compared to its 2D counterpart. The on chip communication performance improved up to 2.2× and 3.1× in 4-layer 3D Mesh compare to 2D Mesh with uniform and transpose traffic patterns respectively.
{"title":"Accurate Performance Analysis of 3D Mesh Network on Chip Architectures","authors":"Bheemappa Halavar, B. Talawar","doi":"10.1109/CONECCT.2018.8482383","DOIUrl":"https://doi.org/10.1109/CONECCT.2018.8482383","url":null,"abstract":"With the increase in number and complexity of cores and components in CMPs and SoCs, a highly structured and efficient on-chip communication network is required to achieve high-performance and scalability. Network on Chips(NoC) emerged as the reliable communication framework in CMPs and SoCs. Many 2-D NoC architectures have been proposed for efficient on-chip communication. In this paper, we explore the design space of 3D NoCs using floorplan driven wire lengths and link delay estimation. We analyse the performance and cost of 2D and two 3D variants of the Mesh topology by injecting two synthetic traffic pattern for varying buffer space and floorplan based delays were considered to for the experiments. Results of our experiments show that for the injection rates from 0.02 to 0.2 the average network latency of a 4layer 3D Mesh is reduced up to 54% compared to its 2D counterpart. The on chip communication performance improved up to 2.2× and 3.1× in 4-layer 3D Mesh compare to 2D Mesh with uniform and transpose traffic patterns respectively.","PeriodicalId":430389,"journal":{"name":"2018 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT)","volume":"124 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131119408","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-03-01DOI: 10.1109/CONECCT.2018.8482398
S. D, P. Shankapal
There is a rising need to understand how the brain processes depression. This paper provides a comparative analysis of fMRI from ND and MDD participants on subjecting them to audio stimuli. The analysis infers that with negligible activation in the ACC and striatum, MDD participants are less capable of accurately classifying and processing emotions.
{"title":"A Comparative Audio Stimulus - fMRI study of Major Depressive Disorder(MDD) and Never Depressed (ND) Subjects","authors":"S. D, P. Shankapal","doi":"10.1109/CONECCT.2018.8482398","DOIUrl":"https://doi.org/10.1109/CONECCT.2018.8482398","url":null,"abstract":"There is a rising need to understand how the brain processes depression. This paper provides a comparative analysis of fMRI from ND and MDD participants on subjecting them to audio stimuli. The analysis infers that with negligible activation in the ACC and striatum, MDD participants are less capable of accurately classifying and processing emotions.","PeriodicalId":430389,"journal":{"name":"2018 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133071529","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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