New attacks are emerging that target the Internet infrastructure. Modern routers use programmable network processors that may be exploited by merely sending suitably crafted data packets into a network. Hardware monitors that are co-located with processor cores can detect attacks that change processor behavior with high probability. In this paper, we present a solution to the problem of secure, dynamic installation of hardware monitoring graphs on these devices. We also address the problem of how to overcome the homogeneity of a network with many identical devices, where a successful attack, albeit possible only with small probability, may have devastating effects.
{"title":"System-level security for network processors with hardware monitors","authors":"Kekai Hu, T. Wolf, Thiago Teixeira, R. Tessier","doi":"10.1145/2593069.2593226","DOIUrl":"https://doi.org/10.1145/2593069.2593226","url":null,"abstract":"New attacks are emerging that target the Internet infrastructure. Modern routers use programmable network processors that may be exploited by merely sending suitably crafted data packets into a network. Hardware monitors that are co-located with processor cores can detect attacks that change processor behavior with high probability. In this paper, we present a solution to the problem of secure, dynamic installation of hardware monitoring graphs on these devices. We also address the problem of how to overcome the homogeneity of a network with many identical devices, where a successful attack, albeit possible only with small probability, may have devastating effects.","PeriodicalId":433816,"journal":{"name":"2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121580347","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Monica Farkash, Bryan G. Hickerson, Michael L. Behm
This paper addresses the challenges of minimizing the time and resources required to validate the changes between two Hardware (HW) model iterations of the same design. It introduces CLTV (Coverage Learned Targeted Validation), an automatic framework which learns during the verification process of the HW and uses the learned information to target the areas of the design that are affected by the incremental HW model iterations. Our paper defines new concepts, presents our implementation of the supporting algorithms, and shows actual results on an IBM POWER8 processor with outstanding results.
{"title":"Coverage Learned Targeted Validation for incremental HW changes","authors":"Monica Farkash, Bryan G. Hickerson, Michael L. Behm","doi":"10.1145/2593069.2593114","DOIUrl":"https://doi.org/10.1145/2593069.2593114","url":null,"abstract":"This paper addresses the challenges of minimizing the time and resources required to validate the changes between two Hardware (HW) model iterations of the same design. It introduces CLTV (Coverage Learned Targeted Validation), an automatic framework which learns during the verification process of the HW and uses the learned information to target the areas of the design that are affected by the incremental HW model iterations. Our paper defines new concepts, presents our implementation of the supporting algorithms, and shows actual results on an IBM POWER8 processor with outstanding results.","PeriodicalId":433816,"journal":{"name":"2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125233138","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We propose a post-fabrication calibration technique for RF circuits that is performed during production testing with minimum extra cost. Calibration is enabled by equipping the circuit with tuning knobs and sensors. Optimal tuning knob identification is achieved in one-shot based on a single test step that involves measuring the sensor outputs once. For this purpose, we rely on variation-aware sensors which provide measurements that remain invariant under tuning knob changes. As an auxiliary benefit, the variation-aware sensors are non-intrusive and totally transparent to the circuit. The technique is demonstrated on a 65nm RF power amplifier.
{"title":"One-shot calibration of rf circuits based on non-intrusive sensors","authors":"M. Andraud, H. Stratigopoulos, E. Simeu","doi":"10.1145/2593069.2593174","DOIUrl":"https://doi.org/10.1145/2593069.2593174","url":null,"abstract":"We propose a post-fabrication calibration technique for RF circuits that is performed during production testing with minimum extra cost. Calibration is enabled by equipping the circuit with tuning knobs and sensors. Optimal tuning knob identification is achieved in one-shot based on a single test step that involves measuring the sensor outputs once. For this purpose, we rely on variation-aware sensors which provide measurements that remain invariant under tuning knob changes. As an auxiliary benefit, the variation-aware sensors are non-intrusive and totally transparent to the circuit. The technique is demonstrated on a 65nm RF power amplifier.","PeriodicalId":433816,"journal":{"name":"2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122069337","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
G. Rodríguez-Navas, C. Seceleanu, H. Hansson, M. Nyberg, Oscar Ljungkrantz, Henrik Lönn
ISO 26262 is the new standard for automotive functional safety. This standard identifies major process steps across a large number of system stages as well as safety-related artifacts required as input and output of these steps. The VeriSpec project intends to identify the main challenges for the adoption of ISO 26262 by the heavy-vehicle industry and to provide useful and industrially relevant “components” (methods, tools etc.) required by the standard. The project work targets two main research goals: (i) requirement formalization support, including a usable front-end for specifying requirements by using patterns, and (ii) formal analysis of realizations in form of architectural models at various levels of abstraction, by model-checking the formal representations of the latter. In this paper, we present the current challenges facing industry and justifying VeriSpec, together with a preliminary roadmap for the research.
ISO 26262是汽车功能安全的新标准。该标准确定了跨越大量系统阶段的主要过程步骤，以及作为这些步骤的输入和输出所需的与安全相关的工件。VeriSpec项目旨在确定重型车辆行业采用ISO 26262的主要挑战，并提供标准所需的有用和工业相关的“组件”(方法，工具等)。该项目工作以两个主要的研究目标为目标:(i)需求形式化支持，包括通过使用模式来指定需求的可用前端，以及(ii)通过对后者的形式化表示进行模型检查，以各种抽象级别的体系结构模型的形式对实现进行形式化分析。在本文中，我们提出了当前行业面临的挑战，并证明了VeriSpec的合理性，以及研究的初步路线图。
{"title":"Automated specification and verification of functional safety in heavy-vehicles: The VeriSpec approach","authors":"G. Rodríguez-Navas, C. Seceleanu, H. Hansson, M. Nyberg, Oscar Ljungkrantz, Henrik Lönn","doi":"10.1145/2593069.2602972","DOIUrl":"https://doi.org/10.1145/2593069.2602972","url":null,"abstract":"ISO 26262 is the new standard for automotive functional safety. This standard identifies major process steps across a large number of system stages as well as safety-related artifacts required as input and output of these steps. The VeriSpec project intends to identify the main challenges for the adoption of ISO 26262 by the heavy-vehicle industry and to provide useful and industrially relevant “components” (methods, tools etc.) required by the standard. The project work targets two main research goals: (i) requirement formalization support, including a usable front-end for specifying requirements by using patterns, and (ii) formal analysis of realizations in form of architectural models at various levels of abstraction, by model-checking the formal representations of the latter. In this paper, we present the current challenges facing industry and justifying VeriSpec, together with a preliminary roadmap for the research.","PeriodicalId":433816,"journal":{"name":"2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123240941","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
H. Bokhari, Haris Javaid, M. Shafique, J. Henkel, S. Parameswaran
In this paper, we propose a novel NoC architecture, called dark-NoC, where multiple layers of architecturally identical, but physically different routers are integrated, leveraging the extra transistors available due to dark silicon . Each layer is separately optimized for a particular voltage-frequency range by the adroit use of multi-Vt circuit optimization. At a given time, only one of the network layers is illuminated while all the other network layers are dark. We provide architectural support for seamless integration of multiple network layers, and a fast inter-layer switching mechanism without dropping in-network packets. Our experiments on a 4 × 4 mesh with multi-programmed real application workloads show that darkNoC improves energy-delay product by up to 56% compared to a traditional single layer NoC with state-of-the-art DVFS. This illustrates darkNoC can be used as an energy-efficient communication fabric in future dark silicon chips.
{"title":"darkNoC: Designing energy-efficient network-on-chip with multi-Vt cells for dark silicon","authors":"H. Bokhari, Haris Javaid, M. Shafique, J. Henkel, S. Parameswaran","doi":"10.1145/2593069.2593117","DOIUrl":"https://doi.org/10.1145/2593069.2593117","url":null,"abstract":"In this paper, we propose a novel NoC architecture, called dark-NoC, where multiple layers of architecturally identical, but physically different routers are integrated, leveraging the extra transistors available due to dark silicon . Each layer is separately optimized for a particular voltage-frequency range by the adroit use of multi-Vt circuit optimization. At a given time, only one of the network layers is illuminated while all the other network layers are dark. We provide architectural support for seamless integration of multiple network layers, and a fast inter-layer switching mechanism without dropping in-network packets. Our experiments on a 4 × 4 mesh with multi-programmed real application workloads show that darkNoC improves energy-delay product by up to 56% compared to a traditional single layer NoC with state-of-the-art DVFS. This illustrates darkNoC can be used as an energy-efficient communication fabric in future dark silicon chips.","PeriodicalId":433816,"journal":{"name":"2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131494959","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Formal methods such as reachability analysis often suffer from state space explosion in the verification of complex analog circuits. This paper proposes a parallel hierarchical SMT-based reachability analysis technique based on circuit decomposition. Circuits are systematically decomposed into subsystems with less complex transient behaviors which can be solved in parallel. Then a simulation-assisted SMT-based reachability analysis approach is adopted to conservatively approximate the reachable spaces in each subsystem with support function representations. We formally develop a general decomposition algorithm without overapproxmiation in system reconstruction. The efficiency of this general methodology is further optimized with an efficient parallel implementation strategy.
{"title":"Parallel hierarchical reachability analysis for analog verification","authors":"H. Lin, Peng Li","doi":"10.1145/2593069.2593178","DOIUrl":"https://doi.org/10.1145/2593069.2593178","url":null,"abstract":"Formal methods such as reachability analysis often suffer from state space explosion in the verification of complex analog circuits. This paper proposes a parallel hierarchical SMT-based reachability analysis technique based on circuit decomposition. Circuits are systematically decomposed into subsystems with less complex transient behaviors which can be solved in parallel. Then a simulation-assisted SMT-based reachability analysis approach is adopted to conservatively approximate the reachable spaces in each subsystem with support function representations. We formally develop a general decomposition algorithm without overapproxmiation in system reconstruction. The efficiency of this general methodology is further optimized with an efficient parallel implementation strategy.","PeriodicalId":433816,"journal":{"name":"2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131780072","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Many prior works have discussed the power grid design and optimization in the post-layout stage, when design change is inevitably expensive and difficult. In contrast, during the early stage of a development cycle, designers have more flexibility to improve the design quality. However, there are several fundamental challenges at early-stage when design database is NOT complete, including extraction, modeling and optimization. This paper tackles these fundamental issues of early-stage power grid design. The proposed methods have been silicon-validated on 32nm on-market chips and successfully applied to a 22nm design for its early stage power grid design. The findings from such practices reveal that, for sub-32nm chips, intrinsic on-die capacitance and power gate scheme may have more significant impact than expected on power integrity, and need to be well addressed at early stage.
{"title":"Early-stage power grid design: Extraction, modeling and optimization","authors":"Cheng Zhuo, H. Gan, W. Shih","doi":"10.1145/2593069.2593129","DOIUrl":"https://doi.org/10.1145/2593069.2593129","url":null,"abstract":"Many prior works have discussed the power grid design and optimization in the post-layout stage, when design change is inevitably expensive and difficult. In contrast, during the early stage of a development cycle, designers have more flexibility to improve the design quality. However, there are several fundamental challenges at early-stage when design database is NOT complete, including extraction, modeling and optimization. This paper tackles these fundamental issues of early-stage power grid design. The proposed methods have been silicon-validated on 32nm on-market chips and successfully applied to a 22nm design for its early stage power grid design. The findings from such practices reveal that, for sub-32nm chips, intrinsic on-die capacitance and power gate scheme may have more significant impact than expected on power integrity, and need to be well addressed at early stage.","PeriodicalId":433816,"journal":{"name":"2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116616972","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Anup Das, R. Shafik, G. Merrett, B. Al-Hashimi, Akash Kumar, B. Veeravalli
The thermal profile of multicore systems vary both within an application's execution (intra) and also when the system switches from one application to another (inter). In this paper, we propose an adaptive thermal management approach to improve the lifetime reliability of multicore systems by considering both inter- and intra-application thermal variations. Fundamental to this approach is a reinforcement learning algorithm, which learns the relationship between the mapping of threads to cores, the frequency of a core and its temperature (sampled from on-board thermal sensors). Action is provided by overriding the operating system's mapping decisions using affinity masks and dynamically changing CPU frequency using in-kernel governors. Lifetime improvement is achieved by controlling not only the peak and average temperatures but also thermal cycling, which is an emerging wear-out concern in modern systems. The proposed approach is validated experimentally using an Intel quad-core platform executing a diverse set of multimedia benchmarks. Results demonstrate that the proposed approach minimizes average temperature, peak temperature and thermal cycling, improving the mean-time-to-failure (MTTF) by an average of 2× for intra-application and 3× for inter-application scenarios when compared to existing thermal management techniques. Furthermore, the dynamic and static energy consumption are also reduced by an average 10% and 11% respectively.
{"title":"Reinforcement learning-based inter- and intra-application thermal optimization for lifetime improvement of multicore systems","authors":"Anup Das, R. Shafik, G. Merrett, B. Al-Hashimi, Akash Kumar, B. Veeravalli","doi":"10.1145/2593069.2593199","DOIUrl":"https://doi.org/10.1145/2593069.2593199","url":null,"abstract":"The thermal profile of multicore systems vary both within an application's execution (intra) and also when the system switches from one application to another (inter). In this paper, we propose an adaptive thermal management approach to improve the lifetime reliability of multicore systems by considering both inter- and intra-application thermal variations. Fundamental to this approach is a reinforcement learning algorithm, which learns the relationship between the mapping of threads to cores, the frequency of a core and its temperature (sampled from on-board thermal sensors). Action is provided by overriding the operating system's mapping decisions using affinity masks and dynamically changing CPU frequency using in-kernel governors. Lifetime improvement is achieved by controlling not only the peak and average temperatures but also thermal cycling, which is an emerging wear-out concern in modern systems. The proposed approach is validated experimentally using an Intel quad-core platform executing a diverse set of multimedia benchmarks. Results demonstrate that the proposed approach minimizes average temperature, peak temperature and thermal cycling, improving the mean-time-to-failure (MTTF) by an average of 2× for intra-application and 3× for inter-application scenarios when compared to existing thermal management techniques. Furthermore, the dynamic and static energy consumption are also reduced by an average 10% and 11% respectively.","PeriodicalId":433816,"journal":{"name":"2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122211162","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Philip Axer, Daniel Thiele, R. Ernst, Jonas Diemer
New hard real-time Advanced Driver Assistance Systems such as the Collision-Avoidance System push the bandwidth requirements of the communication infrastructure to a new level. Controller Area Network (CAN) and FlexRay are reaching their limits. Ethernet-based automotive networks such as Ethernet AVB are capable of addressing these requirements. However, designing predictable Ethernet networks is more complex than the design of a traditional CAN bus. Formal real-time performance characteristics are key to a successful Ethernet integration. In this paper we present an improved Ethernet AVB performance analysis which exploits traffic-stream correlations. The results are significantly tighter compared to related work.
{"title":"Exploiting shaper context to improve performance bounds of Ethernet AVB networks","authors":"Philip Axer, Daniel Thiele, R. Ernst, Jonas Diemer","doi":"10.1145/2593069.2593136","DOIUrl":"https://doi.org/10.1145/2593069.2593136","url":null,"abstract":"New hard real-time Advanced Driver Assistance Systems such as the Collision-Avoidance System push the bandwidth requirements of the communication infrastructure to a new level. Controller Area Network (CAN) and FlexRay are reaching their limits. Ethernet-based automotive networks such as Ethernet AVB are capable of addressing these requirements. However, designing predictable Ethernet networks is more complex than the design of a traditional CAN bus. Formal real-time performance characteristics are key to a successful Ethernet integration. In this paper we present an improved Ethernet AVB performance analysis which exploits traffic-stream correlations. The results are significantly tighter compared to related work.","PeriodicalId":433816,"journal":{"name":"2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134549052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Custom arithmetic circuits designed over Galois fields F2k are prevalent in cryptography, where the field size k is very large (e.g. k = 571-bits). Equivalence checking of such large custom arithmetic circuits against baseline golden models is beyond the capabilities of contemporary techniques. This paper addresses the problem by deriving word-level canonical polynomial representations from gate-level circuits as Z = F (A) over F2k, where Z and A represent the output and input bit-vectors of the circuit, respectively. Using algebraic geometry, we show that the canonical polynomial abstraction can be derived by computing a Gröbner basis of a set of polynomials extracted from the circuit, using a specific elimination (abstraction) term order. By efficiently applying these concepts, we can derive the canonical abstraction in hierarchically designed, custom arithmetic circuits with up to 571-bit datapath, whereas contemporary techniques can verify only up to 163-bit circuits.
在伽罗瓦字段F2k上设计的自定义算术电路在密码学中很普遍，其中字段大小k非常大(例如k = 571位)。这种大型自定义算术电路对基准黄金模型的等效性检查超出了当代技术的能力。本文通过从门级电路中推导出Z = F (A) / F2k的字级正则多项式表示来解决这个问题，其中Z和A分别表示电路的输出和输入位向量。使用代数几何，我们证明了规范多项式抽象可以通过计算从电路中提取的多项式集合的Gröbner基来推导，使用特定的消除(抽象)项顺序。通过有效地应用这些概念，我们可以在具有高达571位数据路径的分层设计的自定义算术电路中推导出规范抽象，而当代技术只能验证高达163位的电路。
{"title":"Equivalence verification of large Galois field arithmetic circuits using word-level abstraction via Gröbner bases","authors":"Tim Pruss, P. Kalla, Florian Enescu","doi":"10.1145/2593069.2593134","DOIUrl":"https://doi.org/10.1145/2593069.2593134","url":null,"abstract":"Custom arithmetic circuits designed over Galois fields F2k are prevalent in cryptography, where the field size k is very large (e.g. k = 571-bits). Equivalence checking of such large custom arithmetic circuits against baseline golden models is beyond the capabilities of contemporary techniques. This paper addresses the problem by deriving word-level canonical polynomial representations from gate-level circuits as Z = F (A) over F2k, where Z and A represent the output and input bit-vectors of the circuit, respectively. Using algebraic geometry, we show that the canonical polynomial abstraction can be derived by computing a Gröbner basis of a set of polynomials extracted from the circuit, using a specific elimination (abstraction) term order. By efficiently applying these concepts, we can derive the canonical abstraction in hierarchically designed, custom arithmetic circuits with up to 571-bit datapath, whereas contemporary techniques can verify only up to 163-bit circuits.","PeriodicalId":433816,"journal":{"name":"2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)","volume":"9 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132026375","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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