Pub Date : 2021-05-10DOI: 10.1109/SPI52361.2021.9505239
Surila Guglani, K. Dimple, B. Kaushik, Sourajeet Roy, Rohit Sharma
In this paper, a polynomial chaos (PC) approach based on the concept of multi-fidelity algorithms is presented for uncertainty quantification of multi-walled carbon nanotube (MWCNT) interconnect networks exhibiting imperfect contacts. The salient feature of the proposed approach is the development of a new low-fidelity model where each MWCNT conductor is represented as multiple parasitically coupled equivalent conductors depending on the nature of the contact resistance of each shell making up that conductor. This proposed low-fidelity model is provably more accurate than existing low-fidelity models, thereby leading to even faster construction of PC metamodels than previously possible.
{"title":"A Multi-Fidelity Polynomial Chaos Approach for Uncertainty Quantification of MWCNT Interconnect Networks in the Presence of Imperfect Contacts","authors":"Surila Guglani, K. Dimple, B. Kaushik, Sourajeet Roy, Rohit Sharma","doi":"10.1109/SPI52361.2021.9505239","DOIUrl":"https://doi.org/10.1109/SPI52361.2021.9505239","url":null,"abstract":"In this paper, a polynomial chaos (PC) approach based on the concept of multi-fidelity algorithms is presented for uncertainty quantification of multi-walled carbon nanotube (MWCNT) interconnect networks exhibiting imperfect contacts. The salient feature of the proposed approach is the development of a new low-fidelity model where each MWCNT conductor is represented as multiple parasitically coupled equivalent conductors depending on the nature of the contact resistance of each shell making up that conductor. This proposed low-fidelity model is provably more accurate than existing low-fidelity models, thereby leading to even faster construction of PC metamodels than previously possible.","PeriodicalId":440368,"journal":{"name":"2021 IEEE 25th Workshop on Signal and Power Integrity (SPI)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128442798","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-05-10DOI: 10.1109/SPI52361.2021.9505219
Daniel Uebach, Thomas Kühler, E. Griese
An integrated directional couplers manufactured in thin glass sheets by a field-assisted diffusion process is analyzed. The Coupler is designed for a simultaneous bidirectional chip-to-chip intercommunication in Electro-Optical Printed Circuit Boards (EOPCBs). A numerical investigation to optimize the designed coupler efficiency is presented using a geometrical optics algorithm. The results are verified by measurements to achieve an optimal coupler structure.
{"title":"Investigation of an Integrated Directional Coupler Manufactured by a Field-Assisted Diffusion Process","authors":"Daniel Uebach, Thomas Kühler, E. Griese","doi":"10.1109/SPI52361.2021.9505219","DOIUrl":"https://doi.org/10.1109/SPI52361.2021.9505219","url":null,"abstract":"An integrated directional couplers manufactured in thin glass sheets by a field-assisted diffusion process is analyzed. The Coupler is designed for a simultaneous bidirectional chip-to-chip intercommunication in Electro-Optical Printed Circuit Boards (EOPCBs). A numerical investigation to optimize the designed coupler efficiency is presented using a geometrical optics algorithm. The results are verified by measurements to achieve an optimal coupler structure.","PeriodicalId":440368,"journal":{"name":"2021 IEEE 25th Workshop on Signal and Power Integrity (SPI)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125908146","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-05-10DOI: 10.1109/SPI52361.2021.9505195
F. Treviso, R. Trinchero, F. Canavero
This paper presents an automatic procedure for the optimization of the hyperparameters of a delay rational model approximating the frequency-domain behavior of high-speed interconnects. The proposed model is built via a kernel-based regression, such as the Least-Square Support Vector Machine (LS-SVM), by considering an ad-hoc kernel with two hyperparameters related to the propagation delays introduced by the system. Such hyperparameters, along with the Tikhonov regularizer used by the LS-SVM regression, are carefully tuned via an automatic approach based on a k-fold cross-validation and Bayesian optimization. The feasibility of the effectiveness of the proposed modeling approach are investigated on a high-speed link.
{"title":"Bayesian Optimization of Hyperparameters in Kernel-Based Delay Rational Models","authors":"F. Treviso, R. Trinchero, F. Canavero","doi":"10.1109/SPI52361.2021.9505195","DOIUrl":"https://doi.org/10.1109/SPI52361.2021.9505195","url":null,"abstract":"This paper presents an automatic procedure for the optimization of the hyperparameters of a delay rational model approximating the frequency-domain behavior of high-speed interconnects. The proposed model is built via a kernel-based regression, such as the Least-Square Support Vector Machine (LS-SVM), by considering an ad-hoc kernel with two hyperparameters related to the propagation delays introduced by the system. Such hyperparameters, along with the Tikhonov regularizer used by the LS-SVM regression, are carefully tuned via an automatic approach based on a k-fold cross-validation and Bayesian optimization. The feasibility of the effectiveness of the proposed modeling approach are investigated on a high-speed link.","PeriodicalId":440368,"journal":{"name":"2021 IEEE 25th Workshop on Signal and Power Integrity (SPI)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124656058","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-05-10DOI: 10.1109/SPI52361.2021.9505189
Longfei Bai
Channel Operating Margin (COM) is an efficient method to evaluate high speed interconnects. Two 100GBASE-KP4 backplanes are simulated and compared to give a brief introduction of COM. The pulse responses of COM are validated by comparing to the transient circuit simulation. A generic model for error propagation is proposed based on the COM results and Markov Chain. It shows that backplane designs with large Decision Feedback Equalizer (DFE) taps can have significant error propagation effect, which degrades the system performance further.
{"title":"Error Propagation in Channel Operating Margin","authors":"Longfei Bai","doi":"10.1109/SPI52361.2021.9505189","DOIUrl":"https://doi.org/10.1109/SPI52361.2021.9505189","url":null,"abstract":"Channel Operating Margin (COM) is an efficient method to evaluate high speed interconnects. Two 100GBASE-KP4 backplanes are simulated and compared to give a brief introduction of COM. The pulse responses of COM are validated by comparing to the transient circuit simulation. A generic model for error propagation is proposed based on the COM results and Markov Chain. It shows that backplane designs with large Decision Feedback Equalizer (DFE) taps can have significant error propagation effect, which degrades the system performance further.","PeriodicalId":440368,"journal":{"name":"2021 IEEE 25th Workshop on Signal and Power Integrity (SPI)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128823804","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-05-10DOI: 10.1109/SPI52361.2021.9505184
Michael Chang, Simon M. Kao, Stephen Chu, Bryant Hsu, Mark Ciou, Kevin Chung, Robby Ho
The paper introduces a Verilog-A model with the skill of vector fitting and neural network for the efficient methodology to analyze the power distribution network of on-chip linear dropout regulator (LDO). A practical methodology demonstrates the effectiveness and the efficiency of the Verilog-A model in the time domain and is derived that takes into account LDO-PDN system impedance response. The goal is to provide adequate performance for cost-effective and system solution and achieving on system-level success.
{"title":"Machine Learning-Based Verilog-A Modeling for Power Distribution Network of On-Die Regulator","authors":"Michael Chang, Simon M. Kao, Stephen Chu, Bryant Hsu, Mark Ciou, Kevin Chung, Robby Ho","doi":"10.1109/SPI52361.2021.9505184","DOIUrl":"https://doi.org/10.1109/SPI52361.2021.9505184","url":null,"abstract":"The paper introduces a Verilog-A model with the skill of vector fitting and neural network for the efficient methodology to analyze the power distribution network of on-chip linear dropout regulator (LDO). A practical methodology demonstrates the effectiveness and the efficiency of the Verilog-A model in the time domain and is derived that takes into account LDO-PDN system impedance response. The goal is to provide adequate performance for cost-effective and system solution and achieving on system-level success.","PeriodicalId":440368,"journal":{"name":"2021 IEEE 25th Workshop on Signal and Power Integrity (SPI)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129037610","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-05-10DOI: 10.1109/SPI52361.2021.9505171
H. Dsilva, S. McMorrow, A. Gregory, S. Krooswyk, R. Mellitz, Beomtaek Lee
At higher data rate (50 Gbps+), there is a need to understand the different interconnect impairments that lead to margin degradation. This paper presents the impact of intra-pair skew from a magnitude and polarity perspective on the interconnect electrical characteristics. Presented is the results of differential insertion loss, mode conversion and differential far-end crosstalk along with margin degradation through channel operating margin in operating at 106.25 Gbps PAM4 signaling. Simulated is a differential microstrip structure using a full-wave electromagnetic wave simulator. Results show that magnitude of intra-pair skew leads to degradation in differential insertion loss due to energy getting converted to common-mode. Insertion loss and intra-pair skew share a cosine relation and hence the impact of intra-pair skew on differential insertion loss is dependent on the magnitude of skew alone. In the case of differential far-end crosstalk, the impact of intra-pair skew may be constructive or destructive depending on the magnitude and polarity of intra-pair skew. Intra-pair skew leads to propagation time difference which in turn impacts the crosstalk and thus impact of intra-pair skew on crosstalk is dependent on the magnitude along with the polarity of skew. Presented is a overview on the importance of capturing the impact of common-mode to differential-mode conversion on margin degradation, which is not captured by many channel simulation tools. This work is an attempt at presenting the importance of limiting the intra-pair skew in the interconnect when targeting higher data rates (50 Gbps+).
{"title":"De-mystifying the impact of Intra-pair Skew on high-speed SerDes Interconnect","authors":"H. Dsilva, S. McMorrow, A. Gregory, S. Krooswyk, R. Mellitz, Beomtaek Lee","doi":"10.1109/SPI52361.2021.9505171","DOIUrl":"https://doi.org/10.1109/SPI52361.2021.9505171","url":null,"abstract":"At higher data rate (50 Gbps+), there is a need to understand the different interconnect impairments that lead to margin degradation. This paper presents the impact of intra-pair skew from a magnitude and polarity perspective on the interconnect electrical characteristics. Presented is the results of differential insertion loss, mode conversion and differential far-end crosstalk along with margin degradation through channel operating margin in operating at 106.25 Gbps PAM4 signaling. Simulated is a differential microstrip structure using a full-wave electromagnetic wave simulator. Results show that magnitude of intra-pair skew leads to degradation in differential insertion loss due to energy getting converted to common-mode. Insertion loss and intra-pair skew share a cosine relation and hence the impact of intra-pair skew on differential insertion loss is dependent on the magnitude of skew alone. In the case of differential far-end crosstalk, the impact of intra-pair skew may be constructive or destructive depending on the magnitude and polarity of intra-pair skew. Intra-pair skew leads to propagation time difference which in turn impacts the crosstalk and thus impact of intra-pair skew on crosstalk is dependent on the magnitude along with the polarity of skew. Presented is a overview on the importance of capturing the impact of common-mode to differential-mode conversion on margin degradation, which is not captured by many channel simulation tools. This work is an attempt at presenting the importance of limiting the intra-pair skew in the interconnect when targeting higher data rates (50 Gbps+).","PeriodicalId":440368,"journal":{"name":"2021 IEEE 25th Workshop on Signal and Power Integrity (SPI)","volume":"316 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122782670","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-05-10DOI: 10.1109/SPI52361.2021.9505174
S. R. Mahendra, A. Weisshaar
This paper presents a design approach for on-chip realization of compact and broadband delay units based on the bridged T-coil. Closed-form design equations for the bridged T-coil circuit elements are derived from the 2nd order Padé approximation. Standardized delay units are designed having high isolation from adjacent circuitry by use of a guard ring. The main layout parasitics are incorporated into the design and a detailed design procedure together with a parasitic circuit model is presented. Two delay units for 20-ps and 30-ps delay are designed in a TowerSemi 0.18μm SiGe BiCMOS process to demonstrate the design approach. Full-wave electromagnetic simulations demonstrate the flatness of the group delay responses up to 13 GHz for the 20-ps delay and up to 8 GHz for the 30-ps delay, exceeding the bandwidths obtained with the Padé approximation design with negligible increase in insertion loss and negligible ripple in the flat group delay region. The maximum insertion loss in the region with flat group delay is less than 1dB.
{"title":"A Compact and Broadband On-Chip Delay Line Design Based on the Bridged T-Coil","authors":"S. R. Mahendra, A. Weisshaar","doi":"10.1109/SPI52361.2021.9505174","DOIUrl":"https://doi.org/10.1109/SPI52361.2021.9505174","url":null,"abstract":"This paper presents a design approach for on-chip realization of compact and broadband delay units based on the bridged T-coil. Closed-form design equations for the bridged T-coil circuit elements are derived from the 2nd order Padé approximation. Standardized delay units are designed having high isolation from adjacent circuitry by use of a guard ring. The main layout parasitics are incorporated into the design and a detailed design procedure together with a parasitic circuit model is presented. Two delay units for 20-ps and 30-ps delay are designed in a TowerSemi 0.18μm SiGe BiCMOS process to demonstrate the design approach. Full-wave electromagnetic simulations demonstrate the flatness of the group delay responses up to 13 GHz for the 20-ps delay and up to 8 GHz for the 30-ps delay, exceeding the bandwidths obtained with the Padé approximation design with negligible increase in insertion loss and negligible ripple in the flat group delay region. The maximum insertion loss in the region with flat group delay is less than 1dB.","PeriodicalId":440368,"journal":{"name":"2021 IEEE 25th Workshop on Signal and Power Integrity (SPI)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121805568","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In the high-speed differential (HSD) interface design, the intra-pair skew becomes more critical as the link speed is ever increasing beyond 56Gbps+ signaling. The skew within a differential pair (intra-pair skew) deteriorates eye opening at the receiver and degrades the channel performance significantly in HSD signaling. However, industry lacks in an accurate and stable intra-pair skew measurement methodology, which created a significant gap in interconnect testing and qualification. In this paper, the effective intra-pair skew (EIPS) is introduced, which is directly calculated from S-parameter data as a single value without time-domain conversion. The EIPS is verified by correlating to the eye opening and the common-mode noise (CMN) in the HSD link of PCIe Gen5 32Gbps NRZ signaling. The MATLAB script for the EIPS calculation is included in the appendix.
{"title":"Intra-Pair Skew Metric, EIPS (Effective Intra-Pair Skew)","authors":"Se-jung Moon, Jianting Li, Xinjun Zhang, Chien-Ping Kao, Beomtaek Lee, H. Dsilva, Jong-Ru Guo","doi":"10.1109/SPI52361.2021.9505188","DOIUrl":"https://doi.org/10.1109/SPI52361.2021.9505188","url":null,"abstract":"In the high-speed differential (HSD) interface design, the intra-pair skew becomes more critical as the link speed is ever increasing beyond 56Gbps+ signaling. The skew within a differential pair (intra-pair skew) deteriorates eye opening at the receiver and degrades the channel performance significantly in HSD signaling. However, industry lacks in an accurate and stable intra-pair skew measurement methodology, which created a significant gap in interconnect testing and qualification. In this paper, the effective intra-pair skew (EIPS) is introduced, which is directly calculated from S-parameter data as a single value without time-domain conversion. The EIPS is verified by correlating to the eye opening and the common-mode noise (CMN) in the HSD link of PCIe Gen5 32Gbps NRZ signaling. The MATLAB script for the EIPS calculation is included in the appendix.","PeriodicalId":440368,"journal":{"name":"2021 IEEE 25th Workshop on Signal and Power Integrity (SPI)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128161065","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-05-10DOI: 10.1109/SPI52361.2021.9505214
Ö. Yildiz, N. Pathé, Marc Bochard, Cheng Yang, C. Schuster
Given the ubiquitous use of via arrays in multilayer substrates based on organic materials, this work explores ceramic-based solutions instead. Assuming typical design and technology constraints, the performance of via arrays on low temperature cofired ceramics is studied in terms of crosstalk as well as transmission. Both single-ended and differential signaling are considered, thus covering a broad range of use cases for microwave applications and high-speed digital links. By employing single vias optimized with respect to 50Ω systems as fundamental building blocks for larger via arrays, different array configurations are proposed and analyzed. The question as to what moving from organic to ceramic materials and vice versa implies in terms of electrical performance is investigated. The majority of the work is based on the computationally efficient physics-based via modeling technique due to the size and complexity of the via array models, but comparisons to conventional full-wave solvers show strong agreement between the two methods up to 50GHz.
{"title":"Analysis of Differential Crosstalk and Transmission for Via Arrays in Low Temperature Cofired Ceramics","authors":"Ö. Yildiz, N. Pathé, Marc Bochard, Cheng Yang, C. Schuster","doi":"10.1109/SPI52361.2021.9505214","DOIUrl":"https://doi.org/10.1109/SPI52361.2021.9505214","url":null,"abstract":"Given the ubiquitous use of via arrays in multilayer substrates based on organic materials, this work explores ceramic-based solutions instead. Assuming typical design and technology constraints, the performance of via arrays on low temperature cofired ceramics is studied in terms of crosstalk as well as transmission. Both single-ended and differential signaling are considered, thus covering a broad range of use cases for microwave applications and high-speed digital links. By employing single vias optimized with respect to 50Ω systems as fundamental building blocks for larger via arrays, different array configurations are proposed and analyzed. The question as to what moving from organic to ceramic materials and vice versa implies in terms of electrical performance is investigated. The majority of the work is based on the computationally efficient physics-based via modeling technique due to the size and complexity of the via array models, but comparisons to conventional full-wave solvers show strong agreement between the two methods up to 50GHz.","PeriodicalId":440368,"journal":{"name":"2021 IEEE 25th Workshop on Signal and Power Integrity (SPI)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130158799","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-05-10DOI: 10.1109/SPI52361.2021.9505182
R. Franchino, R. Mitova
A method and a modeling procedure to simulate and optimize a half bridge power inverter with GaN (gallium nitride) transistors in parallel is proposed. The method is based on S-parameters calculation of the PCB (Printed Circuit Board) and the definition of relevant frequency simulation allowing to characterize harmful couplings effects of the PCB on transistors. The definition of the frequency analysis is explained on the criterion of the current sharing between transistors in parallel, considering the functional switching sequence of the inverter. The frequency analysis is carried out on a four-port Y matrix of the switching loop including PCB couplings and relevant components. The efficiency of the method is demonstrated by the successful modification of the PCB.
{"title":"PCB analysis method by S-parameters for power inverters with GaN devices in parallel","authors":"R. Franchino, R. Mitova","doi":"10.1109/SPI52361.2021.9505182","DOIUrl":"https://doi.org/10.1109/SPI52361.2021.9505182","url":null,"abstract":"A method and a modeling procedure to simulate and optimize a half bridge power inverter with GaN (gallium nitride) transistors in parallel is proposed. The method is based on S-parameters calculation of the PCB (Printed Circuit Board) and the definition of relevant frequency simulation allowing to characterize harmful couplings effects of the PCB on transistors. The definition of the frequency analysis is explained on the criterion of the current sharing between transistors in parallel, considering the functional switching sequence of the inverter. The frequency analysis is carried out on a four-port Y matrix of the switching loop including PCB couplings and relevant components. The efficiency of the method is demonstrated by the successful modification of the PCB.","PeriodicalId":440368,"journal":{"name":"2021 IEEE 25th Workshop on Signal and Power Integrity (SPI)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129984246","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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