This paper presents a new configuration for balanced Operational Transconductance amplifies where digitally controlled current switch is designed to generate the different bias currents. To achieve better linearity, the source degeneration circuit for differential pair is used in the Balanced OTA [1]. The digitally controlled switch is nothing but MOSFETs with different width and lengths. This helps to have different bias currents just by turning on particular MOSFET in the switch module. Using the designed structure a variable resistor is designed [2]. Also as an application example, an electronically tunable phase shifter is implemented [3]. In this phase shifter using the designed OTA, by applying different bias currents generated through the digital switch we can obtain different phase shifts. The circuit performance of linear transconductance amplifier is measured in terms of the linearity, slew rate, CMRR, settling time, over shoot and undershoot. Here all the circuits are implemented Tanner EDA and simulated in 130nm using TSMC MOSIS Level-49 model in TSPICE simulator.
{"title":"Design and Implementation of a Linear Transconductance Amplifier with a Digitally Controlled Current Source","authors":"R. L. Nagaraj, D. Yagain","doi":"10.1109/ICETET.2011.24","DOIUrl":"https://doi.org/10.1109/ICETET.2011.24","url":null,"abstract":"This paper presents a new configuration for balanced Operational Transconductance amplifies where digitally controlled current switch is designed to generate the different bias currents. To achieve better linearity, the source degeneration circuit for differential pair is used in the Balanced OTA [1]. The digitally controlled switch is nothing but MOSFETs with different width and lengths. This helps to have different bias currents just by turning on particular MOSFET in the switch module. Using the designed structure a variable resistor is designed [2]. Also as an application example, an electronically tunable phase shifter is implemented [3]. In this phase shifter using the designed OTA, by applying different bias currents generated through the digital switch we can obtain different phase shifts. The circuit performance of linear transconductance amplifier is measured in terms of the linearity, slew rate, CMRR, settling time, over shoot and undershoot. Here all the circuits are implemented Tanner EDA and simulated in 130nm using TSMC MOSIS Level-49 model in TSPICE simulator.","PeriodicalId":443239,"journal":{"name":"2011 Fourth International Conference on Emerging Trends in Engineering & Technology","volume":"149 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133752840","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The paper is in two parts and in Part (1) attempts to formalise the loose concept of "System of Systems" (SoS) within the context of Systems Theory whilst in Part (2) explores and develops a conceptual framework for emergence that is suitable for further development. We view the notion of SoS as an evolution of the standard notion of systems and provide an abstract and generic definition that is detached from the particular domain. To achieve this we deal first with the abstraction of the fundamental components of the system, describe the different aspects of the structure of a composite system and then embark on the task to explain the difference of the new notion, to the standard notion of Composite Systems. We present a new abstract definition of the notion of System of Systems as an evolution of the notion of Composite Systems, empowered by the concept of autonomy and participation in tasks referred to as plays which are usually linked to games. The notion of the play is introduced as an extension of the notion of the system and involves the notion of autonomous agents in place of objects and the notion of scenario in place of interconnection topology. This new definition characterises SoS as a development of the Composite System notion where now the subsystems act as autonomous intelligent agents in a multi-agent system play based on a scenario that possibly involves a game. The notion of emergence is considered within both the framework of Composite and SoS and it is linked to the problem of defining functions on a given system and evaluating their values. The emergence is thus presented as the defining signature of a system including System of Systems.
{"title":"System of Systems and Emergence Part 1: Principles and Framework","authors":"N. Karcanias, A. Hessami","doi":"10.1109/ICETET.2011.51","DOIUrl":"https://doi.org/10.1109/ICETET.2011.51","url":null,"abstract":"The paper is in two parts and in Part (1) attempts to formalise the loose concept of \"System of Systems\" (SoS) within the context of Systems Theory whilst in Part (2) explores and develops a conceptual framework for emergence that is suitable for further development. We view the notion of SoS as an evolution of the standard notion of systems and provide an abstract and generic definition that is detached from the particular domain. To achieve this we deal first with the abstraction of the fundamental components of the system, describe the different aspects of the structure of a composite system and then embark on the task to explain the difference of the new notion, to the standard notion of Composite Systems. We present a new abstract definition of the notion of System of Systems as an evolution of the notion of Composite Systems, empowered by the concept of autonomy and participation in tasks referred to as plays which are usually linked to games. The notion of the play is introduced as an extension of the notion of the system and involves the notion of autonomous agents in place of objects and the notion of scenario in place of interconnection topology. This new definition characterises SoS as a development of the Composite System notion where now the subsystems act as autonomous intelligent agents in a multi-agent system play based on a scenario that possibly involves a game. The notion of emergence is considered within both the framework of Composite and SoS and it is linked to the problem of defining functions on a given system and evaluating their values. The emergence is thus presented as the defining signature of a system including System of Systems.","PeriodicalId":443239,"journal":{"name":"2011 Fourth International Conference on Emerging Trends in Engineering & Technology","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116254906","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Tomoya Tanaka, K. Sonoda, S. Okochi, A. Chan, M. Nii, K. Kanda, T. Fujita, K. Higuchi, K. Maenaka
A wearable health monitoring system and its applications for long term monitoring are presented in this paper. The system, called a gbutton system, h is attached over the chest for monitoring electrocardiogram (ECG), heart rate (HR), 3 axis acceleration, and temperature, as well as system battery voltage. The data is then sent to the host computer via a wireless transmitter. The button system is composed of three round substrates connected together. The substrate is 24 mm in diameter and 5-10 mm thick, making the system applicable for use in daily life. The several various types of sensors, micro controller, programmable gain amplifier (PGA) and Bluetooth wireless transmitter are embedded in system. The Micro Processing Unit (MPU) samples ECG and acceleration at 125 Hz to calculate HR for transmission. The battery voltage and temperature are sampled at 0.2 Hz due to the slow variability. The current consumption during wireless telecommunications is about 40 mA, so it is possible to use it continuously for about two hours with Li-ion button battery (75 mAh). In this study, we measured data while sleeping (for about 6 hours) with a large capacity battery (2000 mAh) instead of Li-ion battery. Heart rate variability (HRV) was then used as a quantitative marker of automatic nervous system activity, and the temporal variation of HRV was estimated.
{"title":"Wearable Health Monitoring System and Its Applications","authors":"Tomoya Tanaka, K. Sonoda, S. Okochi, A. Chan, M. Nii, K. Kanda, T. Fujita, K. Higuchi, K. Maenaka","doi":"10.1109/ICETET.2011.34","DOIUrl":"https://doi.org/10.1109/ICETET.2011.34","url":null,"abstract":"A wearable health monitoring system and its applications for long term monitoring are presented in this paper. The system, called a gbutton system, h is attached over the chest for monitoring electrocardiogram (ECG), heart rate (HR), 3 axis acceleration, and temperature, as well as system battery voltage. The data is then sent to the host computer via a wireless transmitter. The button system is composed of three round substrates connected together. The substrate is 24 mm in diameter and 5-10 mm thick, making the system applicable for use in daily life. The several various types of sensors, micro controller, programmable gain amplifier (PGA) and Bluetooth wireless transmitter are embedded in system. The Micro Processing Unit (MPU) samples ECG and acceleration at 125 Hz to calculate HR for transmission. The battery voltage and temperature are sampled at 0.2 Hz due to the slow variability. The current consumption during wireless telecommunications is about 40 mA, so it is possible to use it continuously for about two hours with Li-ion button battery (75 mAh). In this study, we measured data while sleeping (for about 6 hours) with a large capacity battery (2000 mAh) instead of Li-ion battery. Heart rate variability (HRV) was then used as a quantitative marker of automatic nervous system activity, and the temporal variation of HRV was estimated.","PeriodicalId":443239,"journal":{"name":"2011 Fourth International Conference on Emerging Trends in Engineering & Technology","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122416516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Globally asynchronous, locally synchronous (GALS) systems-on-chip (SoCs) may be prone to synchronization failure. This paper presents an in-depth analysis of the problem and proposes a novel solution. The problem is analyzed considering the cycle times of the GALS module, and the complexity of the asynchronous interface controllers using Petri Net graph (PN) approach. When high data bandwidth is not required, matched-delay asynchronous ports may be employed. A novel architecture for synchronizing inter-modular communications in GALS, based on delayed latching (DL), is described. DL synchronization does not require pausable clocking, is insensitive to clock tree delays, and supports high data rates. It replaces complex global timing constraints with simpler localized ones. Decoupled input port and Decoupled output port for Delayed Latching are presented. The risk of metastability in the synchronizer is analyzed in a technology-independent manner. Here we present the Petri net models of the Globally Asynchronous and Locally Synchronous (GALS) architectures for speed independent (SI). The models are feed into Petrify to produce logic equations for gate level implementation of asynchronous circuit. The circuit is simulated on VCS and synthesized on Design compiler of Synopsys EDA tool.
{"title":"Notice of Violation of IEEE Publication PrinciplesDelayed Latching for Data Synchronization in GALS SOC","authors":"V. Khetade, S.S. Limaye","doi":"10.1109/ICETET.2011.13","DOIUrl":"https://doi.org/10.1109/ICETET.2011.13","url":null,"abstract":"Globally asynchronous, locally synchronous (GALS) systems-on-chip (SoCs) may be prone to synchronization failure. This paper presents an in-depth analysis of the problem and proposes a novel solution. The problem is analyzed considering the cycle times of the GALS module, and the complexity of the asynchronous interface controllers using Petri Net graph (PN) approach. When high data bandwidth is not required, matched-delay asynchronous ports may be employed. A novel architecture for synchronizing inter-modular communications in GALS, based on delayed latching (DL), is described. DL synchronization does not require pausable clocking, is insensitive to clock tree delays, and supports high data rates. It replaces complex global timing constraints with simpler localized ones. Decoupled input port and Decoupled output port for Delayed Latching are presented. The risk of metastability in the synchronizer is analyzed in a technology-independent manner. Here we present the Petri net models of the Globally Asynchronous and Locally Synchronous (GALS) architectures for speed independent (SI). The models are feed into Petrify to produce logic equations for gate level implementation of asynchronous circuit. The circuit is simulated on VCS and synthesized on Design compiler of Synopsys EDA tool.","PeriodicalId":443239,"journal":{"name":"2011 Fourth International Conference on Emerging Trends in Engineering & Technology","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127919740","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Geerish Suddul, Avinash Soobul, Umar Bahadoor, A. Ramdoyal, Naveesh Doolhur, Morgan Richomme
This paper deals with the study of the role of Unstructured Supplementary Service Data (USSD) as a means to create low cost value added services for emerging countries. Most mobile telecommunication providers worldwide are tied up to third party USSD solution providers. The latter keep their infrastructure closed, which means that the development of services to be offered over USSD comes at a cost. We target this close infrastructure solution, and provide an open source web enabler in the form of an Application Programming interface (API), that can be used to deliver low cost services to mobile end users in emerging countries. The implementation of our solution, in the form of a prototype, has been successfully tested on the Orange (France Telecom) network.
{"title":"An Open USSD Enabler to Simplify Access to Mobile Services in Emerging Countries","authors":"Geerish Suddul, Avinash Soobul, Umar Bahadoor, A. Ramdoyal, Naveesh Doolhur, Morgan Richomme","doi":"10.1109/ICETET.2011.53","DOIUrl":"https://doi.org/10.1109/ICETET.2011.53","url":null,"abstract":"This paper deals with the study of the role of Unstructured Supplementary Service Data (USSD) as a means to create low cost value added services for emerging countries. Most mobile telecommunication providers worldwide are tied up to third party USSD solution providers. The latter keep their infrastructure closed, which means that the development of services to be offered over USSD comes at a cost. We target this close infrastructure solution, and provide an open source web enabler in the form of an Application Programming interface (API), that can be used to deliver low cost services to mobile end users in emerging countries. The implementation of our solution, in the form of a prototype, has been successfully tested on the Orange (France Telecom) network.","PeriodicalId":443239,"journal":{"name":"2011 Fourth International Conference on Emerging Trends in Engineering & Technology","volume":"2012 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132045284","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Digital circuits made up of classical gates dissipate significant amount of energy as bits are erased during logic operations. Use of reversible logic gates to implement such circuits can significantly reduce the power consumed. This paper covers various aspects about reversible computing and reversible logic gates. Furthermore in this paper we have tried to design a reversible implementation of eight bit arithmetic and logic unit, optimal in terms of number of gates used and number of garbage outputs produced.
{"title":"Design of Eight Bit Novel Reversible Arithmetic and Logic Unit","authors":"A. Keskar, V. Satpute","doi":"10.1109/ICETET.2011.17","DOIUrl":"https://doi.org/10.1109/ICETET.2011.17","url":null,"abstract":"Digital circuits made up of classical gates dissipate significant amount of energy as bits are erased during logic operations. Use of reversible logic gates to implement such circuits can significantly reduce the power consumed. This paper covers various aspects about reversible computing and reversible logic gates. Furthermore in this paper we have tried to design a reversible implementation of eight bit arithmetic and logic unit, optimal in terms of number of gates used and number of garbage outputs produced.","PeriodicalId":443239,"journal":{"name":"2011 Fourth International Conference on Emerging Trends in Engineering & Technology","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125578582","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In the present work an expert system has been developed for designing of dampers. This expert system takes inputs from user and it will calculate all dimensions, area of free mass, maximum heat dissipation, and the ratio of maximum heat dissipation to area of free mass. Then expert system will select most suitable damper and generates a script file and an Auto LISP file. By running the script file a 2D drawing and sectional view of the damper can be generated. The Auto LISP file can be run using AutoCAD to generate a 3D model for the damper. These drawings and the model can be used directly on the shop floor for manufacture of the dampers. This expert system reduces the design time of engineer and works as an assistant in designing of dampers. By saving time for initial designing of damper, the productivity of engineers can be increased. The present expert system can be used online for interaction between the customers and designers.
{"title":"Development of an Expert System for Designing of Automobile Dampers","authors":"G. Samuel, A. Bhagat","doi":"10.1109/ICETET.2011.20","DOIUrl":"https://doi.org/10.1109/ICETET.2011.20","url":null,"abstract":"In the present work an expert system has been developed for designing of dampers. This expert system takes inputs from user and it will calculate all dimensions, area of free mass, maximum heat dissipation, and the ratio of maximum heat dissipation to area of free mass. Then expert system will select most suitable damper and generates a script file and an Auto LISP file. By running the script file a 2D drawing and sectional view of the damper can be generated. The Auto LISP file can be run using AutoCAD to generate a 3D model for the damper. These drawings and the model can be used directly on the shop floor for manufacture of the dampers. This expert system reduces the design time of engineer and works as an assistant in designing of dampers. By saving time for initial designing of damper, the productivity of engineers can be increased. The present expert system can be used online for interaction between the customers and designers.","PeriodicalId":443239,"journal":{"name":"2011 Fourth International Conference on Emerging Trends in Engineering & Technology","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123352429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
DSP Application needs to speed-up in computation time can be achieved by assigning complex computation intensive tasks to hardware and by exploiting the parallelism in algorithms.These applications need high performance as well as cost efficient design. Reconfigurable systems offer us a potential for computation acceleration due to its software-like programmable nature of the parallel processing units. Run-time configuration explores a novel research area for reconfigurable hardware to further speedup the processing speed by eliminating the configuration overhead with the overlapping of execution time. Dynamic partial reconfigurable FPGAs offer new design space with a variety of benefits: reduce the configuration time and save memory as the partial reconfiguration files (bitstreams) are smaller than full ones. This paper introduces a simple reconfigurable system and focuses on the newest dynamic partial reconfiguration design flow.
{"title":"Dynamic Partial Reconfiguration in FPGAs for DSP Applications","authors":"C. V. Borkute, A. Deshmukh, Chetna N. Kharkar","doi":"10.1109/ICETET.2011.70","DOIUrl":"https://doi.org/10.1109/ICETET.2011.70","url":null,"abstract":"DSP Application needs to speed-up in computation time can be achieved by assigning complex computation intensive tasks to hardware and by exploiting the parallelism in algorithms.These applications need high performance as well as cost efficient design. Reconfigurable systems offer us a potential for computation acceleration due to its software-like programmable nature of the parallel processing units. Run-time configuration explores a novel research area for reconfigurable hardware to further speedup the processing speed by eliminating the configuration overhead with the overlapping of execution time. Dynamic partial reconfigurable FPGAs offer new design space with a variety of benefits: reduce the configuration time and save memory as the partial reconfiguration files (bitstreams) are smaller than full ones. This paper introduces a simple reconfigurable system and focuses on the newest dynamic partial reconfiguration design flow.","PeriodicalId":443239,"journal":{"name":"2011 Fourth International Conference on Emerging Trends in Engineering & Technology","volume":"23 9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116860315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, Fuzzy logic based supplementary controller is installed with Interline Power Flow Controller [IPFC] to damp low frequency oscillations. IPFC is a new concept of the Flexible AC Transmission system controller for series compensation with the unique capability of power flow of multiple transmission lines. For the analysis Modified linearized Philips -- Heffron model of Single Machine Infinite Bus system is established with a IPFC. The simulation results are presented to show the effectiveness and robustness of the proposed control schemes like Power Oscillation Damping [POD] controller, Power System Stabilizer [PSS] controller and Fuzzy logic controller by selecting effective control signals. Investigations reveal that coordinated tuning of IPFC with Fuzzy logic controller provide the robust dynamic performance. Eigen value analysis validates the performance of various controllers.
{"title":"Performance Evaluation of IPFC by Using Fuzzy Logic Based Controller for Damping of Power System Oscilllations","authors":"Supriya M. Belwanshi, V. Chandrakar, S. Dhurvey","doi":"10.1109/ICETET.2011.43","DOIUrl":"https://doi.org/10.1109/ICETET.2011.43","url":null,"abstract":"In this paper, Fuzzy logic based supplementary controller is installed with Interline Power Flow Controller [IPFC] to damp low frequency oscillations. IPFC is a new concept of the Flexible AC Transmission system controller for series compensation with the unique capability of power flow of multiple transmission lines. For the analysis Modified linearized Philips -- Heffron model of Single Machine Infinite Bus system is established with a IPFC. The simulation results are presented to show the effectiveness and robustness of the proposed control schemes like Power Oscillation Damping [POD] controller, Power System Stabilizer [PSS] controller and Fuzzy logic controller by selecting effective control signals. Investigations reveal that coordinated tuning of IPFC with Fuzzy logic controller provide the robust dynamic performance. Eigen value analysis validates the performance of various controllers.","PeriodicalId":443239,"journal":{"name":"2011 Fourth International Conference on Emerging Trends in Engineering & Technology","volume":"191 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115183564","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Dr Mangesh Bedekar, B. A. Rao, P. Gupta, Suvrajyoti Chatterjee
Collaborative caching and browsing allow a group of users to utilize internet bandwidth in an optimal manner by minimizing outgoing requests and allowing cooperation during web research activities. Let Surf allows a group of clients to retrieve cached materials from within the group while collaborating through a user interface to access items indicative of group behavior, such as the most recent links visited by peer users and the most popular links visited. An implementation of the system is presented and evaluated in terms of latency in loading a sample set of web elements.
{"title":"LetSurf -- Implementing Collaborative Surfing","authors":"Dr Mangesh Bedekar, B. A. Rao, P. Gupta, Suvrajyoti Chatterjee","doi":"10.1109/ICETET.2011.27","DOIUrl":"https://doi.org/10.1109/ICETET.2011.27","url":null,"abstract":"Collaborative caching and browsing allow a group of users to utilize internet bandwidth in an optimal manner by minimizing outgoing requests and allowing cooperation during web research activities. Let Surf allows a group of clients to retrieve cached materials from within the group while collaborating through a user interface to access items indicative of group behavior, such as the most recent links visited by peer users and the most popular links visited. An implementation of the system is presented and evaluated in terms of latency in loading a sample set of web elements.","PeriodicalId":443239,"journal":{"name":"2011 Fourth International Conference on Emerging Trends in Engineering & Technology","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116469624","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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