Pub Date : 2007-08-01DOI: 10.1109/ECCTD.2007.4529634
N. Petra, D. Caro, A. Strollo
In the paper a new GF(2m) multiplier for standard basis representation is developed. Proposed multiplier can be designed for every field GF(2m). Multiplier complexity and delay are analytically evaluated for many polynomial classes. Timing and area occupation performances of the proposed multiplier are compared with those of previously proposed solutions. The comparison shows that the proposed multiplier outperforms previous architectures for every considered GF(2m) field.
{"title":"High speed galois fields GF(2m) multipliers","authors":"N. Petra, D. Caro, A. Strollo","doi":"10.1109/ECCTD.2007.4529634","DOIUrl":"https://doi.org/10.1109/ECCTD.2007.4529634","url":null,"abstract":"In the paper a new GF(2m) multiplier for standard basis representation is developed. Proposed multiplier can be designed for every field GF(2m). Multiplier complexity and delay are analytically evaluated for many polynomial classes. Timing and area occupation performances of the proposed multiplier are compared with those of previously proposed solutions. The comparison shows that the proposed multiplier outperforms previous architectures for every considered GF(2m) field.","PeriodicalId":445822,"journal":{"name":"2007 18th European Conference on Circuit Theory and Design","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130993673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/ECCTD.2007.4529655
Lukas Dolivka, J. Hospodka
This paper describes a way to eliminate the effect of circuit nonidealities on the magnitude frequency response of a circuit utilizing the switched-current technique. The circuit realizes a band-pass filter. The elimination is carried out by optimization based on one of evolutionary algorithms - the differential evolution. The nonidealities are nonzero on-state resistance of the switches and nonzero output conductance of the field-effect transistors implementing the current sources. It is shown that the filter with the current source transconductance values designed according to a common method for ideal components has a significantly different magnitude frequency response when the nonidealities are considered. Hence, the optimization is applied to finding suitable transconductance values so that the difference between the magnitude frequency responses of the ideal and nonideal filter is minimized.
{"title":"Switched-current filter optimization based on evolutionary algorithms","authors":"Lukas Dolivka, J. Hospodka","doi":"10.1109/ECCTD.2007.4529655","DOIUrl":"https://doi.org/10.1109/ECCTD.2007.4529655","url":null,"abstract":"This paper describes a way to eliminate the effect of circuit nonidealities on the magnitude frequency response of a circuit utilizing the switched-current technique. The circuit realizes a band-pass filter. The elimination is carried out by optimization based on one of evolutionary algorithms - the differential evolution. The nonidealities are nonzero on-state resistance of the switches and nonzero output conductance of the field-effect transistors implementing the current sources. It is shown that the filter with the current source transconductance values designed according to a common method for ideal components has a significantly different magnitude frequency response when the nonidealities are considered. Hence, the optimization is applied to finding suitable transconductance values so that the difference between the magnitude frequency responses of the ideal and nonideal filter is minimized.","PeriodicalId":445822,"journal":{"name":"2007 18th European Conference on Circuit Theory and Design","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130365756","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/ECCTD.2007.4529737
F. Bizzarri, D. Linaro, M. Storace
A two-dimensional piecewise-linear approximation of the Hindmarsh-Rose neuron model is obtained, in view of its circuit implementation. The obtained approximation is checked by varying two bifurcation parameters. The brute-force two-dimensional bifurcation diagram of the original model is compared with the one of the piecewise-linear approximation, showing that the approximation is able to reproduce the main qualitative behaviours (quiescency, spiking, bursting, chaotic dynamics) of the original model.
{"title":"PWL approximation of the Hindmarsh-Rose neuron model in view of its circuit implementation","authors":"F. Bizzarri, D. Linaro, M. Storace","doi":"10.1109/ECCTD.2007.4529737","DOIUrl":"https://doi.org/10.1109/ECCTD.2007.4529737","url":null,"abstract":"A two-dimensional piecewise-linear approximation of the Hindmarsh-Rose neuron model is obtained, in view of its circuit implementation. The obtained approximation is checked by varying two bifurcation parameters. The brute-force two-dimensional bifurcation diagram of the original model is compared with the one of the piecewise-linear approximation, showing that the approximation is able to reproduce the main qualitative behaviours (quiescency, spiking, bursting, chaotic dynamics) of the original model.","PeriodicalId":445822,"journal":{"name":"2007 18th European Conference on Circuit Theory and Design","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123332094","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/ECCTD.2007.4529620
T. Paavle, P. Annus, A. Kuusik, R. Land, M. Min
Operation principles, modeling, and practical design of a novel system for bioimpedance (BI) measurement and monitoring are introduced in this paper. The system employs excitation and reference signals in a form of three-level rectangular waveforms with specially shortened duty cycles for eliminating some higher harmonics from the measured response. It enables to decrease systematic errors and ensures simplicity and power efficiency for wearable devices at the same time. The system is designed as a four-channel instrument, while both, the analog and digital approaches are discussed.
{"title":"Bioimpedance monitoring with improved accuracy using three-level stimulus","authors":"T. Paavle, P. Annus, A. Kuusik, R. Land, M. Min","doi":"10.1109/ECCTD.2007.4529620","DOIUrl":"https://doi.org/10.1109/ECCTD.2007.4529620","url":null,"abstract":"Operation principles, modeling, and practical design of a novel system for bioimpedance (BI) measurement and monitoring are introduced in this paper. The system employs excitation and reference signals in a form of three-level rectangular waveforms with specially shortened duty cycles for eliminating some higher harmonics from the measured response. It enables to decrease systematic errors and ensures simplicity and power efficiency for wearable devices at the same time. The system is designed as a four-channel instrument, while both, the analog and digital approaches are discussed.","PeriodicalId":445822,"journal":{"name":"2007 18th European Conference on Circuit Theory and Design","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123354155","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/ECCTD.2007.4529698
M. Coulon, D. Roviras
This paper deals with the bit detection for an asynchronous transmission using a chaos-based multiple access system. Two kinds of detectors are studied: those based on a LMMSE approach, including an adaptive detector, and those based on the estimation of the users' chaotic sequences. Theoretical and simulated performance results are provided, which show the superiority of the first detectors, even when few a priori information concerning the channels is available.
{"title":"Multi-user detection for an asynchronous differential chaos-based multiple access system","authors":"M. Coulon, D. Roviras","doi":"10.1109/ECCTD.2007.4529698","DOIUrl":"https://doi.org/10.1109/ECCTD.2007.4529698","url":null,"abstract":"This paper deals with the bit detection for an asynchronous transmission using a chaos-based multiple access system. Two kinds of detectors are studied: those based on a LMMSE approach, including an adaptive detector, and those based on the estimation of the users' chaotic sequences. Theoretical and simulated performance results are provided, which show the superiority of the first detectors, even when few a priori information concerning the channels is available.","PeriodicalId":445822,"journal":{"name":"2007 18th European Conference on Circuit Theory and Design","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126369285","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/ECCTD.2007.4529757
M. Rahal, A. Demosthenous
The readout electronics for contact-less inductive position sensors are currently based on discrete solutions. To enhance overall system performance, the implementation of the readout electronics into a single ASIC is desirable. This paper discusses the key system blocks of the analog front-end. Two variants of the mixer architecture for the synchronous detection are examined in terms of their ability to reject phase-sensitive offsets. Simulated results using a 0.35-mum CMOS process technology are presented.
非接触式感应位置传感器的读出电子器件目前基于离散解决方案。为了提高整体系统性能，需要将读出电子器件实现到单个ASIC中。本文讨论了模拟前端的关键系统模块。同步检测的混频器结构的两种变体在其拒绝相敏偏移的能力方面进行了检查。给出了采用0.35 μ m CMOS工艺技术的仿真结果。
{"title":"A readout system for inductive position sensors","authors":"M. Rahal, A. Demosthenous","doi":"10.1109/ECCTD.2007.4529757","DOIUrl":"https://doi.org/10.1109/ECCTD.2007.4529757","url":null,"abstract":"The readout electronics for contact-less inductive position sensors are currently based on discrete solutions. To enhance overall system performance, the implementation of the readout electronics into a single ASIC is desirable. This paper discusses the key system blocks of the analog front-end. Two variants of the mixer architecture for the synchronous detection are examined in terms of their ability to reject phase-sensitive offsets. Simulated results using a 0.35-mum CMOS process technology are presented.","PeriodicalId":445822,"journal":{"name":"2007 18th European Conference on Circuit Theory and Design","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122274304","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/ECCTD.2007.4529648
Salvatore di Fazio, F. Pulvirenti, T. Signorelli, Christian Lao, S. Pennisi
The design of a very low-current transconductance operational amplifier specifically optimized for a switched-capacitor LCD column driver is presented. Despite its stringent standby current requirements (lower than 700 nA), the amplifier exhibits a DC gain of about 80 dB and, working in class AB, provides a slew rate greater than 20 V/mus under a load capacitance of 500 fF. The gain-bandwidth product and phase margin are about 2 MHz and 70deg. With exception of the DC gain, these performances represent a major improvement with respect to comparable solutions, and are obtained while halving the area occupation.
{"title":"Low quiescent current high speed amplifier for LCD column driver","authors":"Salvatore di Fazio, F. Pulvirenti, T. Signorelli, Christian Lao, S. Pennisi","doi":"10.1109/ECCTD.2007.4529648","DOIUrl":"https://doi.org/10.1109/ECCTD.2007.4529648","url":null,"abstract":"The design of a very low-current transconductance operational amplifier specifically optimized for a switched-capacitor LCD column driver is presented. Despite its stringent standby current requirements (lower than 700 nA), the amplifier exhibits a DC gain of about 80 dB and, working in class AB, provides a slew rate greater than 20 V/mus under a load capacitance of 500 fF. The gain-bandwidth product and phase margin are about 2 MHz and 70deg. With exception of the DC gain, these performances represent a major improvement with respect to comparable solutions, and are obtained while halving the area occupation.","PeriodicalId":445822,"journal":{"name":"2007 18th European Conference on Circuit Theory and Design","volume":"168 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121715614","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/ECCTD.2007.4529594
F. Corinto, V. Lanza, M. Gilli
Many mathematical models have been proposed to describe systems that present spatio-temporal patterns. Most of them are mainly phase models, where each oscillating cell is characterized in terms of a sole phase variable. It is well known that under suitable assumptions the global dynamics of networks composed by oscillators with weak connections can be investigated through phase models. In particular, the joint application of Malkin's Theorem and the describing function technique allows one to obtain an analytical approximation of the phase deviation equation for weakly connected networks that admit of a Lur'e representation. The aim of this manuscript is to provide a method for identifying the conditions under which weakly connected oscillatory systems exhibit given spatio-temporal patterns and to exploit the results for designing the corresponding networks.
{"title":"Design of bio-inspired network models for spatio-temporal pattern identification","authors":"F. Corinto, V. Lanza, M. Gilli","doi":"10.1109/ECCTD.2007.4529594","DOIUrl":"https://doi.org/10.1109/ECCTD.2007.4529594","url":null,"abstract":"Many mathematical models have been proposed to describe systems that present spatio-temporal patterns. Most of them are mainly phase models, where each oscillating cell is characterized in terms of a sole phase variable. It is well known that under suitable assumptions the global dynamics of networks composed by oscillators with weak connections can be investigated through phase models. In particular, the joint application of Malkin's Theorem and the describing function technique allows one to obtain an analytical approximation of the phase deviation equation for weakly connected networks that admit of a Lur'e representation. The aim of this manuscript is to provide a method for identifying the conditions under which weakly connected oscillatory systems exhibit given spatio-temporal patterns and to exploit the results for designing the corresponding networks.","PeriodicalId":445822,"journal":{"name":"2007 18th European Conference on Circuit Theory and Design","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121344905","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/ECCTD.2007.4529533
Min Xu, E. Rodríguez-Villegas
This paper presents a novel low voltage and low power continuous time sigma-delta modulator based on the floating gate MOS (FGMOS) transistors. The performance of the two main building blocks in the modulator, the continuous time integrator and the comparator, are achieved by exploiting the benefits of the FGMOS devices. It is proven that using FGMOS devices improves the circuit linearity and hence increases the dynamic range. The modulator, designed in AMS 0.35 mum technology, works at a supply voltage of 1 V, exhibits a dynamic range (DR) of 67 dB, signal-to-noise- ratio (SNR) of 63 dB and signal-to-noise-and-distortion-ratio (SNDR) of 60 dB of 2 kHz Bandwidth (BW), with a power consumption of 5 muW.
{"title":"A 1V low power sigma-delta modulator based on floating gate MOS transistors","authors":"Min Xu, E. Rodríguez-Villegas","doi":"10.1109/ECCTD.2007.4529533","DOIUrl":"https://doi.org/10.1109/ECCTD.2007.4529533","url":null,"abstract":"This paper presents a novel low voltage and low power continuous time sigma-delta modulator based on the floating gate MOS (FGMOS) transistors. The performance of the two main building blocks in the modulator, the continuous time integrator and the comparator, are achieved by exploiting the benefits of the FGMOS devices. It is proven that using FGMOS devices improves the circuit linearity and hence increases the dynamic range. The modulator, designed in AMS 0.35 mum technology, works at a supply voltage of 1 V, exhibits a dynamic range (DR) of 67 dB, signal-to-noise- ratio (SNR) of 63 dB and signal-to-noise-and-distortion-ratio (SNDR) of 60 dB of 2 kHz Bandwidth (BW), with a power consumption of 5 muW.","PeriodicalId":445822,"journal":{"name":"2007 18th European Conference on Circuit Theory and Design","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131510542","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/ECCTD.2007.4529708
Z. Marinković, O. Pronić-Rančić, V. Markovic
An application of artificial neural networks for accuracy improving of the microwave FET transistor noise modeling is presented in this paper. The proposed model is based on a basic transistor noise wave model whose noise wave temperatures are assumed to be constant over the operating frequency range. An artificial neural network is included in the model in order to make values of the noise parameters obtained by the original wave model more accurate.
{"title":"Improved noise wave model of microwave FETs based on artificial neural networks","authors":"Z. Marinković, O. Pronić-Rančić, V. Markovic","doi":"10.1109/ECCTD.2007.4529708","DOIUrl":"https://doi.org/10.1109/ECCTD.2007.4529708","url":null,"abstract":"An application of artificial neural networks for accuracy improving of the microwave FET transistor noise modeling is presented in this paper. The proposed model is based on a basic transistor noise wave model whose noise wave temperatures are assumed to be constant over the operating frequency range. An artificial neural network is included in the model in order to make values of the noise parameters obtained by the original wave model more accurate.","PeriodicalId":445822,"journal":{"name":"2007 18th European Conference on Circuit Theory and Design","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121864469","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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