Pub Date : 2007-08-01DOI: 10.1109/ECCTD.2007.4529586
M. Vidojkovic, M. Sanduleanu, J. D. V. Tang, P. Baltus, A. Roermund
In this paper a novel broadband, inductor-less, resistive-feedback, CMOS LNA is presented. The amplifier is designed for the frequency band 0.3 GHz-2 GHz. The measured voltage gain of the implemented LNA is 12 dB at 1 GHz and the 3 dB bandwidth is 2 GHz. An IIP3 of -16 dBm and a noise figure of 4 dB are measured at 900 MHz. The value of the measured IIP2 is -13 dBm. The Sll is better than -10 dB in the frequency band from 300 MHz up to 1 GHz. The power dissipation is 18 mW from a 1.2 V supply. The circuit is designed in a digital CMOS 90 nm low power (LP) process without extra process options.
{"title":"A broadband, inductorless LNA for multi-standard aplications","authors":"M. Vidojkovic, M. Sanduleanu, J. D. V. Tang, P. Baltus, A. Roermund","doi":"10.1109/ECCTD.2007.4529586","DOIUrl":"https://doi.org/10.1109/ECCTD.2007.4529586","url":null,"abstract":"In this paper a novel broadband, inductor-less, resistive-feedback, CMOS LNA is presented. The amplifier is designed for the frequency band 0.3 GHz-2 GHz. The measured voltage gain of the implemented LNA is 12 dB at 1 GHz and the 3 dB bandwidth is 2 GHz. An IIP3 of -16 dBm and a noise figure of 4 dB are measured at 900 MHz. The value of the measured IIP2 is -13 dBm. The Sll is better than -10 dB in the frequency band from 300 MHz up to 1 GHz. The power dissipation is 18 mW from a 1.2 V supply. The circuit is designed in a digital CMOS 90 nm low power (LP) process without extra process options.","PeriodicalId":445822,"journal":{"name":"2007 18th European Conference on Circuit Theory and Design","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132207229","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/ECCTD.2007.4529742
M. Ogata, T. Nishi
This paper presents an explicit expression for the product (DC power) of an averaged current and an averaged voltage of a switch in switching DC-DC converters and also derive conditions for it to be replaced by a diode (a passive switch).
{"title":"Topological conditions for passive switches in switching converters","authors":"M. Ogata, T. Nishi","doi":"10.1109/ECCTD.2007.4529742","DOIUrl":"https://doi.org/10.1109/ECCTD.2007.4529742","url":null,"abstract":"This paper presents an explicit expression for the product (DC power) of an averaged current and an averaged voltage of a switch in switching DC-DC converters and also derive conditions for it to be replaced by a diode (a passive switch).","PeriodicalId":445822,"journal":{"name":"2007 18th European Conference on Circuit Theory and Design","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133793153","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/ECCTD.2007.4529652
A. D. Grasso, S. Pennisi, F. Centurelli, G. Scotti, A. Trifiletti
A bias technique for low-voltage class AB amplifiers is presented. The approach exploits the bulk terminal to set the output quiescent current of a two-stage class-AB CMOS OTA in a reliable manner and without reducing the maximum swing capability. Simulations on a designed example using a 0.25-mum CMOS process show the viability of the approach.
提出了一种低压AB类放大器的偏置技术。该方法利用bulk端子可靠地设置两级ab类CMOS OTA的输出静态电流，且不降低最大摆幅能力。在0.25 μ m CMOS工艺设计实例上的仿真表明了该方法的可行性。
{"title":"CMOS Miller OTA with body-biased output stage","authors":"A. D. Grasso, S. Pennisi, F. Centurelli, G. Scotti, A. Trifiletti","doi":"10.1109/ECCTD.2007.4529652","DOIUrl":"https://doi.org/10.1109/ECCTD.2007.4529652","url":null,"abstract":"A bias technique for low-voltage class AB amplifiers is presented. The approach exploits the bulk terminal to set the output quiescent current of a two-stage class-AB CMOS OTA in a reliable manner and without reducing the maximum swing capability. Simulations on a designed example using a 0.25-mum CMOS process show the viability of the approach.","PeriodicalId":445822,"journal":{"name":"2007 18th European Conference on Circuit Theory and Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133191615","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/ECCTD.2007.4529581
Erik Säll, M. Vesterbacka
Decoders for low power, high-speed flash ADCs are investigated. The sensitivity to bubble errors of the ROM decoder with error correction, ones-counter, 4-level folded Wallace-tree, and multiplexer-based decoder are simulated. The ones-counter and multiplexer-based decoder, corresponding to the error insensitive and hardware efficient cases, are implemented in a 130 nm CMOS SOI technology. Measurements yield an ENOB of about 4.1 bit for both, and energy consumption of 80 pJ and 60 pJ, for the respective decoders. Hence we conclude that the MUX-based decoder seems to be a good choice with respect to area, efficiency, and speed.
{"title":"Thermometer-to-binary decoders for flash analog-to-digital converters","authors":"Erik Säll, M. Vesterbacka","doi":"10.1109/ECCTD.2007.4529581","DOIUrl":"https://doi.org/10.1109/ECCTD.2007.4529581","url":null,"abstract":"Decoders for low power, high-speed flash ADCs are investigated. The sensitivity to bubble errors of the ROM decoder with error correction, ones-counter, 4-level folded Wallace-tree, and multiplexer-based decoder are simulated. The ones-counter and multiplexer-based decoder, corresponding to the error insensitive and hardware efficient cases, are implemented in a 130 nm CMOS SOI technology. Measurements yield an ENOB of about 4.1 bit for both, and energy consumption of 80 pJ and 60 pJ, for the respective decoders. Hence we conclude that the MUX-based decoder seems to be a good choice with respect to area, efficiency, and speed.","PeriodicalId":445822,"journal":{"name":"2007 18th European Conference on Circuit Theory and Design","volume":"162 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132584173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/ECCTD.2007.4529755
N. Massari, S. A. Jawed, M. Gottardi
A new type of asynchronous time-based digital camera is here presented. The sensor architecture is characterized by a new analog low-power winner take all (WTA) network shared among all the pixels of the array. This circuit detects the most illuminated pixel and transmits it through the channel by queuing the other competitors. An iterative algorithm allows to read-out the entire array, temporally dispatching the information by means of an asynchronous read-out circuit placed at column and row level. The pixel, designed with a 0.35 mum CMOS technology and consisting of 28 transistors, performs a simulated average power consumption less than 10 nW @ 1.8 V for an impinging light power of 100 muW/cm2.
提出了一种新型的异步定时数码相机。该传感器结构的特点是在阵列的所有像素之间共享一种新的模拟低功耗赢家通吃(WTA)网络。该电路检测到最亮的像素，并通过通道将其他竞争对手排队传输。迭代算法允许读出整个数组，通过放置在列和行级别的异步读出电路暂时分派信息。该像素采用0.35 μ m CMOS技术设计，由28个晶体管组成，在入射光功率为100 μ w /cm2时，模拟平均功耗低于10 nW @ 1.8 V。
{"title":"A collision-free time-to-first spike camera architecture based on a winner-take-all network","authors":"N. Massari, S. A. Jawed, M. Gottardi","doi":"10.1109/ECCTD.2007.4529755","DOIUrl":"https://doi.org/10.1109/ECCTD.2007.4529755","url":null,"abstract":"A new type of asynchronous time-based digital camera is here presented. The sensor architecture is characterized by a new analog low-power winner take all (WTA) network shared among all the pixels of the array. This circuit detects the most illuminated pixel and transmits it through the channel by queuing the other competitors. An iterative algorithm allows to read-out the entire array, temporally dispatching the information by means of an asynchronous read-out circuit placed at column and row level. The pixel, designed with a 0.35 mum CMOS technology and consisting of 28 transistors, performs a simulated average power consumption less than 10 nW @ 1.8 V for an impinging light power of 100 muW/cm2.","PeriodicalId":445822,"journal":{"name":"2007 18th European Conference on Circuit Theory and Design","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133950043","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/ECCTD.2007.4529746
P. Maffezzoni, L. Codecasa, D. D’Amore, M. Santomauro
This paper provides an original closed-form expression of frequency-pulling phenomenon in unlocked-driven nonlinear oscillators. The formula employs the Floquet eigenvector that projects external perturbation into phase-domain and has the peculiarity to be very general being applicable to any oscillator topology.
{"title":"Closed-Form expression of frequency pulling in unlocked-driven nonlinear oscillators","authors":"P. Maffezzoni, L. Codecasa, D. D’Amore, M. Santomauro","doi":"10.1109/ECCTD.2007.4529746","DOIUrl":"https://doi.org/10.1109/ECCTD.2007.4529746","url":null,"abstract":"This paper provides an original closed-form expression of frequency-pulling phenomenon in unlocked-driven nonlinear oscillators. The formula employs the Floquet eigenvector that projects external perturbation into phase-domain and has the peculiarity to be very general being applicable to any oscillator topology.","PeriodicalId":445822,"journal":{"name":"2007 18th European Conference on Circuit Theory and Design","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114076442","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/ECCTD.2007.4529741
S. Harte, B. O’flynn, R. Catalá, E. Popovici
A miniaturised wireless sensor node with a high level of modularity is presented. A transceiver module with a size of 10 mm by 10 mm, operating in the 433/868 MHz frequency bands has been developed. An interface layer provides a regulated power supply from a rechargeable battery, USB battery charging, and USB communications to support the transceiver module. The node has been designed to support very low power operation for applications with low duty cycles, with a sleep current of 3.3 muA transmission current of 10.4 mA, and reception current of 13.3 mA. The small size combined with the level of modularity and energy efficiency results in the suitability of this system to a wide variety of potential applications. This paper discusses the design goals of the node, the decisions made during the design process, and characterisation of the resulting implementation.
{"title":"Design and implementation of a miniaturised, low power wireless sensor node","authors":"S. Harte, B. O’flynn, R. Catalá, E. Popovici","doi":"10.1109/ECCTD.2007.4529741","DOIUrl":"https://doi.org/10.1109/ECCTD.2007.4529741","url":null,"abstract":"A miniaturised wireless sensor node with a high level of modularity is presented. A transceiver module with a size of 10 mm by 10 mm, operating in the 433/868 MHz frequency bands has been developed. An interface layer provides a regulated power supply from a rechargeable battery, USB battery charging, and USB communications to support the transceiver module. The node has been designed to support very low power operation for applications with low duty cycles, with a sleep current of 3.3 muA transmission current of 10.4 mA, and reception current of 13.3 mA. The small size combined with the level of modularity and energy efficiency results in the suitability of this system to a wide variety of potential applications. This paper discusses the design goals of the node, the decisions made during the design process, and characterisation of the resulting implementation.","PeriodicalId":445822,"journal":{"name":"2007 18th European Conference on Circuit Theory and Design","volume":"210 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117030553","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/ECCTD.2007.4529556
Song-Bok Kim, S. Joeres, S. Heinen
Continuous-time (CT) SigmaDelta modulators seriously suffer from excess loop delay, which can not be seen in discrete-time designs. In this paper, it is shown that excess loop delay decreases the signal-to-noise ratio (SNR), input dynamic range (DR) and stability in CT complex SigmaDelta modulator with CIFF topology. A method for its compensation is presented. The proposed compensation scheme has a unity delay in front of the quantizer and complex compensation coefficients which are determined by analysis of the ideal DT loop filter transfer function. The simulation results are compared to analytical considerations.
{"title":"A compensation method of the excess loop delay in continuous-time complex sigma-delta modulators","authors":"Song-Bok Kim, S. Joeres, S. Heinen","doi":"10.1109/ECCTD.2007.4529556","DOIUrl":"https://doi.org/10.1109/ECCTD.2007.4529556","url":null,"abstract":"Continuous-time (CT) SigmaDelta modulators seriously suffer from excess loop delay, which can not be seen in discrete-time designs. In this paper, it is shown that excess loop delay decreases the signal-to-noise ratio (SNR), input dynamic range (DR) and stability in CT complex SigmaDelta modulator with CIFF topology. A method for its compensation is presented. The proposed compensation scheme has a unity delay in front of the quantizer and complex compensation coefficients which are determined by analysis of the ideal DT loop filter transfer function. The simulation results are compared to analytical considerations.","PeriodicalId":445822,"journal":{"name":"2007 18th European Conference on Circuit Theory and Design","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115515376","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/ECCTD.2007.4529531
J. M. Carrillo, J. L. Ausín, J. F. Duque-Carrillo
A continuous-time common-mode feedback (CMFB) network consisting of two unity-gain buffers and two passive resistors is introduced in this paper. According to the comparison with a previous implementation, the common-mode control structure presented shows an improved linearity performance as well as a higher immunity to device mismatches. The CMFB circuit has been included in the design of a fully differential voltage buffer, based on a fully differential difference amplifier. Simulated results, obtained in a 0.35-mum standard CMOS technology, are provided in order to show the performance of the proposed approach.
{"title":"CMOS continuous-time CMFB circuit with improved linearity","authors":"J. M. Carrillo, J. L. Ausín, J. F. Duque-Carrillo","doi":"10.1109/ECCTD.2007.4529531","DOIUrl":"https://doi.org/10.1109/ECCTD.2007.4529531","url":null,"abstract":"A continuous-time common-mode feedback (CMFB) network consisting of two unity-gain buffers and two passive resistors is introduced in this paper. According to the comparison with a previous implementation, the common-mode control structure presented shows an improved linearity performance as well as a higher immunity to device mismatches. The CMFB circuit has been included in the design of a fully differential voltage buffer, based on a fully differential difference amplifier. Simulated results, obtained in a 0.35-mum standard CMOS technology, are provided in order to show the performance of the proposed approach.","PeriodicalId":445822,"journal":{"name":"2007 18th European Conference on Circuit Theory and Design","volume":"318 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115246060","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/ECCTD.2007.4529686
G. Caruso, A. Macchiarella
In this paper, a low-power design method for MCML based ring oscillators is presented. The proposed method takes into account the parasitic capacitances of the MOS transistors. To validate it, some ring oscillators with different oscillation frequencies were designed in a 0.18 mum CMOS technology. SPICE simulations demonstrate the effectiveness of the design method.
提出了一种基于MCML的环形振荡器的低功耗设计方法。该方法考虑了MOS晶体管的寄生电容。为了验证该方法，在0.18 μ m CMOS工艺下设计了不同振荡频率的环形振荡器。SPICE仿真验证了该设计方法的有效性。
{"title":"A design methodology for low-power MCML ring oscillators","authors":"G. Caruso, A. Macchiarella","doi":"10.1109/ECCTD.2007.4529686","DOIUrl":"https://doi.org/10.1109/ECCTD.2007.4529686","url":null,"abstract":"In this paper, a low-power design method for MCML based ring oscillators is presented. The proposed method takes into account the parasitic capacitances of the MOS transistors. To validate it, some ring oscillators with different oscillation frequencies were designed in a 0.18 mum CMOS technology. SPICE simulations demonstrate the effectiveness of the design method.","PeriodicalId":445822,"journal":{"name":"2007 18th European Conference on Circuit Theory and Design","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121198250","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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