Pub Date : 2007-08-01DOI: 10.1109/ECCTD.2007.4529746
P. Maffezzoni, L. Codecasa, D. D’Amore, M. Santomauro
This paper provides an original closed-form expression of frequency-pulling phenomenon in unlocked-driven nonlinear oscillators. The formula employs the Floquet eigenvector that projects external perturbation into phase-domain and has the peculiarity to be very general being applicable to any oscillator topology.
{"title":"Closed-Form expression of frequency pulling in unlocked-driven nonlinear oscillators","authors":"P. Maffezzoni, L. Codecasa, D. D’Amore, M. Santomauro","doi":"10.1109/ECCTD.2007.4529746","DOIUrl":"https://doi.org/10.1109/ECCTD.2007.4529746","url":null,"abstract":"This paper provides an original closed-form expression of frequency-pulling phenomenon in unlocked-driven nonlinear oscillators. The formula employs the Floquet eigenvector that projects external perturbation into phase-domain and has the peculiarity to be very general being applicable to any oscillator topology.","PeriodicalId":445822,"journal":{"name":"2007 18th European Conference on Circuit Theory and Design","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114076442","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/ECCTD.2007.4529573
H. Hong, M. Rahal, A. Demosthenous, R. Bayford
The design of a current source for wideband electrical impedance tomography medical instrumentation is a challenging task. This paper describes two simple OTA-based floating voltage-controlled current sources (VCCSs) for this application. Both designs are suitable for VLSI implementation and overcome the drawbacks of existing opamp-based discrete VCCS designs. The floating VCCSs are designed to drive loads of 100 Omega to 2 kOmega with current amplitudes of up to 500 muA. The working frequency band is between 100 Hz to 1 MHz. Simulated results using a 0.35-mum CMOS process technology are presented to show the operation of the circuits.
宽带电阻抗断层成像医疗仪器的电流源设计是一项具有挑战性的任务。本文介绍了两种简单的基于ota的浮动压控电流源(VCCSs)。这两种设计都适合VLSI实现，克服了现有基于运算放大器的离散VCCS设计的缺点。浮动vccs设计用于驱动100 ω至2 kω的负载，电流幅值高达500 muA。工作频段为100hz ~ 1mhz。采用0.35 μ m CMOS工艺技术，给出了电路的仿真结果。
{"title":"Floating voltage-controlled current sources for electrical impedance tomography","authors":"H. Hong, M. Rahal, A. Demosthenous, R. Bayford","doi":"10.1109/ECCTD.2007.4529573","DOIUrl":"https://doi.org/10.1109/ECCTD.2007.4529573","url":null,"abstract":"The design of a current source for wideband electrical impedance tomography medical instrumentation is a challenging task. This paper describes two simple OTA-based floating voltage-controlled current sources (VCCSs) for this application. Both designs are suitable for VLSI implementation and overcome the drawbacks of existing opamp-based discrete VCCS designs. The floating VCCSs are designed to drive loads of 100 Omega to 2 kOmega with current amplitudes of up to 500 muA. The working frequency band is between 100 Hz to 1 MHz. Simulated results using a 0.35-mum CMOS process technology are presented to show the operation of the circuits.","PeriodicalId":445822,"journal":{"name":"2007 18th European Conference on Circuit Theory and Design","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123813509","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/ECCTD.2007.4529674
Fabio Pareschi, R. Rovatti, G. Setti
The use of second-level testing to reduce Type II errors in RNG validation was suggested from the very beginning though rarely employed in real-world cases. Yet, as security requirements become more critical and the availability of even faster RNG more commonplace, second-level testing will be key to distinguishing RNGs based on the quality of very large chunks of their output. This paper addresses some principles governing the proper design of second-level tests (i.e. how to divide available data into chunks and how to compute second-level p-values) as well as its implications on the design of the underlying basic tests.
{"title":"Second-level testing revisited and applications to NIST SP800-22","authors":"Fabio Pareschi, R. Rovatti, G. Setti","doi":"10.1109/ECCTD.2007.4529674","DOIUrl":"https://doi.org/10.1109/ECCTD.2007.4529674","url":null,"abstract":"The use of second-level testing to reduce Type II errors in RNG validation was suggested from the very beginning though rarely employed in real-world cases. Yet, as security requirements become more critical and the availability of even faster RNG more commonplace, second-level testing will be key to distinguishing RNGs based on the quality of very large chunks of their output. This paper addresses some principles governing the proper design of second-level tests (i.e. how to divide available data into chunks and how to compute second-level p-values) as well as its implications on the design of the underlying basic tests.","PeriodicalId":445822,"journal":{"name":"2007 18th European Conference on Circuit Theory and Design","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123899496","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/ECCTD.2007.4529543
Natalia A. Fernandez-Garcia, J. Albó-Canals, V. Brea, J. Riera-Babures, D. Cabello, X. Vilasís-Cardona
The so-called split&shift (S&S) methodology has previously been introduced as an effective area saving technique for hardware implementation of cellular non-linear networks. This work provides the first experimental proof of such a methodology through a circuit implementation over an FPGA platform. Results of area, processing time and functionality of different instances of the S&S methodology are given.
{"title":"Verification of Split&Shift techniques for CNN hardware reduction","authors":"Natalia A. Fernandez-Garcia, J. Albó-Canals, V. Brea, J. Riera-Babures, D. Cabello, X. Vilasís-Cardona","doi":"10.1109/ECCTD.2007.4529543","DOIUrl":"https://doi.org/10.1109/ECCTD.2007.4529543","url":null,"abstract":"The so-called split&shift (S&S) methodology has previously been introduced as an effective area saving technique for hardware implementation of cellular non-linear networks. This work provides the first experimental proof of such a methodology through a circuit implementation over an FPGA platform. Results of area, processing time and functionality of different instances of the S&S methodology are given.","PeriodicalId":445822,"journal":{"name":"2007 18th European Conference on Circuit Theory and Design","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129215785","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/ECCTD.2007.4529632
D. Crookes, Richard M. Jiang
In this paper, we introduce a novel high-radix binary signed digit (BSD) serial-parallel multiplier suitable for low-power high-speed multiplication. The proposed N- bittimesN-bit radix-16 serial-parallel multiplier can reduce the number of accumulation cycles of partial products to as much as N/4, and eliminate most of the invertion operations which consume power in a conventional multiplier in generating the partial products. Unlike other high-radix methods, the pre-multiplication in the new algorithm employs a BSD method which requires no extra adder, and thus removes the extra delay for additions which hinders other high-radix algorithms.
{"title":"A low-power high-radix serial-parallel multiplier","authors":"D. Crookes, Richard M. Jiang","doi":"10.1109/ECCTD.2007.4529632","DOIUrl":"https://doi.org/10.1109/ECCTD.2007.4529632","url":null,"abstract":"In this paper, we introduce a novel high-radix binary signed digit (BSD) serial-parallel multiplier suitable for low-power high-speed multiplication. The proposed N- bittimesN-bit radix-16 serial-parallel multiplier can reduce the number of accumulation cycles of partial products to as much as N/4, and eliminate most of the invertion operations which consume power in a conventional multiplier in generating the partial products. Unlike other high-radix methods, the pre-multiplication in the new algorithm employs a BSD method which requires no extra adder, and thus removes the extra delay for additions which hinders other high-radix algorithms.","PeriodicalId":445822,"journal":{"name":"2007 18th European Conference on Circuit Theory and Design","volume":"117 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129460201","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/ECCTD.2007.4529689
Valeria Garofalo, E. Napoli, N. Petra, A. Strollo
A detailed analysis of different code compression algorithms is provided in this paper. The performances of the algorithms have been tested on ARM codes whose size is below 32 KB. Code compression performances have been considered including the compression overheads due to the decoding tables, to the alignment and to the tables for random access to the compressed code. We have analyzed Huffman, Tunstall, LZ77 and Class-based techniques. Optimal performances are provided by Class Based algorithms with an average compression ratio of 64%. For this algorithm we have realized a static decompression engine that provides, after an initial latency of three clock cycles, one 32b instruction for clock cycle.
{"title":"Code compression for ARM7 embedded systems","authors":"Valeria Garofalo, E. Napoli, N. Petra, A. Strollo","doi":"10.1109/ECCTD.2007.4529689","DOIUrl":"https://doi.org/10.1109/ECCTD.2007.4529689","url":null,"abstract":"A detailed analysis of different code compression algorithms is provided in this paper. The performances of the algorithms have been tested on ARM codes whose size is below 32 KB. Code compression performances have been considered including the compression overheads due to the decoding tables, to the alignment and to the tables for random access to the compressed code. We have analyzed Huffman, Tunstall, LZ77 and Class-based techniques. Optimal performances are provided by Class Based algorithms with an average compression ratio of 64%. For this algorithm we have realized a static decompression engine that provides, after an initial latency of three clock cycles, one 32b instruction for clock cycle.","PeriodicalId":445822,"journal":{"name":"2007 18th European Conference on Circuit Theory and Design","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125088211","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/ECCTD.2007.4529684
R. Mita, G. Palumbo
In this paper, a simple analytical model which allows the estimation of the propagation delay of an RC circuit with a linear input is presented. The closed-form model can be used to evaluate the propagation delay of CMOS gates or wires in modern VLSI and ULSI process. Despite its simplicity, the model error has a maximum value of 2 % and in general is lower than 1%.
{"title":"Highly-accurate propagation delay analytical model of an RC-circuit with a ramp input","authors":"R. Mita, G. Palumbo","doi":"10.1109/ECCTD.2007.4529684","DOIUrl":"https://doi.org/10.1109/ECCTD.2007.4529684","url":null,"abstract":"In this paper, a simple analytical model which allows the estimation of the propagation delay of an RC circuit with a linear input is presented. The closed-form model can be used to evaluate the propagation delay of CMOS gates or wires in modern VLSI and ULSI process. Despite its simplicity, the model error has a maximum value of 2 % and in general is lower than 1%.","PeriodicalId":445822,"journal":{"name":"2007 18th European Conference on Circuit Theory and Design","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123745490","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/ECCTD.2007.4529686
G. Caruso, A. Macchiarella
In this paper, a low-power design method for MCML based ring oscillators is presented. The proposed method takes into account the parasitic capacitances of the MOS transistors. To validate it, some ring oscillators with different oscillation frequencies were designed in a 0.18 mum CMOS technology. SPICE simulations demonstrate the effectiveness of the design method.
提出了一种基于MCML的环形振荡器的低功耗设计方法。该方法考虑了MOS晶体管的寄生电容。为了验证该方法，在0.18 μ m CMOS工艺下设计了不同振荡频率的环形振荡器。SPICE仿真验证了该设计方法的有效性。
{"title":"A design methodology for low-power MCML ring oscillators","authors":"G. Caruso, A. Macchiarella","doi":"10.1109/ECCTD.2007.4529686","DOIUrl":"https://doi.org/10.1109/ECCTD.2007.4529686","url":null,"abstract":"In this paper, a low-power design method for MCML based ring oscillators is presented. The proposed method takes into account the parasitic capacitances of the MOS transistors. To validate it, some ring oscillators with different oscillation frequencies were designed in a 0.18 mum CMOS technology. SPICE simulations demonstrate the effectiveness of the design method.","PeriodicalId":445822,"journal":{"name":"2007 18th European Conference on Circuit Theory and Design","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121198250","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/ECCTD.2007.4529716
José C. García, J. Montiel-Nelson, S. Nooshabadi
This paper proposes a high performance and low power bootstrapped CMOS level-converter (lf-converter) for level restoration from the low-swing on the interconnect line to high-swing at the receiver side. The proposed lf-converter reduces the power-delay product by 83% to 90%, in comparison with the previously reported bootstrapped level-converter circuit (lrc-converter), when implemented on 0.13 mum CMOS 1.2V technology. The active area for lf-converter is 18.7 mum2, which is 3.9% less than the counterpart lrc-converter circuit.
本文提出了一种高性能、低功耗自举CMOS电平转换器(lf-converter)，用于从互连线上的低摆幅电平恢复到接收侧的高摆幅电平。当采用0.13 μ m CMOS 1.2V技术实现时，与之前报道的自举电平转换电路(lrc-转换器)相比，所提出的lf转换器可将功率延迟产品降低83%至90%。lf变换器的有源面积为18.7 mm2，比lrc变换器的有源面积小3.9%。
{"title":"High performance bootstrapped CMOS low to high-swing level-converter for on-chip interconnects","authors":"José C. García, J. Montiel-Nelson, S. Nooshabadi","doi":"10.1109/ECCTD.2007.4529716","DOIUrl":"https://doi.org/10.1109/ECCTD.2007.4529716","url":null,"abstract":"This paper proposes a high performance and low power bootstrapped CMOS level-converter (lf-converter) for level restoration from the low-swing on the interconnect line to high-swing at the receiver side. The proposed lf-converter reduces the power-delay product by 83% to 90%, in comparison with the previously reported bootstrapped level-converter circuit (lrc-converter), when implemented on 0.13 mum CMOS 1.2V technology. The active area for lf-converter is 18.7 mum2, which is 3.9% less than the counterpart lrc-converter circuit.","PeriodicalId":445822,"journal":{"name":"2007 18th European Conference on Circuit Theory and Design","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126816648","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/ECCTD.2007.4529725
S. Moro, T. Matsumoto
In this paper, we discuss the synchronization phenomena in star-coupled Wien-bridge oscillators by investigating the power consumption of the system using the distorted waves with fundamental frequency component and third harmonics component. The results suggest that the harmonics component can govern the synchronization phenomena, and why 120deg phase shift is stably excited.
{"title":"Analysis of synchronization phenomena in star-coupled Wien-bridge oscillators using distorted waves","authors":"S. Moro, T. Matsumoto","doi":"10.1109/ECCTD.2007.4529725","DOIUrl":"https://doi.org/10.1109/ECCTD.2007.4529725","url":null,"abstract":"In this paper, we discuss the synchronization phenomena in star-coupled Wien-bridge oscillators by investigating the power consumption of the system using the distorted waves with fundamental frequency component and third harmonics component. The results suggest that the harmonics component can govern the synchronization phenomena, and why 120deg phase shift is stably excited.","PeriodicalId":445822,"journal":{"name":"2007 18th European Conference on Circuit Theory and Design","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127930649","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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