Pub Date : 2007-08-01DOI: 10.1109/ECCTD.2007.4529561
G. Boselli, G. Trucco, V. Liberali
In this paper, we discuss generation of digital switching noise and its propagation through substrate and interconnection parasitics. Effects of switching noise on analog voltage references and radio-frequency blocks are presented. Both simulated and measured results confirmed that crosstalk effects are strongly dependent on substrate and package type. Isolation strategies must be specifically designed for a mixed-signal chip, as they could even worse crosstalk if they are not properly designed accounting for values of parasitics.
{"title":"Effects of digital switching noise on analog circuits performance","authors":"G. Boselli, G. Trucco, V. Liberali","doi":"10.1109/ECCTD.2007.4529561","DOIUrl":"https://doi.org/10.1109/ECCTD.2007.4529561","url":null,"abstract":"In this paper, we discuss generation of digital switching noise and its propagation through substrate and interconnection parasitics. Effects of switching noise on analog voltage references and radio-frequency blocks are presented. Both simulated and measured results confirmed that crosstalk effects are strongly dependent on substrate and package type. Isolation strategies must be specifically designed for a mixed-signal chip, as they could even worse crosstalk if they are not properly designed accounting for values of parasitics.","PeriodicalId":445822,"journal":{"name":"2007 18th European Conference on Circuit Theory and Design","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128711105","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/ECCTD.2007.4529554
Artur Silva, N. Horta, J. Guilherme
This paper presents a multi-standard reconfigurable sigma-delta modulator, which is able to support the predictable standards of fourth generation of mobile communication systems (4G). Furthermore, the proposed architecture halves the number of required analog-to-digital converters in parallel receivers, by processing concurrently two different signals. The major design issues are outlined and operation modes are detailed. A system-level simulation is performed to demonstrate the feasibility of the presented solution.
{"title":"Design of a multimode reconfigurable sigma-delta converter for 4G wireless receivers","authors":"Artur Silva, N. Horta, J. Guilherme","doi":"10.1109/ECCTD.2007.4529554","DOIUrl":"https://doi.org/10.1109/ECCTD.2007.4529554","url":null,"abstract":"This paper presents a multi-standard reconfigurable sigma-delta modulator, which is able to support the predictable standards of fourth generation of mobile communication systems (4G). Furthermore, the proposed architecture halves the number of required analog-to-digital converters in parallel receivers, by processing concurrently two different signals. The major design issues are outlined and operation modes are detailed. A system-level simulation is performed to demonstrate the feasibility of the presented solution.","PeriodicalId":445822,"journal":{"name":"2007 18th European Conference on Circuit Theory and Design","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129134875","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/ECCTD.2007.4529742
M. Ogata, T. Nishi
This paper presents an explicit expression for the product (DC power) of an averaged current and an averaged voltage of a switch in switching DC-DC converters and also derive conditions for it to be replaced by a diode (a passive switch).
{"title":"Topological conditions for passive switches in switching converters","authors":"M. Ogata, T. Nishi","doi":"10.1109/ECCTD.2007.4529742","DOIUrl":"https://doi.org/10.1109/ECCTD.2007.4529742","url":null,"abstract":"This paper presents an explicit expression for the product (DC power) of an averaged current and an averaged voltage of a switch in switching DC-DC converters and also derive conditions for it to be replaced by a diode (a passive switch).","PeriodicalId":445822,"journal":{"name":"2007 18th European Conference on Circuit Theory and Design","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133793153","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/ECCTD.2007.4529643
N. Yildiz, V. Tavsanoglu
Cellular nonlinear/neural networks (CNN's) are one of the analog systems that is hard to emulate or simulate on digital systems. It is known that CNN systems are linear for Gabor-type spatial filters. Although it is possible to represent the state equations of the discrete CNN in matrix notation, it is almost impossible to implement the huge state matrix on a digital system without optimization. In this paper some well known linear equation solving methods are optimized for CNN and required computational powers and memories are compared.
{"title":"On the digital simulation of linear cellular neural networks","authors":"N. Yildiz, V. Tavsanoglu","doi":"10.1109/ECCTD.2007.4529643","DOIUrl":"https://doi.org/10.1109/ECCTD.2007.4529643","url":null,"abstract":"Cellular nonlinear/neural networks (CNN's) are one of the analog systems that is hard to emulate or simulate on digital systems. It is known that CNN systems are linear for Gabor-type spatial filters. Although it is possible to represent the state equations of the discrete CNN in matrix notation, it is almost impossible to implement the huge state matrix on a digital system without optimization. In this paper some well known linear equation solving methods are optimized for CNN and required computational powers and memories are compared.","PeriodicalId":445822,"journal":{"name":"2007 18th European Conference on Circuit Theory and Design","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122232605","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/ECCTD.2007.4529753
O. Boncalo, M. Udrescu, L. Prodan, M. Vladutiu, A. Amaricai
This paper addresses the problem of evaluating the fault tolerance algorithms and methodologies (FTAMs) for quantum circuits, by making use of fault injection techniques. The proposed mutant-based fault injection techniques are inspired from their classical counterparts [T.A. DeLong et al., 1996] [E. Jenn et al., 1994], and were adapted to the specific features of quantum computation, including the available error models [J. P. Hayes et al., 2004] [E. Knill et al., 1997]. The HDLs were employed in order to perform fault injection, due to their capacity of behavioral and structural circuit description, as well as their hierarchical features. Besides providing a much realistic description, the experimental simulated fault injection campaigns provide quantitative means for quantum fault tolerance assessment.
本文讨论了利用故障注入技术评估量子电路容错算法和方法的问题。本文提出的基于突变体的断层注入技术是从经典的断层注入技术中得到启发的[j]。Jenn et al.， 1994]，并适应了量子计算的具体特点，包括可用的误差模型[J]。李海涛，陈晓明，等。[j]。Knill等，1997]。由于hdl具有描述行为和结构电路的能力，以及其层次性，因此采用hdl进行故障注入。实验模拟的故障注入运动除了提供更真实的描述外，还为量子容错评估提供了定量手段。
{"title":"Assessing quantum circuits reliability with mutant-based simulated fault injection","authors":"O. Boncalo, M. Udrescu, L. Prodan, M. Vladutiu, A. Amaricai","doi":"10.1109/ECCTD.2007.4529753","DOIUrl":"https://doi.org/10.1109/ECCTD.2007.4529753","url":null,"abstract":"This paper addresses the problem of evaluating the fault tolerance algorithms and methodologies (FTAMs) for quantum circuits, by making use of fault injection techniques. The proposed mutant-based fault injection techniques are inspired from their classical counterparts [T.A. DeLong et al., 1996] [E. Jenn et al., 1994], and were adapted to the specific features of quantum computation, including the available error models [J. P. Hayes et al., 2004] [E. Knill et al., 1997]. The HDLs were employed in order to perform fault injection, due to their capacity of behavioral and structural circuit description, as well as their hierarchical features. Besides providing a much realistic description, the experimental simulated fault injection campaigns provide quantitative means for quantum fault tolerance assessment.","PeriodicalId":445822,"journal":{"name":"2007 18th European Conference on Circuit Theory and Design","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126992485","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/ECCTD.2007.4529699
Z. Galias, Xinghuo Yu
Zero-order holder discretization of two-dimensional sliding mode control system is studied. Steady-state behaviors are classified and their bounds are found. Conditions under which the system trajectory in the steady state spends at most two iterations on each side of the sliding surface are presented. The existence of complex switching patterns for arbitrarily small discretization steps is confirmed. Theoretical results are illustrated with simulation examples.
{"title":"Study of discretization of two-dimensional sliding mode control systems","authors":"Z. Galias, Xinghuo Yu","doi":"10.1109/ECCTD.2007.4529699","DOIUrl":"https://doi.org/10.1109/ECCTD.2007.4529699","url":null,"abstract":"Zero-order holder discretization of two-dimensional sliding mode control system is studied. Steady-state behaviors are classified and their bounds are found. Conditions under which the system trajectory in the steady state spends at most two iterations on each side of the sliding surface are presented. The existence of complex switching patterns for arbitrarily small discretization steps is confirmed. Theoretical results are illustrated with simulation examples.","PeriodicalId":445822,"journal":{"name":"2007 18th European Conference on Circuit Theory and Design","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130744923","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/ECCTD.2007.4529741
S. Harte, B. O’flynn, R. Catalá, E. Popovici
A miniaturised wireless sensor node with a high level of modularity is presented. A transceiver module with a size of 10 mm by 10 mm, operating in the 433/868 MHz frequency bands has been developed. An interface layer provides a regulated power supply from a rechargeable battery, USB battery charging, and USB communications to support the transceiver module. The node has been designed to support very low power operation for applications with low duty cycles, with a sleep current of 3.3 muA transmission current of 10.4 mA, and reception current of 13.3 mA. The small size combined with the level of modularity and energy efficiency results in the suitability of this system to a wide variety of potential applications. This paper discusses the design goals of the node, the decisions made during the design process, and characterisation of the resulting implementation.
{"title":"Design and implementation of a miniaturised, low power wireless sensor node","authors":"S. Harte, B. O’flynn, R. Catalá, E. Popovici","doi":"10.1109/ECCTD.2007.4529741","DOIUrl":"https://doi.org/10.1109/ECCTD.2007.4529741","url":null,"abstract":"A miniaturised wireless sensor node with a high level of modularity is presented. A transceiver module with a size of 10 mm by 10 mm, operating in the 433/868 MHz frequency bands has been developed. An interface layer provides a regulated power supply from a rechargeable battery, USB battery charging, and USB communications to support the transceiver module. The node has been designed to support very low power operation for applications with low duty cycles, with a sleep current of 3.3 muA transmission current of 10.4 mA, and reception current of 13.3 mA. The small size combined with the level of modularity and energy efficiency results in the suitability of this system to a wide variety of potential applications. This paper discusses the design goals of the node, the decisions made during the design process, and characterisation of the resulting implementation.","PeriodicalId":445822,"journal":{"name":"2007 18th European Conference on Circuit Theory and Design","volume":"210 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117030553","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/ECCTD.2007.4529581
Erik Säll, M. Vesterbacka
Decoders for low power, high-speed flash ADCs are investigated. The sensitivity to bubble errors of the ROM decoder with error correction, ones-counter, 4-level folded Wallace-tree, and multiplexer-based decoder are simulated. The ones-counter and multiplexer-based decoder, corresponding to the error insensitive and hardware efficient cases, are implemented in a 130 nm CMOS SOI technology. Measurements yield an ENOB of about 4.1 bit for both, and energy consumption of 80 pJ and 60 pJ, for the respective decoders. Hence we conclude that the MUX-based decoder seems to be a good choice with respect to area, efficiency, and speed.
{"title":"Thermometer-to-binary decoders for flash analog-to-digital converters","authors":"Erik Säll, M. Vesterbacka","doi":"10.1109/ECCTD.2007.4529581","DOIUrl":"https://doi.org/10.1109/ECCTD.2007.4529581","url":null,"abstract":"Decoders for low power, high-speed flash ADCs are investigated. The sensitivity to bubble errors of the ROM decoder with error correction, ones-counter, 4-level folded Wallace-tree, and multiplexer-based decoder are simulated. The ones-counter and multiplexer-based decoder, corresponding to the error insensitive and hardware efficient cases, are implemented in a 130 nm CMOS SOI technology. Measurements yield an ENOB of about 4.1 bit for both, and energy consumption of 80 pJ and 60 pJ, for the respective decoders. Hence we conclude that the MUX-based decoder seems to be a good choice with respect to area, efficiency, and speed.","PeriodicalId":445822,"journal":{"name":"2007 18th European Conference on Circuit Theory and Design","volume":"162 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132584173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/ECCTD.2007.4529566
Ümit Güz, Hakan Gürkan, B. Yarman
In this work, a new mathematical modeling approach is proposed for the representation of the speech and audio signals. This approach is based on the generation of the so called predefined signature sequence (PSS) and predefined envelope sequence (PES) sets. After the generation process of the PSS and PES sets, they are clustered by effective k-means clustering algorithm and the PSS and PES are redefined by using the centroids of the clusters. By using this approach, the drawbacks such as the size of the sets, speed of the reconstruction process (computational complexity) which arise in our proposed methods previously are highly eliminated. In spite of these improvements, the initial results proved that, the quality of the reconstructed signals remains within the limitations of the acceptable hearing quality.
{"title":"A new algorithm for high speed speech and audio coding","authors":"Ümit Güz, Hakan Gürkan, B. Yarman","doi":"10.1109/ECCTD.2007.4529566","DOIUrl":"https://doi.org/10.1109/ECCTD.2007.4529566","url":null,"abstract":"In this work, a new mathematical modeling approach is proposed for the representation of the speech and audio signals. This approach is based on the generation of the so called predefined signature sequence (PSS) and predefined envelope sequence (PES) sets. After the generation process of the PSS and PES sets, they are clustered by effective k-means clustering algorithm and the PSS and PES are redefined by using the centroids of the clusters. By using this approach, the drawbacks such as the size of the sets, speed of the reconstruction process (computational complexity) which arise in our proposed methods previously are highly eliminated. In spite of these improvements, the initial results proved that, the quality of the reconstructed signals remains within the limitations of the acceptable hearing quality.","PeriodicalId":445822,"journal":{"name":"2007 18th European Conference on Circuit Theory and Design","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128311919","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/ECCTD.2007.4529586
M. Vidojkovic, M. Sanduleanu, J. D. V. Tang, P. Baltus, A. Roermund
In this paper a novel broadband, inductor-less, resistive-feedback, CMOS LNA is presented. The amplifier is designed for the frequency band 0.3 GHz-2 GHz. The measured voltage gain of the implemented LNA is 12 dB at 1 GHz and the 3 dB bandwidth is 2 GHz. An IIP3 of -16 dBm and a noise figure of 4 dB are measured at 900 MHz. The value of the measured IIP2 is -13 dBm. The Sll is better than -10 dB in the frequency band from 300 MHz up to 1 GHz. The power dissipation is 18 mW from a 1.2 V supply. The circuit is designed in a digital CMOS 90 nm low power (LP) process without extra process options.
{"title":"A broadband, inductorless LNA for multi-standard aplications","authors":"M. Vidojkovic, M. Sanduleanu, J. D. V. Tang, P. Baltus, A. Roermund","doi":"10.1109/ECCTD.2007.4529586","DOIUrl":"https://doi.org/10.1109/ECCTD.2007.4529586","url":null,"abstract":"In this paper a novel broadband, inductor-less, resistive-feedback, CMOS LNA is presented. The amplifier is designed for the frequency band 0.3 GHz-2 GHz. The measured voltage gain of the implemented LNA is 12 dB at 1 GHz and the 3 dB bandwidth is 2 GHz. An IIP3 of -16 dBm and a noise figure of 4 dB are measured at 900 MHz. The value of the measured IIP2 is -13 dBm. The Sll is better than -10 dB in the frequency band from 300 MHz up to 1 GHz. The power dissipation is 18 mW from a 1.2 V supply. The circuit is designed in a digital CMOS 90 nm low power (LP) process without extra process options.","PeriodicalId":445822,"journal":{"name":"2007 18th European Conference on Circuit Theory and Design","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132207229","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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