Pub Date : 2007-08-01DOI: 10.1109/ECCTD.2007.4529548
P. Bruschi, N. Nizza, M. Dei, G. Barillaro
An interface circuit for integrated capacitive sensors with pulse width modulated output is presented. The circuit is based on an original architecture implementing offset and low frequency noise cancellation by means of chopper modulation. Electrical simulations, performed on a prototype designed using 0.32 mum/ 3.3 V CMOS devices, showed that a sensitivity to temperature lower than 10 ppm/degC with a power consumption of 66 muW can be obtained with this approach.
提出了一种脉冲宽度调制输出的集成电容式传感器接口电路。该电路基于原始结构，通过斩波调制实现偏移和低频噪声消除。在使用0.32 mum/ 3.3 V CMOS器件设计的原型上进行的电学模拟表明，该方法对温度的灵敏度低于10 ppm/℃，功耗为66 muW。
{"title":"A low power capacitance to pulse width converter for integrated sensors","authors":"P. Bruschi, N. Nizza, M. Dei, G. Barillaro","doi":"10.1109/ECCTD.2007.4529548","DOIUrl":"https://doi.org/10.1109/ECCTD.2007.4529548","url":null,"abstract":"An interface circuit for integrated capacitive sensors with pulse width modulated output is presented. The circuit is based on an original architecture implementing offset and low frequency noise cancellation by means of chopper modulation. Electrical simulations, performed on a prototype designed using 0.32 mum/ 3.3 V CMOS devices, showed that a sensitivity to temperature lower than 10 ppm/degC with a power consumption of 66 muW can be obtained with this approach.","PeriodicalId":445822,"journal":{"name":"2007 18th European Conference on Circuit Theory and Design","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127591922","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/ECCTD.2007.4529677
T. Addabbo, A. Fort, S. Rocchi, V. Vignoli
In this paper a novel family of maximum-period Nonlinear Congruential Generators (NLCGs) based on the digitized Renyi chaotic map is considered for the definition of hardware-efficient Pseudo Random Number Generators (PRNGs). In detail, a theoretical result is provided about the periodicity of the output sequences generated by the proposed NLCGs. Moreover, the distribution of the generated numbers is discussed, comparing the results obtained the proposed NLCGs with those obtainable from traditional PRNGs based on linear recurrences methods.
{"title":"On the generation of pseudo-random sequences exploiting digitized chaotic systems","authors":"T. Addabbo, A. Fort, S. Rocchi, V. Vignoli","doi":"10.1109/ECCTD.2007.4529677","DOIUrl":"https://doi.org/10.1109/ECCTD.2007.4529677","url":null,"abstract":"In this paper a novel family of maximum-period Nonlinear Congruential Generators (NLCGs) based on the digitized Renyi chaotic map is considered for the definition of hardware-efficient Pseudo Random Number Generators (PRNGs). In detail, a theoretical result is provided about the periodicity of the output sequences generated by the proposed NLCGs. Moreover, the distribution of the generated numbers is discussed, comparing the results obtained the proposed NLCGs with those obtainable from traditional PRNGs based on linear recurrences methods.","PeriodicalId":445822,"journal":{"name":"2007 18th European Conference on Circuit Theory and Design","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127974768","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/ECCTD.2007.4529749
Takuya Hamada, Y. Horio, K. Aihara
Recently, researchers attempt to use chaos in applications such as chaotic communication, chaotic encryption, combinatorial optimization problems and chaotic computation. Chaotic integrated circuits are essential for a practical implementation of a large-scale chaotic system. A chaotic oscillator based on hysteresis two-port voltage-controlled current sources (2P-VCCS) has been extensively studied. In this paper, we propose an IC implementation of the hysteresis 2P-VCCS chaotic circuit. A prototype chip is designed with MOSIS TSMC 0.35 mum CMOS process. Through SPICE simulations with Spectre and experiments on the prototype chip, we illustrate a variety of dynamics from the proposed circuit including a quad screw attractor.
{"title":"An IC implementation of a hysteresis two-port VCCS chaotic oscillator","authors":"Takuya Hamada, Y. Horio, K. Aihara","doi":"10.1109/ECCTD.2007.4529749","DOIUrl":"https://doi.org/10.1109/ECCTD.2007.4529749","url":null,"abstract":"Recently, researchers attempt to use chaos in applications such as chaotic communication, chaotic encryption, combinatorial optimization problems and chaotic computation. Chaotic integrated circuits are essential for a practical implementation of a large-scale chaotic system. A chaotic oscillator based on hysteresis two-port voltage-controlled current sources (2P-VCCS) has been extensively studied. In this paper, we propose an IC implementation of the hysteresis 2P-VCCS chaotic circuit. A prototype chip is designed with MOSIS TSMC 0.35 mum CMOS process. Through SPICE simulations with Spectre and experiments on the prototype chip, we illustrate a variety of dynamics from the proposed circuit including a quad screw attractor.","PeriodicalId":445822,"journal":{"name":"2007 18th European Conference on Circuit Theory and Design","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132666607","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/ECCTD.2007.4529628
B. Bechen, T. Boom, D. Weiler, B. Hosticka
In this paper the theoretical and practical minimum of the power consumption is investigated for 3 ADC architectures, which are predestined for low conversion speed and applications in low-power sensor readout circuits. The analysis is made for the switched capacitor versions of the SAR ADC, cyclic ADC and sigma-delta modulator. The theoretical limit of the power efficiency is investigated by a commonly used figure of merit (FOM). As a case study two low-power ADCs were designed and fabricated. In order to compare ADCs fabricated in different technologies a technology-independent FOM is introduced.
{"title":"Theoretical and practical minimum of the power Consumption of 3 ADCs in SC technique","authors":"B. Bechen, T. Boom, D. Weiler, B. Hosticka","doi":"10.1109/ECCTD.2007.4529628","DOIUrl":"https://doi.org/10.1109/ECCTD.2007.4529628","url":null,"abstract":"In this paper the theoretical and practical minimum of the power consumption is investigated for 3 ADC architectures, which are predestined for low conversion speed and applications in low-power sensor readout circuits. The analysis is made for the switched capacitor versions of the SAR ADC, cyclic ADC and sigma-delta modulator. The theoretical limit of the power efficiency is investigated by a commonly used figure of merit (FOM). As a case study two low-power ADCs were designed and fabricated. In order to compare ADCs fabricated in different technologies a technology-independent FOM is introduced.","PeriodicalId":445822,"journal":{"name":"2007 18th European Conference on Circuit Theory and Design","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133705956","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/ECCTD.2007.4529550
G. Giustolisi, G. Palumbo, E. Spitale
In this communication, we propose a compensation procedure for LDO regulators which exploits both a current/buffer amplifier Miller compensation and a standard Miller compensation. The analysis shows how to design the compensation network in order to guarantee the stability for all the loading conditions. The results are then used to design a LDO regulator which is stable for a load current range of 4 orders of magnitude (from 10 muA to 100 mA) without requiring an external off-chip capacitor with ESR. Simulations in good agreement with the theoretical results are also shown.
{"title":"LDO compensation strategy based on current buffer/amplifiers","authors":"G. Giustolisi, G. Palumbo, E. Spitale","doi":"10.1109/ECCTD.2007.4529550","DOIUrl":"https://doi.org/10.1109/ECCTD.2007.4529550","url":null,"abstract":"In this communication, we propose a compensation procedure for LDO regulators which exploits both a current/buffer amplifier Miller compensation and a standard Miller compensation. The analysis shows how to design the compensation network in order to guarantee the stability for all the loading conditions. The results are then used to design a LDO regulator which is stable for a load current range of 4 orders of magnitude (from 10 muA to 100 mA) without requiring an external off-chip capacitor with ESR. Simulations in good agreement with the theoretical results are also shown.","PeriodicalId":445822,"journal":{"name":"2007 18th European Conference on Circuit Theory and Design","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134624154","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/ECCTD.2007.4529609
M. Alioto, M. Poli, S. Rocchi, V. Vignoli
In this paper, a model of the bus power consumption able to predict the results of a multi-bit differential power attack (DPA) in symmetric-key cryptographic algorithm (e.g. AES, DES) is developed. The analytical results represent a theoretical basis to better understand the vulnerability to DPA attacks of cryptographic VLSI circuits. To the best of the authors' knowledge, this is the first paper that quantitatively evaluates the fundamental parameters that determine the effectiveness of DPA attacks to symmetric-key algorithms. The results are validated by means of SPICE simulations on the address bus of a MIPS32 architecture in a 0.18-mum CMOS technology, with the MIPS32 being modeled by an in-house cycle-accurate simulator.
本文建立了一种能够预测对称密钥加密算法(如AES、DES)中多位差分功率攻击(DPA)结果的总线功耗模型。分析结果为更好地理解加密VLSI电路的DPA攻击脆弱性提供了理论基础。据作者所知，这是第一篇定量评估决定DPA攻击对对称密钥算法有效性的基本参数的论文。采用0.18 μ m CMOS技术，在MIPS32架构的地址总线上进行SPICE仿真，并使用内部周期精确模拟器对MIPS32进行建模，验证了结果。
{"title":"A general model of DPA attacks to precharged busses in symmetric-key cryptographic algorithms","authors":"M. Alioto, M. Poli, S. Rocchi, V. Vignoli","doi":"10.1109/ECCTD.2007.4529609","DOIUrl":"https://doi.org/10.1109/ECCTD.2007.4529609","url":null,"abstract":"In this paper, a model of the bus power consumption able to predict the results of a multi-bit differential power attack (DPA) in symmetric-key cryptographic algorithm (e.g. AES, DES) is developed. The analytical results represent a theoretical basis to better understand the vulnerability to DPA attacks of cryptographic VLSI circuits. To the best of the authors' knowledge, this is the first paper that quantitatively evaluates the fundamental parameters that determine the effectiveness of DPA attacks to symmetric-key algorithms. The results are validated by means of SPICE simulations on the address bus of a MIPS32 architecture in a 0.18-mum CMOS technology, with the MIPS32 being modeled by an in-house cycle-accurate simulator.","PeriodicalId":445822,"journal":{"name":"2007 18th European Conference on Circuit Theory and Design","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134056215","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/ECCTD.2007.4529556
Song-Bok Kim, S. Joeres, S. Heinen
Continuous-time (CT) SigmaDelta modulators seriously suffer from excess loop delay, which can not be seen in discrete-time designs. In this paper, it is shown that excess loop delay decreases the signal-to-noise ratio (SNR), input dynamic range (DR) and stability in CT complex SigmaDelta modulator with CIFF topology. A method for its compensation is presented. The proposed compensation scheme has a unity delay in front of the quantizer and complex compensation coefficients which are determined by analysis of the ideal DT loop filter transfer function. The simulation results are compared to analytical considerations.
{"title":"A compensation method of the excess loop delay in continuous-time complex sigma-delta modulators","authors":"Song-Bok Kim, S. Joeres, S. Heinen","doi":"10.1109/ECCTD.2007.4529556","DOIUrl":"https://doi.org/10.1109/ECCTD.2007.4529556","url":null,"abstract":"Continuous-time (CT) SigmaDelta modulators seriously suffer from excess loop delay, which can not be seen in discrete-time designs. In this paper, it is shown that excess loop delay decreases the signal-to-noise ratio (SNR), input dynamic range (DR) and stability in CT complex SigmaDelta modulator with CIFF topology. A method for its compensation is presented. The proposed compensation scheme has a unity delay in front of the quantizer and complex compensation coefficients which are determined by analysis of the ideal DT loop filter transfer function. The simulation results are compared to analytical considerations.","PeriodicalId":445822,"journal":{"name":"2007 18th European Conference on Circuit Theory and Design","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115515376","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/ECCTD.2007.4529531
J. M. Carrillo, J. L. Ausín, J. F. Duque-Carrillo
A continuous-time common-mode feedback (CMFB) network consisting of two unity-gain buffers and two passive resistors is introduced in this paper. According to the comparison with a previous implementation, the common-mode control structure presented shows an improved linearity performance as well as a higher immunity to device mismatches. The CMFB circuit has been included in the design of a fully differential voltage buffer, based on a fully differential difference amplifier. Simulated results, obtained in a 0.35-mum standard CMOS technology, are provided in order to show the performance of the proposed approach.
{"title":"CMOS continuous-time CMFB circuit with improved linearity","authors":"J. M. Carrillo, J. L. Ausín, J. F. Duque-Carrillo","doi":"10.1109/ECCTD.2007.4529531","DOIUrl":"https://doi.org/10.1109/ECCTD.2007.4529531","url":null,"abstract":"A continuous-time common-mode feedback (CMFB) network consisting of two unity-gain buffers and two passive resistors is introduced in this paper. According to the comparison with a previous implementation, the common-mode control structure presented shows an improved linearity performance as well as a higher immunity to device mismatches. The CMFB circuit has been included in the design of a fully differential voltage buffer, based on a fully differential difference amplifier. Simulated results, obtained in a 0.35-mum standard CMOS technology, are provided in order to show the performance of the proposed approach.","PeriodicalId":445822,"journal":{"name":"2007 18th European Conference on Circuit Theory and Design","volume":"318 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115246060","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, a CMOS analog-to-digital converter (ADC) with an 8-bit 500 MSPS at 1.8 V is designed. The architecture of the proposed ADC is based on a Folding ADC with a cascaded-folding and a cascaded-interpolation structure. A self-linearized preamplifier with source degeneration technique and a folder averaging technique for the high-performance are introduced. Further, a novel auto-switching encoder is also proposed. The chip has been fabricated with 0.18mu m 1-poly 5-metal CMOS technology. The active chip area is 0.79 mm2 and it consumes about 200 mW at 1.8 V power supply. The DNL and INL are within plusmn0.6/plusmn0.6LSB, respectively. The measured result of SNDR is 47.05dB.
{"title":"Design of a 1.8V 8-bit 500MSPS folding-interpolation CMOS A/D converter with a folder averaging technique","authors":"Dongjin Lee, Jaewon Song, Jongha Shin, Sanghoon Hwang, Minkyu Song, Tad Wysocki","doi":"10.1109/ECCTD.2007.4529606","DOIUrl":"https://doi.org/10.1109/ECCTD.2007.4529606","url":null,"abstract":"In this paper, a CMOS analog-to-digital converter (ADC) with an 8-bit 500 MSPS at 1.8 V is designed. The architecture of the proposed ADC is based on a Folding ADC with a cascaded-folding and a cascaded-interpolation structure. A self-linearized preamplifier with source degeneration technique and a folder averaging technique for the high-performance are introduced. Further, a novel auto-switching encoder is also proposed. The chip has been fabricated with 0.18mu m 1-poly 5-metal CMOS technology. The active chip area is 0.79 mm2 and it consumes about 200 mW at 1.8 V power supply. The DNL and INL are within plusmn0.6/plusmn0.6LSB, respectively. The measured result of SNDR is 47.05dB.","PeriodicalId":445822,"journal":{"name":"2007 18th European Conference on Circuit Theory and Design","volume":"204 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123177020","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/ECCTD.2007.4529578
V. Turunen, Tero Nieminen, M. Kosunen, K. Halonen
This paper describes the design and implementation of a upconverting D/A converter (DAC). Designed converter is capable of upconverting two 12-bit 60 MHz (in-phase and quadrature) signal bands around 2.4 GHz radio frequency. Upconversion is implemented by reorganizing switching scheme of a traditional current-steering D/A converter. Designed with 0.13 mum CMOS process, total area and estimated power consumption including DSP are 8.14 mm2 and 520 mW respectively.
本文介绍了一种上变频数模转换器(DAC)的设计与实现。所设计的转换器能够在2.4 GHz无线电频率上下转换两个12位60 MHz(同相和正交)信号频段。上变频是通过对传统电流导向数模转换器的开关方案进行重组来实现的。采用0.13 μ m CMOS工艺设计，包括DSP在内的总面积和估计功耗分别为8.14 mm2和520 mW。
{"title":"12-bit 2.4 GHz D/A upconverter","authors":"V. Turunen, Tero Nieminen, M. Kosunen, K. Halonen","doi":"10.1109/ECCTD.2007.4529578","DOIUrl":"https://doi.org/10.1109/ECCTD.2007.4529578","url":null,"abstract":"This paper describes the design and implementation of a upconverting D/A converter (DAC). Designed converter is capable of upconverting two 12-bit 60 MHz (in-phase and quadrature) signal bands around 2.4 GHz radio frequency. Upconversion is implemented by reorganizing switching scheme of a traditional current-steering D/A converter. Designed with 0.13 mum CMOS process, total area and estimated power consumption including DSP are 8.14 mm2 and 520 mW respectively.","PeriodicalId":445822,"journal":{"name":"2007 18th European Conference on Circuit Theory and Design","volume":"210 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113977855","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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