Pub Date : 2013-12-01DOI: 10.1109/IDT.2013.6727089
R. Asif, M. S. BinMilha, A. Hussaini, R. Abd‐Alhameed, S. R. Jones, J. Noras, Jonathan Rodriguez
In this work we present the work on the equalization algorithms to be used in future orthogonally multiplexed wavelets based multi signaling communication systems. The performance of ZF and MMSE algorithms has been analyzed using SISO and MIMO communication models. The transmitted electromagnetic waves were subjected through Rayleigh multipath fading channel with AWGN. The results showed that the performance of both of the above mentioned algorithms is the same in SISO channel but in MIMO environment MMSE has better performance.
{"title":"Performance evaluation of ZF and MMSE equalizers for wavelets V-Blast","authors":"R. Asif, M. S. BinMilha, A. Hussaini, R. Abd‐Alhameed, S. R. Jones, J. Noras, Jonathan Rodriguez","doi":"10.1109/IDT.2013.6727089","DOIUrl":"https://doi.org/10.1109/IDT.2013.6727089","url":null,"abstract":"In this work we present the work on the equalization algorithms to be used in future orthogonally multiplexed wavelets based multi signaling communication systems. The performance of ZF and MMSE algorithms has been analyzed using SISO and MIMO communication models. The transmitted electromagnetic waves were subjected through Rayleigh multipath fading channel with AWGN. The results showed that the performance of both of the above mentioned algorithms is the same in SISO channel but in MIMO environment MMSE has better performance.","PeriodicalId":446826,"journal":{"name":"2013 8th IEEE Design and Test Symposium","volume":"132 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127007033","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/IDT.2013.6727122
Ahmed Nassar, F. Kurdahi
This paper presents a runtime verification (RV) framework on distributed shared-memory multiprocessors based on explicit functional/concurrency intent specification in the form of temporal logic properties. A generic programming model, that subsumes task and data parallelism, has been wrought along with an automata-based formulation of the RV problem. Algorithms are implemented for the construction and minimization of automata checkers that can be executed concurrently with multithreaded applications to assert their correct functioning. The needed architectural supporting mechanisms and the ensuing design tradeoffs are investigated using an approximately-timed transaction-level model. The simulation model confirms scalability of the proposed RV approach to large multiprocessor systems. It also quantifies the increase in the number of processors needed to replenish the monitoring-induced performance degradation.
{"title":"Architectural support for runtime verification on ccNUMA multiprocessors","authors":"Ahmed Nassar, F. Kurdahi","doi":"10.1109/IDT.2013.6727122","DOIUrl":"https://doi.org/10.1109/IDT.2013.6727122","url":null,"abstract":"This paper presents a runtime verification (RV) framework on distributed shared-memory multiprocessors based on explicit functional/concurrency intent specification in the form of temporal logic properties. A generic programming model, that subsumes task and data parallelism, has been wrought along with an automata-based formulation of the RV problem. Algorithms are implemented for the construction and minimization of automata checkers that can be executed concurrently with multithreaded applications to assert their correct functioning. The needed architectural supporting mechanisms and the ensuing design tradeoffs are investigated using an approximately-timed transaction-level model. The simulation model confirms scalability of the proposed RV approach to large multiprocessor systems. It also quantifies the increase in the number of processors needed to replenish the monitoring-induced performance degradation.","PeriodicalId":446826,"journal":{"name":"2013 8th IEEE Design and Test Symposium","volume":"414 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116522607","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/IDT.2013.6727146
H. Saleh, B. Mohammad
A universal floating-point fused dot-product (UFDP) unit is presented that is capable of performing floating-point multiplication and addition or subtraction operations on two pairs of data, floating-point multiply add operation on three data items, floating-point multiplication of two data items and floating-point addition or subtraction of two data items. The proposed UFDP unit could be used as the only floating-point primitive a processor needs, where it easily can replace a floating-point adder, multiplier, fused multiply-add and a fused dot-product unit. Due to the dominance of multiply-add and dot-product operations in audio and video processing algorithms this unit can lead to substantial performance enhancement. The synthesis results using 32nm industry standard-cell library shows that the proposed architecture occupies an area of approximately twice a basic floating-point multiplier, can perform all operations in less 160% of a basic floating-point operation and consumes 80% more than a basic floating-point multiplier.
{"title":"Universal fused floating-point dot-product unit (UFDP)","authors":"H. Saleh, B. Mohammad","doi":"10.1109/IDT.2013.6727146","DOIUrl":"https://doi.org/10.1109/IDT.2013.6727146","url":null,"abstract":"A universal floating-point fused dot-product (UFDP) unit is presented that is capable of performing floating-point multiplication and addition or subtraction operations on two pairs of data, floating-point multiply add operation on three data items, floating-point multiplication of two data items and floating-point addition or subtraction of two data items. The proposed UFDP unit could be used as the only floating-point primitive a processor needs, where it easily can replace a floating-point adder, multiplier, fused multiply-add and a fused dot-product unit. Due to the dominance of multiply-add and dot-product operations in audio and video processing algorithms this unit can lead to substantial performance enhancement. The synthesis results using 32nm industry standard-cell library shows that the proposed architecture occupies an area of approximately twice a basic floating-point multiplier, can perform all operations in less 160% of a basic floating-point operation and consumes 80% more than a basic floating-point multiplier.","PeriodicalId":446826,"journal":{"name":"2013 8th IEEE Design and Test Symposium","volume":"49 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128835083","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/IDT.2013.6727125
M. Neggazi, L. Hamami, A. Amira
In this paper, an energy aware real-time wireless fall detection system based on the multi-scale analysis is proposed. Furthermore, an efficient feature extraction and compression algorithm for high accuracy fall recognition is presented. The proposed algorithm is carried out on the low-power Shimmer sensing platform. The developed method aims to reduce the amount of 3D acceleration data for energy efficiency improvement of the energy-hungry wireless links. Interestingly, our results show an average power consumption of less than 60% on the Shimmer Bluetooth link. In addition, the average of the 3D acceleration data rate savings is about 87.5%. Moreover, the proposed energy-aware fall detection system has been proven to distinguish among falls and activities of daily living, and the accuracy has been evaluated in terms of specificity and sensitivity and has shown excellent results. The sparsity degree for an efficient representation of 3D acceleration signal and high fall detection accuracy rate is also studied. The percent error between the original and reconstruted 3D acceleration signal of 7% after applying compressive sensing would yield a space savings of 56%, for a sparsity S=77 and signal length N=512.
{"title":"A multi-scale analysis and compressive sensing based energy aware fall detection system","authors":"M. Neggazi, L. Hamami, A. Amira","doi":"10.1109/IDT.2013.6727125","DOIUrl":"https://doi.org/10.1109/IDT.2013.6727125","url":null,"abstract":"In this paper, an energy aware real-time wireless fall detection system based on the multi-scale analysis is proposed. Furthermore, an efficient feature extraction and compression algorithm for high accuracy fall recognition is presented. The proposed algorithm is carried out on the low-power Shimmer sensing platform. The developed method aims to reduce the amount of 3D acceleration data for energy efficiency improvement of the energy-hungry wireless links. Interestingly, our results show an average power consumption of less than 60% on the Shimmer Bluetooth link. In addition, the average of the 3D acceleration data rate savings is about 87.5%. Moreover, the proposed energy-aware fall detection system has been proven to distinguish among falls and activities of daily living, and the accuracy has been evaluated in terms of specificity and sensitivity and has shown excellent results. The sparsity degree for an efficient representation of 3D acceleration signal and high fall detection accuracy rate is also studied. The percent error between the original and reconstruted 3D acceleration signal of 7% after applying compressive sensing would yield a space savings of 56%, for a sparsity S=77 and signal length N=512.","PeriodicalId":446826,"journal":{"name":"2013 8th IEEE Design and Test Symposium","volume":"108 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125582389","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/IDT.2013.6727141
Y. Halawani, B. Mohammad, Dirar Humouz, M. Al-Qutayri, H. Saleh
Wireless sensor nodes (WSN) are used extensively to monitor a wide range of physical and environmental parameters. Data acquisition, processing, storage and transmission are mandatory requirements for different applications. These nodes are expected to generate a correct representation of the sensed quantities, which is then used to make various decisions and control actions. This means that the node requires more memory capabilities to store data either temporary or permanently. The collected data can then be used. As the monitoring device of WSN is increasingly mobile, the need for efficient power management (PM) techniques is becoming crucial in order to extend the lifetime of the battery-powered device. Energy is a critical performance metric in WSNs. Challenges facing WSN designers range from computational energy, energy consumption, energy source, communication channels, etc. A new emerging memory technology like memristor provides a good candidate for WSN PM. Memristor non-volatility features coupled with small size and low energy operation provide a normally-off instant-on mode of operation for the WSN; this will minimize the loss of energy to leakage power. The paper gives an insight about using memristor in a PM scheme at the system level.
{"title":"Memristor for energy efficient wireless sensor node","authors":"Y. Halawani, B. Mohammad, Dirar Humouz, M. Al-Qutayri, H. Saleh","doi":"10.1109/IDT.2013.6727141","DOIUrl":"https://doi.org/10.1109/IDT.2013.6727141","url":null,"abstract":"Wireless sensor nodes (WSN) are used extensively to monitor a wide range of physical and environmental parameters. Data acquisition, processing, storage and transmission are mandatory requirements for different applications. These nodes are expected to generate a correct representation of the sensed quantities, which is then used to make various decisions and control actions. This means that the node requires more memory capabilities to store data either temporary or permanently. The collected data can then be used. As the monitoring device of WSN is increasingly mobile, the need for efficient power management (PM) techniques is becoming crucial in order to extend the lifetime of the battery-powered device. Energy is a critical performance metric in WSNs. Challenges facing WSN designers range from computational energy, energy consumption, energy source, communication channels, etc. A new emerging memory technology like memristor provides a good candidate for WSN PM. Memristor non-volatility features coupled with small size and low energy operation provide a normally-off instant-on mode of operation for the WSN; this will minimize the loss of energy to leakage power. The paper gives an insight about using memristor in a PM scheme at the system level.","PeriodicalId":446826,"journal":{"name":"2013 8th IEEE Design and Test Symposium","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123090017","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/IDT.2013.6727135
O. Hammami
Network on chip are fundamental in the performance of complex system on chip. Numerous solutions have been proposed both for regular and irregular topologies. Irregular or custom topologies present numerous benefits with regard to area/performance optimizations and can be automatically generated through NOC synthesis flows. NOC synthesis generates NOC topologies from application requirements coregraphs. NOC synthesis techniques use either exact or heuristic techniques. So far NOC synthesis techniques have not been benchmarked against ITRS roadmaps. We propose in this paper to benchmark linear programming based NOC synthesis techniques using NOCBENCH v.1.0 benchmarks. The results show that new models and techniques are needed to overcome complexity of future manycore.
{"title":"NOC synthesis vs ITRS predictions: The challenges of linear programming based synthesis","authors":"O. Hammami","doi":"10.1109/IDT.2013.6727135","DOIUrl":"https://doi.org/10.1109/IDT.2013.6727135","url":null,"abstract":"Network on chip are fundamental in the performance of complex system on chip. Numerous solutions have been proposed both for regular and irregular topologies. Irregular or custom topologies present numerous benefits with regard to area/performance optimizations and can be automatically generated through NOC synthesis flows. NOC synthesis generates NOC topologies from application requirements coregraphs. NOC synthesis techniques use either exact or heuristic techniques. So far NOC synthesis techniques have not been benchmarked against ITRS roadmaps. We propose in this paper to benchmark linear programming based NOC synthesis techniques using NOCBENCH v.1.0 benchmarks. The results show that new models and techniques are needed to overcome complexity of future manycore.","PeriodicalId":446826,"journal":{"name":"2013 8th IEEE Design and Test Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129146968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/IDT.2013.6727092
D. Sabena, M. Reorda, L. Sterpone, P. Rech, L. Carro
Recently, General Purpose Graphic Processing Units (GPGPUs) have begun to be preferred to CPUs for several computationally intensive applications, not necessarily related to computer graphics. However, due to their complexity GPGPUs also show a relatively high sensitivity to soft errors. Hence, there is some interest in devising and applying software techniques able to exploit their computational power by just acting on the executed code. In this paper we report some preliminary results obtained by applying two different software redundancy techniques aimed at soft-error detection; these techniques are completely algorithm independent, and have been applied on a sample application running on a Commercial-Off-The-Shelf GPGPU. The results have been gathered resorting to a neutron testing campaign. Some experimental results, explaining the capabilities of the methods, are presented and commented.
最近，通用图形处理单元(General Purpose Graphic Processing unit, gpgpu)已经开始在一些计算密集型的应用中比cpu更受青睐，这些应用不一定与计算机图形学相关。然而，由于其复杂性，gpgpu对软误差也表现出相对较高的敏感性。因此，人们对设计和应用软件技术很感兴趣，这些软件技术能够通过仅作用于已执行的代码来利用它们的计算能力。本文报告了采用两种不同的软件冗余技术进行软错误检测的初步结果;这些技术是完全独立于算法的，并已应用于运行在商用现成GPGPU上的示例应用程序。结果是通过中子测试活动收集的。给出了一些实验结果，说明了该方法的能力，并对其进行了评论。
{"title":"On the evaluation of soft-errors detection techniques for GPGPUs","authors":"D. Sabena, M. Reorda, L. Sterpone, P. Rech, L. Carro","doi":"10.1109/IDT.2013.6727092","DOIUrl":"https://doi.org/10.1109/IDT.2013.6727092","url":null,"abstract":"Recently, General Purpose Graphic Processing Units (GPGPUs) have begun to be preferred to CPUs for several computationally intensive applications, not necessarily related to computer graphics. However, due to their complexity GPGPUs also show a relatively high sensitivity to soft errors. Hence, there is some interest in devising and applying software techniques able to exploit their computational power by just acting on the executed code. In this paper we report some preliminary results obtained by applying two different software redundancy techniques aimed at soft-error detection; these techniques are completely algorithm independent, and have been applied on a sample application running on a Commercial-Off-The-Shelf GPGPU. The results have been gathered resorting to a neutron testing campaign. Some experimental results, explaining the capabilities of the methods, are presented and commented.","PeriodicalId":446826,"journal":{"name":"2013 8th IEEE Design and Test Symposium","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133685572","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/IDT.2013.6727094
I. Agbo, Seyab Khan, S. Hamdioui
Bias Temperature Instability (BTI) - Negative BTI in PMOS and Positive BTI in NMOS transistors-has become a key reliability bottleneck in the nano-scaled era. This paper presents BTI impact on SRAM's sense amplifier of different technologies, a robust sense amplifier has a lower sensing delay and higher sensing voltage. The results show that as technology scales down (i.e., from 90nm to 65nm, and 45nm), BTI impact on sensing delay increases, while that on the sensing voltage decreases, causing the sense amplifier memory, hence to be less robust and reliable. In addition, the paper also investigate the use of supply voltage to reduce the BTI degradation. The result show that increasing the power supply can reduce the sense amplifier BTI degradadtion with 33% for sensing voltage and with 18% for sensing delay; leading to clear tradeoff engineering question between power and robustness.
{"title":"BTI impact on SRAM sense amplifier","authors":"I. Agbo, Seyab Khan, S. Hamdioui","doi":"10.1109/IDT.2013.6727094","DOIUrl":"https://doi.org/10.1109/IDT.2013.6727094","url":null,"abstract":"Bias Temperature Instability (BTI) - Negative BTI in PMOS and Positive BTI in NMOS transistors-has become a key reliability bottleneck in the nano-scaled era. This paper presents BTI impact on SRAM's sense amplifier of different technologies, a robust sense amplifier has a lower sensing delay and higher sensing voltage. The results show that as technology scales down (i.e., from 90nm to 65nm, and 45nm), BTI impact on sensing delay increases, while that on the sensing voltage decreases, causing the sense amplifier memory, hence to be less robust and reliable. In addition, the paper also investigate the use of supply voltage to reduce the BTI degradation. The result show that increasing the power supply can reduce the sense amplifier BTI degradadtion with 33% for sensing voltage and with 18% for sensing delay; leading to clear tradeoff engineering question between power and robustness.","PeriodicalId":446826,"journal":{"name":"2013 8th IEEE Design and Test Symposium","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123193929","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/IDT.2013.6727085
R. Asif, M. Usman, T. Ghazaany, A. Hussaini, R. Abd‐Alhameed, S. R. Jones, J. Noras, Jonathan Rodriguez
In this work we present the angle of arrival estimation techniques and their comparison at different values of SNR using a 5 element UCA. The techniques that have been considered include phase interferometry, Multiple Signal Classification and covariance. The results show that for very low values of SNR the performance of the covariance matrix based algorithm is the best but for slightly higher values of SNR, MUSIC algorithm outperforms covariance.
{"title":"Evaluation of the angle of arrival based techniques","authors":"R. Asif, M. Usman, T. Ghazaany, A. Hussaini, R. Abd‐Alhameed, S. R. Jones, J. Noras, Jonathan Rodriguez","doi":"10.1109/IDT.2013.6727085","DOIUrl":"https://doi.org/10.1109/IDT.2013.6727085","url":null,"abstract":"In this work we present the angle of arrival estimation techniques and their comparison at different values of SNR using a 5 element UCA. The techniques that have been considered include phase interferometry, Multiple Signal Classification and covariance. The results show that for very low values of SNR the performance of the covariance matrix based algorithm is the best but for slightly higher values of SNR, MUSIC algorithm outperforms covariance.","PeriodicalId":446826,"journal":{"name":"2013 8th IEEE Design and Test Symposium","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114408627","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/IDT.2013.6727129
F. Sahraoui, Ghaffari Fakhreddine, M. A. Benkhelifa, B. Granado
Single Event Upset (SEU) is a major concern for SRAM-based FPGAs where a simple bit-flip can lead to an abnormal execution. We present in this paper, a new fault tolerance method based on hardware BER (Backward Error Recovery) to protect/correct system against the occurrence of transient faults. We use the partial dynamic reconfiguration offered by Xilinx Virtex-5 FPGAs to ensure hardware checkpoint and upon detection of fault we use recovery. Our method has several advantages: first it is non-intrusive (no internal modification of hardware modules of the system), second it is not based on redundant hardware resources (like most methods in the literature), and finally it has a static area overhead ratio when applied to a system. To validate our approach, we implemented it on a Xilinx platform based on a Partial Reconfigurable Region (PRR).
{"title":"An efficient BER-based reliability method for SRAM-based FPGA","authors":"F. Sahraoui, Ghaffari Fakhreddine, M. A. Benkhelifa, B. Granado","doi":"10.1109/IDT.2013.6727129","DOIUrl":"https://doi.org/10.1109/IDT.2013.6727129","url":null,"abstract":"Single Event Upset (SEU) is a major concern for SRAM-based FPGAs where a simple bit-flip can lead to an abnormal execution. We present in this paper, a new fault tolerance method based on hardware BER (Backward Error Recovery) to protect/correct system against the occurrence of transient faults. We use the partial dynamic reconfiguration offered by Xilinx Virtex-5 FPGAs to ensure hardware checkpoint and upon detection of fault we use recovery. Our method has several advantages: first it is non-intrusive (no internal modification of hardware modules of the system), second it is not based on redundant hardware resources (like most methods in the literature), and finally it has a static area overhead ratio when applied to a system. To validate our approach, we implemented it on a Xilinx platform based on a Partial Reconfigurable Region (PRR).","PeriodicalId":446826,"journal":{"name":"2013 8th IEEE Design and Test Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129653827","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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