Pub Date : 2013-12-01DOI: 10.1109/IDT.2013.6727113
Saloni, M. Goswami, Babu R. Singh
Recent trends in mixed-signal design for wireless application require high speed, power-efficient ADCs. Flash ADC architecture is an optimum choice for speed but dissipates power exponentially with increase in resolution. The present work on 5-bit 1.5 GS/s ADC explores new architectural strategy of circuit design in optimizing the power using reduced comparator architecture. The proposed circuit using only 5 comparators when operated with 2.5 V supply, dissipates less (83mW) power and silicon area as compared to existing architectures. The proposed ADC offers an ENOB of 4.60 bits, SNR of 27.2dB, SFDR of 36.21dB, INL and DNL of 0.32L5B and 0.43L5B respectively when simulated using 500nm CMOS MOSIS (AMIS) C5X design kit.
{"title":"A 5-bit 1.5 GS/s ADC using reduced comparator architecture","authors":"Saloni, M. Goswami, Babu R. Singh","doi":"10.1109/IDT.2013.6727113","DOIUrl":"https://doi.org/10.1109/IDT.2013.6727113","url":null,"abstract":"Recent trends in mixed-signal design for wireless application require high speed, power-efficient ADCs. Flash ADC architecture is an optimum choice for speed but dissipates power exponentially with increase in resolution. The present work on 5-bit 1.5 GS/s ADC explores new architectural strategy of circuit design in optimizing the power using reduced comparator architecture. The proposed circuit using only 5 comparators when operated with 2.5 V supply, dissipates less (83mW) power and silicon area as compared to existing architectures. The proposed ADC offers an ENOB of 4.60 bits, SNR of 27.2dB, SFDR of 36.21dB, INL and DNL of 0.32L5B and 0.43L5B respectively when simulated using 500nm CMOS MOSIS (AMIS) C5X design kit.","PeriodicalId":446826,"journal":{"name":"2013 8th IEEE Design and Test Symposium","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125529329","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/IDT.2013.6727144
I. Voyiatzis, C. Efstathiou, C. Sgouropoulou
Transparent BIST schemes for RAM modules assure the preservation of the memory contents during periodic testing. Symmetric Transparent Built-in Self Test (BIST) schemes skip the signature prediction phase required in traditional transparent BIST, achieving considerable reduction in test time. In this work we propose a Symmetric transparent BIST scheme that can be utilized to serially apply march tests bit-by-bit to word-organized RAM's, in a transparent manner, in the sense that the initial contents of the RAM are preserved. To the best of our knowledge, this is the first scheme proposed in the open literature to target intraword faults in the concept of transparent BIST for RAMs.
{"title":"Transparent testing for intra-word memory faults","authors":"I. Voyiatzis, C. Efstathiou, C. Sgouropoulou","doi":"10.1109/IDT.2013.6727144","DOIUrl":"https://doi.org/10.1109/IDT.2013.6727144","url":null,"abstract":"Transparent BIST schemes for RAM modules assure the preservation of the memory contents during periodic testing. Symmetric Transparent Built-in Self Test (BIST) schemes skip the signature prediction phase required in traditional transparent BIST, achieving considerable reduction in test time. In this work we propose a Symmetric transparent BIST scheme that can be utilized to serially apply march tests bit-by-bit to word-organized RAM's, in a transparent manner, in the sense that the initial contents of the RAM are preserved. To the best of our knowledge, this is the first scheme proposed in the open literature to target intraword faults in the concept of transparent BIST for RAMs.","PeriodicalId":446826,"journal":{"name":"2013 8th IEEE Design and Test Symposium","volume":"228 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133134162","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-05-29DOI: 10.1109/IDT.2013.6727104
Amin Zafarian, Iraj Kalali Fard, A. Golmakani, J. Shirazi
A fully integrated low-noise amplifier (LNA) with 0.4V supply voltage and ultra low power consumption at 1.5GHz by folded cascode structure is presented. The proposed LNA is designed in a TSMC 0.18 μm CMOS technology, in which all transistors are biased in subthreshold region. Through the use of proposed circuit for gain enhancement in this structure and using forward body bias technique, a very high figure of merit is achieved, in comparison to similar structures. The LNA provides a power gain of 14.7dB with a noise figure of 2.9dB while consuming only 790μW dc power. Also, impedance matching of input and output of the circuit in its operating frequency is desirable and in the whole bandwidth of the circuit, input and output isolation is below -33dB.
{"title":"A 0.4V 790μw CMOS low noise amplifier in sub-threshold region at 1.5GHz","authors":"Amin Zafarian, Iraj Kalali Fard, A. Golmakani, J. Shirazi","doi":"10.1109/IDT.2013.6727104","DOIUrl":"https://doi.org/10.1109/IDT.2013.6727104","url":null,"abstract":"A fully integrated low-noise amplifier (LNA) with 0.4V supply voltage and ultra low power consumption at 1.5GHz by folded cascode structure is presented. The proposed LNA is designed in a TSMC 0.18 μm CMOS technology, in which all transistors are biased in subthreshold region. Through the use of proposed circuit for gain enhancement in this structure and using forward body bias technique, a very high figure of merit is achieved, in comparison to similar structures. The LNA provides a power gain of 14.7dB with a noise figure of 2.9dB while consuming only 790μW dc power. Also, impedance matching of input and output of the circuit in its operating frequency is desirable and in the whole bandwidth of the circuit, input and output isolation is below -33dB.","PeriodicalId":446826,"journal":{"name":"2013 8th IEEE Design and Test Symposium","volume":"520 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134404844","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-10-29DOI: 10.1109/IDT.2013.6727131
Quang-Hai Khuat, Quang-Hoa Le, D. Chillet, S. Pillement
This article proposes a spatio-temporal scheduling algorithm for a three-dimensional integrated circuits (3D ICs) defined by stacking an homogeneous embedded Field-Programmable Gate Array (eFPGA) above an homogenous Chip MultiProcessor (CMP) layer over through-silicon vias (TSVs) connection. Our proposal, based on Proportionate-fair (Pfair) algorithm, computes the spatio-temporal scheduling of hardware tasks on the reconfigurable resources by taking into account the communication between tasks and then places the associated software tasks on the multiprocessors layer. Compared to the “equivalent” solutions produced by the recursive Branch and Bound (BB) algorithm, our proposal shows up to 14,5% communication cost reduction.
{"title":"Spatio-temporal scheduling for 3D reconfigurable & multiprocessor architecture","authors":"Quang-Hai Khuat, Quang-Hoa Le, D. Chillet, S. Pillement","doi":"10.1109/IDT.2013.6727131","DOIUrl":"https://doi.org/10.1109/IDT.2013.6727131","url":null,"abstract":"This article proposes a spatio-temporal scheduling algorithm for a three-dimensional integrated circuits (3D ICs) defined by stacking an homogeneous embedded Field-Programmable Gate Array (eFPGA) above an homogenous Chip MultiProcessor (CMP) layer over through-silicon vias (TSVs) connection. Our proposal, based on Proportionate-fair (Pfair) algorithm, computes the spatio-temporal scheduling of hardware tasks on the reconfigurable resources by taking into account the communication between tasks and then places the associated software tasks on the multiprocessors layer. Compared to the “equivalent” solutions produced by the recursive Branch and Bound (BB) algorithm, our proposal shows up to 14,5% communication cost reduction.","PeriodicalId":446826,"journal":{"name":"2013 8th IEEE Design and Test Symposium","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124441117","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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