Pub Date : 2013-12-01DOI: 10.1109/IDT.2013.6727142
Hamad Marzouqi, M. Al-Qutayri, K. Salah
This paper proposes a 256 Redundant Signed Digits hardware multiplier based on Karatsuba that is suitable for prime field ECC processors. Redundant representation is essential for prime field ECC processors as the basis for carry free arithmetic. The proposed multiplier works by applying Karatsuba method at two levels where three recursively constructed blocks are used to perform large integer multiplication iteratively. Different design alternatives are presented and implemented in Xilinx Virtex-5 FPGA. A pipelined multiplier with a recursive blocks of size 64 digits can perform one full 256 RSD digits multiplication within 1.08μs, operating at maximum frequency of 61.91 MHz.
{"title":"RSD based Karatsuba multiplier for ECC processors","authors":"Hamad Marzouqi, M. Al-Qutayri, K. Salah","doi":"10.1109/IDT.2013.6727142","DOIUrl":"https://doi.org/10.1109/IDT.2013.6727142","url":null,"abstract":"This paper proposes a 256 Redundant Signed Digits hardware multiplier based on Karatsuba that is suitable for prime field ECC processors. Redundant representation is essential for prime field ECC processors as the basis for carry free arithmetic. The proposed multiplier works by applying Karatsuba method at two levels where three recursively constructed blocks are used to perform large integer multiplication iteratively. Different design alternatives are presented and implemented in Xilinx Virtex-5 FPGA. A pipelined multiplier with a recursive blocks of size 64 digits can perform one full 256 RSD digits multiplication within 1.08μs, operating at maximum frequency of 61.91 MHz.","PeriodicalId":446826,"journal":{"name":"2013 8th IEEE Design and Test Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130814780","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/IDT.2013.6727079
Rabab Ezz-Eldin, M. El-Moursy, H. Hamed
Asynchronous NoC switch is proposed as a robust design to mitigate the impact of process variation. Circuit analysis is used to evaluate the influence of process variation on both synchronous and asynchronous designs. The delay and throughput variation are evaluated with different technologies. Although the asynchronous switch has large delay variation as compared to synchronous switch, high throughput is achieved under high process variation conditions. The throughput remains unchanged under high process variation conditions in asynchronous NoC switch, while the throughput of synchronous switch is rapidly reduced at the same conditions.
{"title":"High throughput asynchronous NoC switch for high process variation","authors":"Rabab Ezz-Eldin, M. El-Moursy, H. Hamed","doi":"10.1109/IDT.2013.6727079","DOIUrl":"https://doi.org/10.1109/IDT.2013.6727079","url":null,"abstract":"Asynchronous NoC switch is proposed as a robust design to mitigate the impact of process variation. Circuit analysis is used to evaluate the influence of process variation on both synchronous and asynchronous designs. The delay and throughput variation are evaluated with different technologies. Although the asynchronous switch has large delay variation as compared to synchronous switch, high throughput is achieved under high process variation conditions. The throughput remains unchanged under high process variation conditions in asynchronous NoC switch, while the throughput of synchronous switch is rapidly reduced at the same conditions.","PeriodicalId":446826,"journal":{"name":"2013 8th IEEE Design and Test Symposium","volume":"44 6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120915819","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/IDT.2013.6727093
A. Benali, M. Bouya, M. Faqir, A. Amrani, M. Ghogho, A. Benabdellah
As the request for high preferment and reliable 3D Integrated Circuit (IC) packages is increasing. Investigations in this technology are accelerating with the aim to reduce both cost and size. Glass interposer is recently used in this domain, it represents an effective alternative to the silicon due to its low cost, ease manufacturing and low electrical parasitic effects and cross talk. Although, the study of the reliability of the Through Glass Via (TGV) and its most critical stress areas remains a major concern. This study is about the thermal stress simulation in the glass interposer used in a three dimensional (3D) miniaturized camera package, in which we are using the Finite Element Analysis (FEA) method within ANSYS software to analyze the thermal stress concentration areas and inspect the geometric parameters effect on the resulting stress in a single TGV 3D model. Results are relevant to the boundary conditions and material properties used through all simulations. This work can be implemented to optimize via geometry and the whole glass interposer used in the 3D packaging technology.
{"title":"Through glass via thermomechanical analysis: Geometrical parameters effect on thermal stress","authors":"A. Benali, M. Bouya, M. Faqir, A. Amrani, M. Ghogho, A. Benabdellah","doi":"10.1109/IDT.2013.6727093","DOIUrl":"https://doi.org/10.1109/IDT.2013.6727093","url":null,"abstract":"As the request for high preferment and reliable 3D Integrated Circuit (IC) packages is increasing. Investigations in this technology are accelerating with the aim to reduce both cost and size. Glass interposer is recently used in this domain, it represents an effective alternative to the silicon due to its low cost, ease manufacturing and low electrical parasitic effects and cross talk. Although, the study of the reliability of the Through Glass Via (TGV) and its most critical stress areas remains a major concern. This study is about the thermal stress simulation in the glass interposer used in a three dimensional (3D) miniaturized camera package, in which we are using the Finite Element Analysis (FEA) method within ANSYS software to analyze the thermal stress concentration areas and inspect the geometric parameters effect on the resulting stress in a single TGV 3D model. Results are relevant to the boundary conditions and material properties used through all simulations. This work can be implemented to optimize via geometry and the whole glass interposer used in the 3D packaging technology.","PeriodicalId":446826,"journal":{"name":"2013 8th IEEE Design and Test Symposium","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126178016","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/IDT.2013.6727112
G. H. Ibrahim, A. Hafez, A. Khalil
A digital detection scheme for demodulating QPSK signals is proposed. The proposed scheme can be a cascaded block following a super-regenerative oscillator that regenerates an input weak RF signal maintaining sent phase information. The detection scheme enables a simple and scalable implementation using digital logic gates and eliminates the need to downconversion step with accompanying PLL and mixers circuits. The resulting receiver would achieve lower power consumption figures than classical QPSK receivers based on direct downconversion.
{"title":"A simple digital detection scheme for demodulating QPSK signals in super-regenerative receiver architecture","authors":"G. H. Ibrahim, A. Hafez, A. Khalil","doi":"10.1109/IDT.2013.6727112","DOIUrl":"https://doi.org/10.1109/IDT.2013.6727112","url":null,"abstract":"A digital detection scheme for demodulating QPSK signals is proposed. The proposed scheme can be a cascaded block following a super-regenerative oscillator that regenerates an input weak RF signal maintaining sent phase information. The detection scheme enables a simple and scalable implementation using digital logic gates and eliminates the need to downconversion step with accompanying PLL and mixers circuits. The resulting receiver would achieve lower power consumption figures than classical QPSK receivers based on direct downconversion.","PeriodicalId":446826,"journal":{"name":"2013 8th IEEE Design and Test Symposium","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128157612","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/IDT.2013.6727133
P. Roy, M. R. Patra, H. Rahaman, P. Dasgupta
A second generation lab-on-chip device termed as digital microfluidic biochip is developed as a time-multiplexed reconfigurable device capable of executing multiple bioassay protocols simultaneously on a single 2D planar array. They combine biology with electronics and integrate various bioassay operations namely sample preparation, analysis, separation and detection. Optical detection, processing and analysis are considered to be of major significance as these may influence the decisions on diagnosis, detection and testing. In this paper we initially propose two separate circuit designs of digital detection analyzer to be coupled with a biochip for execution of prescheduled bioassay protocols. The two types of analyzers enable automated detailed analysis of the optical detection results based on the data acquired at the detection site through successful Biochip operation for a) homogeneous droplet samples and b) heterogeneous droplet samples. A third circuit that integrates the previous two designs for dual mode operation is also proposed. Synthesis and simulation of all the three proposed designs are carried out using pre-characterized reference data for measurement of different parameters of human blood samples and the corresponding final detection results are displayed and verified successfully.
{"title":"Novel designs of digital detection analyzer for intelligent detection and analysis in digital microfluidic biochips","authors":"P. Roy, M. R. Patra, H. Rahaman, P. Dasgupta","doi":"10.1109/IDT.2013.6727133","DOIUrl":"https://doi.org/10.1109/IDT.2013.6727133","url":null,"abstract":"A second generation lab-on-chip device termed as digital microfluidic biochip is developed as a time-multiplexed reconfigurable device capable of executing multiple bioassay protocols simultaneously on a single 2D planar array. They combine biology with electronics and integrate various bioassay operations namely sample preparation, analysis, separation and detection. Optical detection, processing and analysis are considered to be of major significance as these may influence the decisions on diagnosis, detection and testing. In this paper we initially propose two separate circuit designs of digital detection analyzer to be coupled with a biochip for execution of prescheduled bioassay protocols. The two types of analyzers enable automated detailed analysis of the optical detection results based on the data acquired at the detection site through successful Biochip operation for a) homogeneous droplet samples and b) heterogeneous droplet samples. A third circuit that integrates the previous two designs for dual mode operation is also proposed. Synthesis and simulation of all the three proposed designs are carried out using pre-characterized reference data for measurement of different parameters of human blood samples and the corresponding final detection results are displayed and verified successfully.","PeriodicalId":446826,"journal":{"name":"2013 8th IEEE Design and Test Symposium","volume":"2020 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114500126","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/IDT.2013.6727137
O. O. Anoh, R. Abd‐Alhameed, S. R. Jones, J. Noras, Y. A. Dama, A. Altimimi, N. Ali, M. Alkhambashi
Wavelets are constructed from the basis sets of their parent scaling functions of the two-scale dilation equation (1). Whereas orthogonal wavelets come from one orthogonal basis set, the biorthogonal wavelets project from different basis sets. Each basis set is correspondingly weighted to form filters, either highpass or lowpass, which form the constituents of quadrature mirror filter (QMF) banks. Consequently, these filters can be used to design wavelets, the differently weighted parameters contributing respective wavelet properties which influence the performance of the transforms in applications, for example multicarrier modulation. This study investigated applications for onward multicarrier modulation applications. The results show that the optimum choice of particular wavelet adopted in digital multicarrier communication signal processing may be quite different from choices in other areas of wavelet applications, for example image and video compression.
{"title":"Comparison of orthogonal and biorthogonal wavelets for multicarrier systems","authors":"O. O. Anoh, R. Abd‐Alhameed, S. R. Jones, J. Noras, Y. A. Dama, A. Altimimi, N. Ali, M. Alkhambashi","doi":"10.1109/IDT.2013.6727137","DOIUrl":"https://doi.org/10.1109/IDT.2013.6727137","url":null,"abstract":"Wavelets are constructed from the basis sets of their parent scaling functions of the two-scale dilation equation (1). Whereas orthogonal wavelets come from one orthogonal basis set, the biorthogonal wavelets project from different basis sets. Each basis set is correspondingly weighted to form filters, either highpass or lowpass, which form the constituents of quadrature mirror filter (QMF) banks. Consequently, these filters can be used to design wavelets, the differently weighted parameters contributing respective wavelet properties which influence the performance of the transforms in applications, for example multicarrier modulation. This study investigated applications for onward multicarrier modulation applications. The results show that the optimum choice of particular wavelet adopted in digital multicarrier communication signal processing may be quite different from choices in other areas of wavelet applications, for example image and video compression.","PeriodicalId":446826,"journal":{"name":"2013 8th IEEE Design and Test Symposium","volume":"104 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133167400","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/IDT.2013.6727106
W. El-Halwagy, M. Dessouky, H. El-Ghitani
This paper analyzes an analog technique for VCO linearization based on a switched-capacitor feedback loop. The analysis covers both inversely and directly proportional VCOs. Based on this analysis, design criteria for determining the best loop parameters are presented using a look-up table. In addition, the tradeoffs between the linearized VCO tuning range, dynamic range, and loop settling speed are marked out. Simulation results show that the above analysis allowed the design of a linearization loop which improved the non-linearity of a 2 GHz tuning range VCO from 8% to 0.4%.
{"title":"Analysis and design of analog-based voltage controlled oscillator linearization technique","authors":"W. El-Halwagy, M. Dessouky, H. El-Ghitani","doi":"10.1109/IDT.2013.6727106","DOIUrl":"https://doi.org/10.1109/IDT.2013.6727106","url":null,"abstract":"This paper analyzes an analog technique for VCO linearization based on a switched-capacitor feedback loop. The analysis covers both inversely and directly proportional VCOs. Based on this analysis, design criteria for determining the best loop parameters are presented using a look-up table. In addition, the tradeoffs between the linearized VCO tuning range, dynamic range, and loop settling speed are marked out. Simulation results show that the above analysis allowed the design of a linearization loop which improved the non-linearity of a 2 GHz tuning range VCO from 8% to 0.4%.","PeriodicalId":446826,"journal":{"name":"2013 8th IEEE Design and Test Symposium","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131317552","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/IDT.2013.6727096
K. Salah
In this paper, a proposed through silicon via (TSV) structure is used to construct AC-DC converters. This structure is analyzed using 3D electromagnetic full-wave simulators. The results show that the proposed 3D converter exhibits small area with superior performance compared to a 2D transformer, for the same footprint as lossy substrate effects are neglected for low frequency range of interest for DC converters.
{"title":"A TSV-based architecture for AC-DC converters","authors":"K. Salah","doi":"10.1109/IDT.2013.6727096","DOIUrl":"https://doi.org/10.1109/IDT.2013.6727096","url":null,"abstract":"In this paper, a proposed through silicon via (TSV) structure is used to construct AC-DC converters. This structure is analyzed using 3D electromagnetic full-wave simulators. The results show that the proposed 3D converter exhibits small area with superior performance compared to a 2D transformer, for the same footprint as lossy substrate effects are neglected for low frequency range of interest for DC converters.","PeriodicalId":446826,"journal":{"name":"2013 8th IEEE Design and Test Symposium","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131995924","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/IDT.2013.6727127
S. Carlo, Giulio Gambardella, P. Lanza, P. Prinetto, Daniele Rolfo, Pascal Trotta
Video-based navigation is an increasingly used procedure with hard real-time requirements and high computational effort. In this field, FPGA hardware acceleration supplies low-cost and considerable performances enhancement. Video-based navigation algorithms extrapolate and correlate features from images, relying on their accuracy. Image enhancement provides more defined and contrasted frames, assuring high precision feature extraction. The paper introduces an FPGA-based self-adaptive image enhancer. The IP-core is suitable for hard-real time applications, such as space applications, thanks to the guaranteed high-throughput.
{"title":"SAFE: A self adaptive frame enhancer FPGA-based IP-core for real-time space applications","authors":"S. Carlo, Giulio Gambardella, P. Lanza, P. Prinetto, Daniele Rolfo, Pascal Trotta","doi":"10.1109/IDT.2013.6727127","DOIUrl":"https://doi.org/10.1109/IDT.2013.6727127","url":null,"abstract":"Video-based navigation is an increasingly used procedure with hard real-time requirements and high computational effort. In this field, FPGA hardware acceleration supplies low-cost and considerable performances enhancement. Video-based navigation algorithms extrapolate and correlate features from images, relying on their accuracy. Image enhancement provides more defined and contrasted frames, assuring high precision feature extraction. The paper introduces an FPGA-based self-adaptive image enhancer. The IP-core is suitable for hard-real time applications, such as space applications, thanks to the guaranteed high-throughput.","PeriodicalId":446826,"journal":{"name":"2013 8th IEEE Design and Test Symposium","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123499420","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/IDT.2013.6727147
I. Voyiatzis, Stelios N. Neophytou, M. Michael, Stavros Hadjitheophanous, C. Sgouropoulou, C. Efstathiou
In test set embedding Built-In Self Test (BIST) schemes a pre-computed test set is embedded into the sequence generated by a hardware generator. These schemes have to evaluate the location of each test pattern in the sequence as fast as possible, in order to test as many as possible candidate configurations of the test pattern generator; this problem is known as the test vector-embedding problem. In this paper we investigate the effect of the size of the test set on the length of the sequence generate of the accumulator structure in order to generate pre-computed test sets and present a method targeting hard-to-detect faults in order to drive down the test generation time.
{"title":"Test set embedding into accumulator-generated sequences targeting hard-to-detect faults","authors":"I. Voyiatzis, Stelios N. Neophytou, M. Michael, Stavros Hadjitheophanous, C. Sgouropoulou, C. Efstathiou","doi":"10.1109/IDT.2013.6727147","DOIUrl":"https://doi.org/10.1109/IDT.2013.6727147","url":null,"abstract":"In test set embedding Built-In Self Test (BIST) schemes a pre-computed test set is embedded into the sequence generated by a hardware generator. These schemes have to evaluate the location of each test pattern in the sequence as fast as possible, in order to test as many as possible candidate configurations of the test pattern generator; this problem is known as the test vector-embedding problem. In this paper we investigate the effect of the size of the test set on the length of the sequence generate of the accumulator structure in order to generate pre-computed test sets and present a method targeting hard-to-detect faults in order to drive down the test generation time.","PeriodicalId":446826,"journal":{"name":"2013 8th IEEE Design and Test Symposium","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127529267","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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