Pub Date : 2013-12-01DOI: 10.1109/IDT.2013.6727098
U. Schwalke, Frank Wessely, Tillmann A. Krauss
In CMOS technology, NMOS- and PMOS-FETs are hardware defined by choosing the appropriate doping of source (S) and drain (D) junctions with respect to the substrate. However, in this work we report on a novel CMOS multi-gate (MG) nanowire field-effect transistor (NWFET) architecture on silicon-on-insulator (SOI) material which is virtually free of doping. The MG-NWFETs are originally ambipolar nanowire devices with midgap Schottky-barriers serving as S/D contacts. A tri-gate structure is used as front-gate for current control across the NWFET whereas a planar back-gate is used to select the desired unipolar device type (i.e. NMOS or PMOS) via field-induced accumulation of electrons or holes, respectively. Both, logic and memory devices can be realized with the same simple nanowire structure. By means of 2D and 3D device simulation and subsequent experimental verification the potential of this novel reconfigurable device and circuit architecture will be demonstrated.
{"title":"Simulation and experimental verification: Dopant-free Si-nanowire CMOS technology on silicon-on-insulator material","authors":"U. Schwalke, Frank Wessely, Tillmann A. Krauss","doi":"10.1109/IDT.2013.6727098","DOIUrl":"https://doi.org/10.1109/IDT.2013.6727098","url":null,"abstract":"In CMOS technology, NMOS- and PMOS-FETs are hardware defined by choosing the appropriate doping of source (S) and drain (D) junctions with respect to the substrate. However, in this work we report on a novel CMOS multi-gate (MG) nanowire field-effect transistor (NWFET) architecture on silicon-on-insulator (SOI) material which is virtually free of doping. The MG-NWFETs are originally ambipolar nanowire devices with midgap Schottky-barriers serving as S/D contacts. A tri-gate structure is used as front-gate for current control across the NWFET whereas a planar back-gate is used to select the desired unipolar device type (i.e. NMOS or PMOS) via field-induced accumulation of electrons or holes, respectively. Both, logic and memory devices can be realized with the same simple nanowire structure. By means of 2D and 3D device simulation and subsequent experimental verification the potential of this novel reconfigurable device and circuit architecture will be demonstrated.","PeriodicalId":446826,"journal":{"name":"2013 8th IEEE Design and Test Symposium","volume":"531 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131533035","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/IDT.2013.6727091
I. Mezzah, O. Kermia, H. Chemali, Omar Abdelmalek, V. Beroulle, D. Hély
In this paper, we propose a new RFID tag monitoring approach, based on adding an infrastructure circuit to simultaneously monitor and save faulty tag behaviour, in order to enable the implementation of advanced RFID diagnosis functions and mainly to reinforce tag security against fault attacks. The added infrastructure circuit is essentially composed of hardware assertions exclusively devoted to on-line fault detection on the tag. Saved information about detected faults can then be read using RFID readers. Our approach is initially evaluated and implemented in a developed tag emulator platform based on an FPGA board, then thoroughly exercised to demonstrate its valuable contribution to diagnosis means. Experimental results, obtained via random fault injection mechanism, show the effectiveness of the proposed approach.
{"title":"Assertion based on-line fault detection applied on UHF RFID tag","authors":"I. Mezzah, O. Kermia, H. Chemali, Omar Abdelmalek, V. Beroulle, D. Hély","doi":"10.1109/IDT.2013.6727091","DOIUrl":"https://doi.org/10.1109/IDT.2013.6727091","url":null,"abstract":"In this paper, we propose a new RFID tag monitoring approach, based on adding an infrastructure circuit to simultaneously monitor and save faulty tag behaviour, in order to enable the implementation of advanced RFID diagnosis functions and mainly to reinforce tag security against fault attacks. The added infrastructure circuit is essentially composed of hardware assertions exclusively devoted to on-line fault detection on the tag. Saved information about detected faults can then be read using RFID readers. Our approach is initially evaluated and implemented in a developed tag emulator platform based on an FPGA board, then thoroughly exercised to demonstrate its valuable contribution to diagnosis means. Experimental results, obtained via random fault injection mechanism, show the effectiveness of the proposed approach.","PeriodicalId":446826,"journal":{"name":"2013 8th IEEE Design and Test Symposium","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114275389","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/IDT.2013.6727121
Montassar Ben Saad, A. Jedidi, S. Niar, M. Abid
The ever-increasing transistor integration density has allowed to design complex and powerful system-on-chips (SoC). As a consequence, the power density also increased significantly in the SoC, as well as, the accompanying heat. These two results have a negative impact on the performance of the SoC. Thermal dissipation and power-density are important factors that may degrade significantly the reliability and the lifetime of the SoC. These aspects will limit the next generation embedded system performances. Traditionally, thermal problems are solved by employing on advanced packaging and cooling solutions. But the modern high-performance SoC is already pushing the limits of what the cooling solutions can offer. By opposition to the existing approaches, in this paper, thermal dissipation is controlled at the source code level. The different compilation optimizations are explored to find the best performance/thermal dissipation tradeoffs.
{"title":"Compilation optimization exploration for thermal dissipation reduction in embedded systems","authors":"Montassar Ben Saad, A. Jedidi, S. Niar, M. Abid","doi":"10.1109/IDT.2013.6727121","DOIUrl":"https://doi.org/10.1109/IDT.2013.6727121","url":null,"abstract":"The ever-increasing transistor integration density has allowed to design complex and powerful system-on-chips (SoC). As a consequence, the power density also increased significantly in the SoC, as well as, the accompanying heat. These two results have a negative impact on the performance of the SoC. Thermal dissipation and power-density are important factors that may degrade significantly the reliability and the lifetime of the SoC. These aspects will limit the next generation embedded system performances. Traditionally, thermal problems are solved by employing on advanced packaging and cooling solutions. But the modern high-performance SoC is already pushing the limits of what the cooling solutions can offer. By opposition to the existing approaches, in this paper, thermal dissipation is controlled at the source code level. The different compilation optimizations are explored to find the best performance/thermal dissipation tradeoffs.","PeriodicalId":446826,"journal":{"name":"2013 8th IEEE Design and Test Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114714525","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/IDT.2013.6727101
I. Abdelghany, W. Saab, Tarek Sakakini, Abdul-Amir Yassine, A. Chehab, A. Kayssi, I. Elhajj
Approximate computing is an attractive approach to energy saving area as many error-tolerant applications can make use of it for preserving energy on battery-powered mobile devices. This paper explores three designs of truncated 8-bit combinational multipliers that provide an approximate result while reducing energy consumption. Truncation methods are presented and analyzed in terms of energy reduction and error distribution. The three designs offer different balances and tradeoffs between accuracy and energy savings, with one of the designs reaching 86% in energy savings at the expense of reduced yet acceptable image quality in an image processing test. All designs resulted in an acceptable PSNR and an excellent performance when tested with SUSAN applications, while performance varied when tested with JPEG applications.
{"title":"Energy-efficient truncated multipliers with scaling","authors":"I. Abdelghany, W. Saab, Tarek Sakakini, Abdul-Amir Yassine, A. Chehab, A. Kayssi, I. Elhajj","doi":"10.1109/IDT.2013.6727101","DOIUrl":"https://doi.org/10.1109/IDT.2013.6727101","url":null,"abstract":"Approximate computing is an attractive approach to energy saving area as many error-tolerant applications can make use of it for preserving energy on battery-powered mobile devices. This paper explores three designs of truncated 8-bit combinational multipliers that provide an approximate result while reducing energy consumption. Truncation methods are presented and analyzed in terms of energy reduction and error distribution. The three designs offer different balances and tradeoffs between accuracy and energy savings, with one of the designs reaching 86% in energy savings at the expense of reduced yet acceptable image quality in an image processing test. All designs resulted in an acceptable PSNR and an excellent performance when tested with SUSAN applications, while performance varied when tested with JPEG applications.","PeriodicalId":446826,"journal":{"name":"2013 8th IEEE Design and Test Symposium","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129262567","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/IDT.2013.6727123
Jaber Hassan J. Al Yamani, F. Boussaïd, A. Bermak, D. Martinez
Commercial gas recognition systems use advanced computationally intensive signal processing/pattern recognition algorithms to identify gases and discriminate between them. This severely impacts on the size and cost of such systems but also limits their large-scale deployment. Biologically-inspired gas recognition schemes have the potential to greatly simplify the task of gas recognition, enabling the advent of low cost and low power miniature gas systems. In this paper, we present an experimental evaluation of bio-inspired latency coding for gas recognition. The performance of this bio-inspired approach was evaluated against four commonly used pattern recognition algorithms, namely K Nearest Neighbors (KNN), neural networks (Multi-Layer Perceptron (MLP), Radial Basis Function (RBF)) and density models (Gaussian Mixture Models (GMM). Reported experimental results suggest that latency coding could perform as well if not better than more computationally intensive pattern recognition techniques.
{"title":"Experimental evaluation of latency coding for gas recognition","authors":"Jaber Hassan J. Al Yamani, F. Boussaïd, A. Bermak, D. Martinez","doi":"10.1109/IDT.2013.6727123","DOIUrl":"https://doi.org/10.1109/IDT.2013.6727123","url":null,"abstract":"Commercial gas recognition systems use advanced computationally intensive signal processing/pattern recognition algorithms to identify gases and discriminate between them. This severely impacts on the size and cost of such systems but also limits their large-scale deployment. Biologically-inspired gas recognition schemes have the potential to greatly simplify the task of gas recognition, enabling the advent of low cost and low power miniature gas systems. In this paper, we present an experimental evaluation of bio-inspired latency coding for gas recognition. The performance of this bio-inspired approach was evaluated against four commonly used pattern recognition algorithms, namely K Nearest Neighbors (KNN), neural networks (Multi-Layer Perceptron (MLP), Radial Basis Function (RBF)) and density models (Gaussian Mixture Models (GMM). Reported experimental results suggest that latency coding could perform as well if not better than more computationally intensive pattern recognition techniques.","PeriodicalId":446826,"journal":{"name":"2013 8th IEEE Design and Test Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122407165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/IDT.2013.6727078
H. Mondal, Sujay Deb
Both industry and academia has accepted Networks-on-Chip (NoCs) as the communication backbone for multi-core Systems-on-Chip (SoCs). But the traditional approach of implementing a NoC with planar metal interconnects has high latency and significant power consumption overhead. This is due to multi-hop links used in data exchange, specifically when the number of cores is significantly high. To address these problems multi-hop wire interconnects in a NoC can be replaced with high-bandwidth single-hop long-range wireless links. This opens up new opportunities for detailed investigations into the energy efficient design of wireless NoCs using suitable on-chip wireless transceivers. Wireless transceivers with power gating can significantly improve the energy efficiency of the interconnection network. In this paper we have implemented and evaluated sleep transistor based power-gated transceiver for low power on-chip wireless interconnects. This approach improved power saving for wireless communication up to 70% compared to existing wireless NoC. The transceiver consumes 36.8771 mA current while on and less than 9 nA while in sleep mode from 1 V power supply. The delay associated with this wireless transceiver is less than 10 ps.
{"title":"Energy efficient on-chip wireless interconnects with sleepy transceivers","authors":"H. Mondal, Sujay Deb","doi":"10.1109/IDT.2013.6727078","DOIUrl":"https://doi.org/10.1109/IDT.2013.6727078","url":null,"abstract":"Both industry and academia has accepted Networks-on-Chip (NoCs) as the communication backbone for multi-core Systems-on-Chip (SoCs). But the traditional approach of implementing a NoC with planar metal interconnects has high latency and significant power consumption overhead. This is due to multi-hop links used in data exchange, specifically when the number of cores is significantly high. To address these problems multi-hop wire interconnects in a NoC can be replaced with high-bandwidth single-hop long-range wireless links. This opens up new opportunities for detailed investigations into the energy efficient design of wireless NoCs using suitable on-chip wireless transceivers. Wireless transceivers with power gating can significantly improve the energy efficiency of the interconnection network. In this paper we have implemented and evaluated sleep transistor based power-gated transceiver for low power on-chip wireless interconnects. This approach improved power saving for wireless communication up to 70% compared to existing wireless NoC. The transceiver consumes 36.8771 mA current while on and less than 9 nA while in sleep mode from 1 V power supply. The delay associated with this wireless transceiver is less than 10 ps.","PeriodicalId":446826,"journal":{"name":"2013 8th IEEE Design and Test Symposium","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122925591","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/IDT.2013.6727132
M. Taouil, M. Lefter, S. Hamdioui
3D-Stacked IC (3D-SIC) based on Through-Silicon-Vias (TSV) is an emerging technology that provides many benefits such as low power, high bandwidth 3D memories and heterogeneous integration. One of the attractive applications making used of such benefits is the stacking of memory dies on logic. System integrators for such application have to provide appropriate test strategy. However, they have to deal with block box IPs as IP providers usually refuse to share the IP content. Moreover, they dislike including JTAG in memory dies. Therefore, developing a low cost and high quality test approaches, while taking these constraints into consideration, is of great importance. This paper presents a framework of interconnect test approaches for memories stacked on logic, and look further than the only proposed JTAG solutions. The benefits and drawbacks of each possible solution is extensively discusses for stacked memories both with and without MBISTs, placed on the memory dies or on a separate logic die.
{"title":"Exploring test opportunities for memory and interconnects in 3D ICs","authors":"M. Taouil, M. Lefter, S. Hamdioui","doi":"10.1109/IDT.2013.6727132","DOIUrl":"https://doi.org/10.1109/IDT.2013.6727132","url":null,"abstract":"3D-Stacked IC (3D-SIC) based on Through-Silicon-Vias (TSV) is an emerging technology that provides many benefits such as low power, high bandwidth 3D memories and heterogeneous integration. One of the attractive applications making used of such benefits is the stacking of memory dies on logic. System integrators for such application have to provide appropriate test strategy. However, they have to deal with block box IPs as IP providers usually refuse to share the IP content. Moreover, they dislike including JTAG in memory dies. Therefore, developing a low cost and high quality test approaches, while taking these constraints into consideration, is of great importance. This paper presents a framework of interconnect test approaches for memories stacked on logic, and look further than the only proposed JTAG solutions. The benefits and drawbacks of each possible solution is extensively discusses for stacked memories both with and without MBISTs, placed on the memory dies or on a separate logic die.","PeriodicalId":446826,"journal":{"name":"2013 8th IEEE Design and Test Symposium","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128697952","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/IDT.2013.6727134
O. Hammami, Xinyu Li
ITRS Semiconductor roadmap projects that hundreds of processors will be needed for future generation system on chip (SOC) designs. Network-on-Chip (NoC) is an emerging paradigm for communications within large VLSI systems implemented on a single silicon chip. Among the NoC conception problems, there exists the Network-on-Chip Topology synthesis Problem, which consists in generating the topology of the NoC to guarantee the system performance, silicone area and power consumption design objective. The typical and well adapted design methodologies in the literature all take a core graph as the input of NoC synthesis, which represents the communication between components. But until now there are no common NoC synthesis benchmarks to test the different methods over the same instances. In this paper, a core graph generator and a suit of generated core graphs are proposed to give researcher a common standard NoC synthesis benchmarks. This core graph generator and benchmarks can help and accelerate the NoC synthesis research of large scale SoC design.
{"title":"NOCBENCH: NOC synthesis benchmarks","authors":"O. Hammami, Xinyu Li","doi":"10.1109/IDT.2013.6727134","DOIUrl":"https://doi.org/10.1109/IDT.2013.6727134","url":null,"abstract":"ITRS Semiconductor roadmap projects that hundreds of processors will be needed for future generation system on chip (SOC) designs. Network-on-Chip (NoC) is an emerging paradigm for communications within large VLSI systems implemented on a single silicon chip. Among the NoC conception problems, there exists the Network-on-Chip Topology synthesis Problem, which consists in generating the topology of the NoC to guarantee the system performance, silicone area and power consumption design objective. The typical and well adapted design methodologies in the literature all take a core graph as the input of NoC synthesis, which represents the communication between components. But until now there are no common NoC synthesis benchmarks to test the different methods over the same instances. In this paper, a core graph generator and a suit of generated core graphs are proposed to give researcher a common standard NoC synthesis benchmarks. This core graph generator and benchmarks can help and accelerate the NoC synthesis research of large scale SoC design.","PeriodicalId":446826,"journal":{"name":"2013 8th IEEE Design and Test Symposium","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124374640","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/IDT.2013.6727116
A. Siblini, Elias Baaklini, Hassan Sbeity, A. Fadlallah, S. Niar
Multiprocessor-system-on-a-chip (MPSoC) is the dominating architecture in embedded systems. Applications need to be multi-threaded to benefit from the concurrency provided by the MPSoC. Many parallel versions of the new emerging H.264/AVC [1] already exist. However, providing a full parallel H.264 version is blocked by the fact that all parts of the decoder depend on the first sequential stage of the decoding process which is the entropy decoder (mainly CAVLC). The entropy decoder consumes about 30% [8] of the total time of the decoder. In this work, we propose an optimized FPGA design achieving the demands of multi-threaded H.264 decoder versions which can be integrated in an MPSoC. We focus in our work on time optimization and on cycle number decrease when decoding an encoded 4×4 block of pixels. We also aim to achieve a design that operates at high frequencies. The work leads to the ability to decode at least 62 frames per second for HD resolution 1280×720. Decoding takes 22 clock cycles for one block of 4×4 pixels at most. The design has an upper frequency limit of 247MHz. High resolutions frames such as 1920×1088 FHD (full high definition) video maintain a minimum frequency of 30 fps.
{"title":"Efficient FPGA implementation of H.264 CAVLC entropy decoder","authors":"A. Siblini, Elias Baaklini, Hassan Sbeity, A. Fadlallah, S. Niar","doi":"10.1109/IDT.2013.6727116","DOIUrl":"https://doi.org/10.1109/IDT.2013.6727116","url":null,"abstract":"Multiprocessor-system-on-a-chip (MPSoC) is the dominating architecture in embedded systems. Applications need to be multi-threaded to benefit from the concurrency provided by the MPSoC. Many parallel versions of the new emerging H.264/AVC [1] already exist. However, providing a full parallel H.264 version is blocked by the fact that all parts of the decoder depend on the first sequential stage of the decoding process which is the entropy decoder (mainly CAVLC). The entropy decoder consumes about 30% [8] of the total time of the decoder. In this work, we propose an optimized FPGA design achieving the demands of multi-threaded H.264 decoder versions which can be integrated in an MPSoC. We focus in our work on time optimization and on cycle number decrease when decoding an encoded 4×4 block of pixels. We also aim to achieve a design that operates at high frequencies. The work leads to the ability to decode at least 62 frames per second for HD resolution 1280×720. Decoding takes 22 clock cycles for one block of 4×4 pixels at most. The design has an upper frequency limit of 247MHz. High resolutions frames such as 1920×1088 FHD (full high definition) video maintain a minimum frequency of 30 fps.","PeriodicalId":446826,"journal":{"name":"2013 8th IEEE Design and Test Symposium","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131319904","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/IDT.2013.6727105
B. Mohammad, Nadeem Eleyan, Greg Seok, Hong Kim
One of the least popular steps in custom memory design is the tedious task of generating the logical to physical Bit Mapping information. This Bit Mapping information is important for the silicon validation and test engineers to debug failures in the memory blocks on the tester. Historically generating the Bit Mapping document required the designer to manually figure out this mapping and either create a diagram by hand or write a custom script to describe the mapping. This manual process is error prone and hard to validate. For small geometry process technology and big size memory it is important to identify any failing location to facilitate silicon debug. This paper presents an automated flow for generating bit mapping information directly from the physical layout and logical simulations. The flow also generates a graphical interface to identify the location of each memory address. This can be used to identify any potential noise issue (bit flipping) due to interaction between the different memory locations.
{"title":"Automated flow for generating CMOS custom memory bit map between logical and physical implementation","authors":"B. Mohammad, Nadeem Eleyan, Greg Seok, Hong Kim","doi":"10.1109/IDT.2013.6727105","DOIUrl":"https://doi.org/10.1109/IDT.2013.6727105","url":null,"abstract":"One of the least popular steps in custom memory design is the tedious task of generating the logical to physical Bit Mapping information. This Bit Mapping information is important for the silicon validation and test engineers to debug failures in the memory blocks on the tester. Historically generating the Bit Mapping document required the designer to manually figure out this mapping and either create a diagram by hand or write a custom script to describe the mapping. This manual process is error prone and hard to validate. For small geometry process technology and big size memory it is important to identify any failing location to facilitate silicon debug. This paper presents an automated flow for generating bit mapping information directly from the physical layout and logical simulations. The flow also generates a graphical interface to identify the location of each memory address. This can be used to identify any potential noise issue (bit flipping) due to interaction between the different memory locations.","PeriodicalId":446826,"journal":{"name":"2013 8th IEEE Design and Test Symposium","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123330809","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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