An artificial intelligence (AI)-enabled ECG chip (AI-ECG chip) for classifying continuous ECG signals is described. The AI-ECG chip employs a two-stage strategy. It integrates a QRS complex wave detection architecture for signal preprocessing and a two-layer deep-learning network for post-processing. TSMC $text{180}~nm$ complementary metal-oxide semiconductor fabrication process was used to produce the AI-ECG chip, which can be operated at a maximum frequency of $text{26.3}~MHz$ while consuming $text{3.11}~mW$ . Despite its compact $1.41 - m{m^2}$ size. The AI-ECG chip can achieve arrhythmia detection accuracy of 90.56%. A salient feature of this chip is the ability to identify up to four different arrhythmias, thus offering a more extensive diagnostic range than most comparable chips. In summary, the AI-ECG chip achieves great balance among chip size, power efficiency, and detection capabilities. It is an attractive solution for portable ECG monitoring systems.
{"title":"Artificial Intelligence Chip Design for High-Speed Cardiac Arrhythmia Classification","authors":"Yuan-Ho Chen, Ching-Tien Wang, Shinn-Yn Lin, Chao-Sung Lai, Bing Sheu","doi":"10.1109/mnano.2023.3316875","DOIUrl":"https://doi.org/10.1109/mnano.2023.3316875","url":null,"abstract":"An artificial intelligence (AI)-enabled ECG chip (AI-ECG chip) for classifying continuous ECG signals is described. The AI-ECG chip employs a two-stage strategy. It integrates a QRS complex wave detection architecture for signal preprocessing and a two-layer deep-learning network for post-processing. TSMC <inline-formula xmlns:mml=\"http://www.w3.org/1998/Math/MathML\" xmlns:xlink=\"http://www.w3.org/1999/xlink\"><tex-math notation=\"LaTeX\">$text{180}~nm$</tex-math></inline-formula> complementary metal-oxide semiconductor fabrication process was used to produce the AI-ECG chip, which can be operated at a maximum frequency of <inline-formula xmlns:mml=\"http://www.w3.org/1998/Math/MathML\" xmlns:xlink=\"http://www.w3.org/1999/xlink\"><tex-math notation=\"LaTeX\">$text{26.3}~MHz$</tex-math></inline-formula> while consuming <inline-formula xmlns:mml=\"http://www.w3.org/1998/Math/MathML\" xmlns:xlink=\"http://www.w3.org/1999/xlink\"><tex-math notation=\"LaTeX\">$text{3.11}~mW$</tex-math></inline-formula> . Despite its compact <inline-formula xmlns:mml=\"http://www.w3.org/1998/Math/MathML\" xmlns:xlink=\"http://www.w3.org/1999/xlink\"><tex-math notation=\"LaTeX\">$1.41 - m{m^2}$</tex-math></inline-formula> size. The AI-ECG chip can achieve arrhythmia detection accuracy of 90.56%. A salient feature of this chip is the ability to identify up to four different arrhythmias, thus offering a more extensive diagnostic range than most comparable chips. In summary, the AI-ECG chip achieves great balance among chip size, power efficiency, and detection capabilities. It is an attractive solution for portable ECG monitoring systems.","PeriodicalId":44724,"journal":{"name":"IEEE Nanotechnology Magazine","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"136257369","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-01-01DOI: 10.1109/mnano.2023.3316871
Yao-Tung Tsou, Guo Cheng Jian
With edge computing and public networks on the rise, safeguarding personal data is paramount. This article presents a comprehensive survey of Privacy-Enhancing Technologies (PETs) in emerging edge envisioned networks, focusing on privacy-preserving image processing and data analysis. The survey highlights the prevailing trend of using differential privacy techniques for image de-identification, offering insights into the state-of-the-art literature in this area. Additionally, it introduces DeCloakFace, an advanced technique for privacy-preserving image recognition on edge devices, showcasing its applicability and advantages. By identifying research gaps and exploring future directions, the article aims to advance PETs in addressing privacy concerns within emerging edge envisioned public networks. Differential privacy for image de-identification receives special attention, emphasizing its significance in preserving privacy while enabling effective data analysis.
{"title":"DeCloakFace","authors":"Yao-Tung Tsou, Guo Cheng Jian","doi":"10.1109/mnano.2023.3316871","DOIUrl":"https://doi.org/10.1109/mnano.2023.3316871","url":null,"abstract":"With edge computing and public networks on the rise, safeguarding personal data is paramount. This article presents a comprehensive survey of Privacy-Enhancing Technologies (PETs) in emerging edge envisioned networks, focusing on privacy-preserving image processing and data analysis. The survey highlights the prevailing trend of using differential privacy techniques for image de-identification, offering insights into the state-of-the-art literature in this area. Additionally, it introduces DeCloakFace, an advanced technique for privacy-preserving image recognition on edge devices, showcasing its applicability and advantages. By identifying research gaps and exploring future directions, the article aims to advance PETs in addressing privacy concerns within emerging edge envisioned public networks. Differential privacy for image de-identification receives special attention, emphasizing its significance in preserving privacy while enabling effective data analysis.","PeriodicalId":44724,"journal":{"name":"IEEE Nanotechnology Magazine","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135010071","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-01DOI: 10.1109/MNANO.2022.3208723
Evangelos Tsipas, Theodoros Panagiotis Chatzinikolaou, Karolos-Alexandros Tsakalos, K. Rallis, Rafailia-Eleni Karamani, Iosif-Angelos Fyrigos, Stavros Kitsios, P. Bousoulas, Dimitrios Tsoukalas, G. Sirakoulis
Computing demands are growing rapidly as bigdata and artificial intelligence applications become increasingly tasking. Bio-inspired and quantum-based techniques are proving to be quite promising for the development of novel circuits and systems. These systems can contribute to the resolution of a wider variety of problems while also providing improvements to existing techniques. As the von Neumann architecture’s expected performance, which has been dominant for the past several decades, is now hindered by physical limitations, novel computing architectures, assisted by novel materials and circuit devices, are starting to emerge and provide promising results. The topic of this work is to examine the memory and computing capabilities of emergent memristor-based nanocircuits and demonstrate their advantages compared to their classical counterparts.
{"title":"Unconventional Computing With Memristive Nanocircuits","authors":"Evangelos Tsipas, Theodoros Panagiotis Chatzinikolaou, Karolos-Alexandros Tsakalos, K. Rallis, Rafailia-Eleni Karamani, Iosif-Angelos Fyrigos, Stavros Kitsios, P. Bousoulas, Dimitrios Tsoukalas, G. Sirakoulis","doi":"10.1109/MNANO.2022.3208723","DOIUrl":"https://doi.org/10.1109/MNANO.2022.3208723","url":null,"abstract":"Computing demands are growing rapidly as bigdata and artificial intelligence applications become increasingly tasking. Bio-inspired and quantum-based techniques are proving to be quite promising for the development of novel circuits and systems. These systems can contribute to the resolution of a wider variety of problems while also providing improvements to existing techniques. As the von Neumann architecture’s expected performance, which has been dominant for the past several decades, is now hindered by physical limitations, novel computing architectures, assisted by novel materials and circuit devices, are starting to emerge and provide promising results. The topic of this work is to examine the memory and computing capabilities of emergent memristor-based nanocircuits and demonstrate their advantages compared to their classical counterparts.","PeriodicalId":44724,"journal":{"name":"IEEE Nanotechnology Magazine","volume":"16 1","pages":"22-33"},"PeriodicalIF":1.6,"publicationDate":"2022-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43367937","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-01DOI: 10.1109/MNANO.2022.3208757
Farzad Niknia, Ziheng Wang, Shanshan Liu, A. Louri, Fabrizio Lombardi
Artificial neural networks (ANNs) are usually implemented in accelerators to achieve efficient processing of inference; the hardware implementation of an ANN accelerator requires careful consideration on overhead metrics (such as delay, energy and area) and performance (usually measured by the accuracy). This paper considers the ASIC-based accelerator from arithmetic design considerations. The feasibility of using different schemes (parallel, serial and hybrid arrangements) and different types of arithmetic computing (floating-point, fixed-point and stochastic computing) when implementing multilayer perceptrons (MLPs) are considered. The evaluation results of MLPs for two popular datasets show that the floating-point/fixed-point-based parallel (hybrid) design achieves the smallest latency (area) and the SC-based design offers the lowest energy dissipation.
{"title":"Nanoscale Accelerators for Artificial Neural Networks","authors":"Farzad Niknia, Ziheng Wang, Shanshan Liu, A. Louri, Fabrizio Lombardi","doi":"10.1109/MNANO.2022.3208757","DOIUrl":"https://doi.org/10.1109/MNANO.2022.3208757","url":null,"abstract":"Artificial neural networks (ANNs) are usually implemented in accelerators to achieve efficient processing of inference; the hardware implementation of an ANN accelerator requires careful consideration on overhead metrics (such as delay, energy and area) and performance (usually measured by the accuracy). This paper considers the ASIC-based accelerator from arithmetic design considerations. The feasibility of using different schemes (parallel, serial and hybrid arrangements) and different types of arithmetic computing (floating-point, fixed-point and stochastic computing) when implementing multilayer perceptrons (MLPs) are considered. The evaluation results of MLPs for two popular datasets show that the floating-point/fixed-point-based parallel (hybrid) design achieves the smallest latency (area) and the SC-based design offers the lowest energy dissipation.","PeriodicalId":44724,"journal":{"name":"IEEE Nanotechnology Magazine","volume":"16 1","pages":"14-21"},"PeriodicalIF":1.6,"publicationDate":"2022-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43199179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-01DOI: 10.1109/MNANO.2022.3208722
N. C. Laurenciu, C. Timmermans, S. Cotofana
The realization of energy efficient, low area, and fast processing neuron and synapse circuits is of prime importance for unleashing neuromorphic computing full potential. In this paper, we introduce a graphene-based synapse, which can emulate Spike Timing Dependent Plasticity (STDP) and Short/Long Term Plasticity (STP/LTP) with variable signal amplitude and temporal dynamics. The synapse operation is validated by means of SPICE simulations, and its synaptic modulation ability is showcased through reinforcement learning within a Spiking Neural Network for robotic navigation with obstacles avoidance. Besides its functional versatility, the proposed graphene-based synapse can potentially occupy low active area ($ approx 170{kern 1pt} {mathrm{n}}{{mathrm{m}}^2}$≈170nm2) and operate at low voltage ($200{kern 1pt} {mathrm{mV}}$200 mV ). When compared with a biological brain synapse, its energy consumption per spike for a weight update operation ($0.5{kern 1pt} {mathrm{fJ}}$0.5 fJ ) is $20 times $20× lower, while the processing speed is increased by six orders of magnitude. Such properties are essential desiderata for the realization of large scale neuromorphic systems, making the proposed graphene-based synapse an outstanding candidate for this purpose.
{"title":"Low Energy, Non-Cortical, Graphene Nanoribbon-Based STDP Plastic Synapses","authors":"N. C. Laurenciu, C. Timmermans, S. Cotofana","doi":"10.1109/MNANO.2022.3208722","DOIUrl":"https://doi.org/10.1109/MNANO.2022.3208722","url":null,"abstract":"The realization of energy efficient, low area, and fast processing neuron and synapse circuits is of prime importance for unleashing neuromorphic computing full potential. In this paper, we introduce a graphene-based synapse, which can emulate Spike Timing Dependent Plasticity (STDP) and Short/Long Term Plasticity (STP/LTP) with variable signal amplitude and temporal dynamics. The synapse operation is validated by means of SPICE simulations, and its synaptic modulation ability is showcased through reinforcement learning within a Spiking Neural Network for robotic navigation with obstacles avoidance. Besides its functional versatility, the proposed graphene-based synapse can potentially occupy low active area ($ approx 170{kern 1pt} {mathrm{n}}{{mathrm{m}}^2}$≈170nm2) and operate at low voltage ($200{kern 1pt} {mathrm{mV}}$200 mV ). When compared with a biological brain synapse, its energy consumption per spike for a weight update operation ($0.5{kern 1pt} {mathrm{fJ}}$0.5 fJ ) is $20 times $20× lower, while the processing speed is increased by six orders of magnitude. Such properties are essential desiderata for the realization of large scale neuromorphic systems, making the proposed graphene-based synapse an outstanding candidate for this purpose.","PeriodicalId":44724,"journal":{"name":"IEEE Nanotechnology Magazine","volume":"16 1","pages":"4-13"},"PeriodicalIF":1.6,"publicationDate":"2022-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"45702649","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-01DOI: 10.1109/MNANO.2022.3208789
Evangelos Tsipas, Theodoros Panagiotis Chatzinikolaou, Karolos-Alexandros Tsakalos, K. Rallis, Rafailia-Eleni Karamani, Iosif-Angelos Fyrigos, Stavros Kitsios, P. Bousoulas, D. Tsoukalas, G. Sirakoulis
One of the most enticing candidates for next-generation computing systems is the memristor. Memristor-based novel architectures have demonstrated considerable promise in replacing or augmenting traditional computing platforms based on the Von Neumann architecture, which faces many issues in the big-data era, as well as in newly developed neuromorphic tasks. Although the current classical computing architecture is unlikely to be abandoned in the foreseeable future, the growing trend of neuromorphic, quantum, and bio-inspired computing schemes calls for more specialized beyond Von Neumann platforms. Memristors showcase multiple advantages in terms of small area footprint, energy efficiency, high endurance, bio-compatibility, and their inherent synaptic and neuromorphic behavior. The topic of this work is to present the memristive devices that meet the requirements for the implementation of the novel beyond Von Neumann applications and examine their switching mechanism and material selection, as well as to conduct a performance comparison between the fabricated devices paving the way for future computing applications.
{"title":"Unconventional Memristive Nanodevices","authors":"Evangelos Tsipas, Theodoros Panagiotis Chatzinikolaou, Karolos-Alexandros Tsakalos, K. Rallis, Rafailia-Eleni Karamani, Iosif-Angelos Fyrigos, Stavros Kitsios, P. Bousoulas, D. Tsoukalas, G. Sirakoulis","doi":"10.1109/MNANO.2022.3208789","DOIUrl":"https://doi.org/10.1109/MNANO.2022.3208789","url":null,"abstract":"One of the most enticing candidates for next-generation computing systems is the memristor. Memristor-based novel architectures have demonstrated considerable promise in replacing or augmenting traditional computing platforms based on the Von Neumann architecture, which faces many issues in the big-data era, as well as in newly developed neuromorphic tasks. Although the current classical computing architecture is unlikely to be abandoned in the foreseeable future, the growing trend of neuromorphic, quantum, and bio-inspired computing schemes calls for more specialized beyond Von Neumann platforms. Memristors showcase multiple advantages in terms of small area footprint, energy efficiency, high endurance, bio-compatibility, and their inherent synaptic and neuromorphic behavior. The topic of this work is to present the memristive devices that meet the requirements for the implementation of the novel beyond Von Neumann applications and examine their switching mechanism and material selection, as well as to conduct a performance comparison between the fabricated devices paving the way for future computing applications.","PeriodicalId":44724,"journal":{"name":"IEEE Nanotechnology Magazine","volume":"16 1","pages":"34-45"},"PeriodicalIF":1.6,"publicationDate":"2022-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"42063957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：