Pub Date : 2022-04-01DOI: 10.1109/mnano.2022.3141443
J. Eshraghian, Xinxin Wang, W. Lu
Memristive arrays are a natural fit to implement spiking neural network (SNN) acceleration. Representing information as digital spiking events can improve noise margins and tolerance to device variability compared to analog bitline current summation approaches to multiply–accumulate (MAC) operations. Restricting neuron activations to single-bit spikes also alleviates the significant analog-to-digital converter (ADC) overhead that mixed-signal approaches have struggled to overcome. Binarized, and more generally, limited-precision, NNs are considered to trade off computational overhead with model accuracy, but unlike conventional deep learning models, SNNs do not encode information in the precision-constrained amplitude of the spike. Rather, information may be encoded in the spike time as a temporal code, in the spike frequency as a rate code, and in any number of stand-alone and combined codes. Even if activations and weights are bounded in precision, time can be thought of as continuous and provides an alternative dimension to encode information in. This article explores the challenges that face the memristor-based acceleration of NNs and how binarized SNNs (BSNNs) may offer a good fit for these emerging hardware systems.
{"title":"Memristor-Based Binarized Spiking Neural Networks: Challenges and applications","authors":"J. Eshraghian, Xinxin Wang, W. Lu","doi":"10.1109/mnano.2022.3141443","DOIUrl":"https://doi.org/10.1109/mnano.2022.3141443","url":null,"abstract":"Memristive arrays are a natural fit to implement spiking neural network (SNN) acceleration. Representing information as digital spiking events can improve noise margins and tolerance to device variability compared to analog bitline current summation approaches to multiply–accumulate (MAC) operations. Restricting neuron activations to single-bit spikes also alleviates the significant analog-to-digital converter (ADC) overhead that mixed-signal approaches have struggled to overcome. Binarized, and more generally, limited-precision, NNs are considered to trade off computational overhead with model accuracy, but unlike conventional deep learning models, SNNs do not encode information in the precision-constrained amplitude of the spike. Rather, information may be encoded in the spike time as a temporal code, in the spike frequency as a rate code, and in any number of stand-alone and combined codes. Even if activations and weights are bounded in precision, time can be thought of as continuous and provides an alternative dimension to encode information in. This article explores the challenges that face the memristor-based acceleration of NNs and how binarized SNNs (BSNNs) may offer a good fit for these emerging hardware systems.","PeriodicalId":44724,"journal":{"name":"IEEE Nanotechnology Magazine","volume":"16 1","pages":"14-23"},"PeriodicalIF":1.6,"publicationDate":"2022-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43832864","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
SpinQ Triangulum is the second generation of the desktop quantum computers designed and manufactured by SpinQ Technology. SpinQ’s desktop quantum computer series, based on a room-temperature nuclear magnetic resonance (NMR) spectrometer, provides lightweight, cost-effective, and maintenance-free quantum computing platforms that aim to provide real-device experience for quantum computing education for kindergarten through 12th grade (K–12) and the college level. These platforms also feature quantum control design capabilities for studying quantum control and quantum noise.
{"title":"SpinQ Triangulum: A commercial three-qubit desktop quantum computer","authors":"Guanru Feng, Shin-Yao Hou, Hongyang Zhou, Wei Shi, Shengqiang Yu, Zikai Sheng, Xin Rao, Kaihong Ma, Chenxing Chen, Bing Ren, Guozing Miao, Jingen Xiang, B. Zeng","doi":"10.1109/mnano.2022.3175392","DOIUrl":"https://doi.org/10.1109/mnano.2022.3175392","url":null,"abstract":"SpinQ Triangulum is the second generation of the desktop quantum computers designed and manufactured by SpinQ Technology. SpinQ’s desktop quantum computer series, based on a room-temperature nuclear magnetic resonance (NMR) spectrometer, provides lightweight, cost-effective, and maintenance-free quantum computing platforms that aim to provide real-device experience for quantum computing education for kindergarten through 12th grade (K–12) and the college level. These platforms also feature quantum control design capabilities for studying quantum control and quantum noise.","PeriodicalId":44724,"journal":{"name":"IEEE Nanotechnology Magazine","volume":"16 1","pages":"20-29"},"PeriodicalIF":1.6,"publicationDate":"2022-02-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"46433642","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-02-01DOI: 10.1109/MNANO.2021.3126129
D. Gracias
In recent decades, the extreme miniaturization in very large-scale microchip fabrication and the development of ultrasensitive instrumentation such as scanning probe microscopy and bottom-up macromolecular chemistry, have allowed integrated nanotechnology to transform human engineering. Now, an emergent thrust seeks to move this field into new areas, such as biological interfaces, wearables, and small-scale robotics. Many of these functions are already embodied in our bodies, plants, and organisms, and they require unique attributes, including three dimensionality, heterogeneous materials integration, flexibility, motion, and shape change. Integrated nanotechnology 2.0 focuses on the design, fabrication, and assembly of nanostructured devices that could significantly impact human life through artificial intelligence, smart medicine, and robotics. In this article, a few examples, principles, and perspectives are outlined.
{"title":"Integrated Nanotechnology 2.0: 3D, Smart, Flexible, and Dynamic [Highlights]","authors":"D. Gracias","doi":"10.1109/MNANO.2021.3126129","DOIUrl":"https://doi.org/10.1109/MNANO.2021.3126129","url":null,"abstract":"In recent decades, the extreme miniaturization in very large-scale microchip fabrication and the development of ultrasensitive instrumentation such as scanning probe microscopy and bottom-up macromolecular chemistry, have allowed integrated nanotechnology to transform human engineering. Now, an emergent thrust seeks to move this field into new areas, such as biological interfaces, wearables, and small-scale robotics. Many of these functions are already embodied in our bodies, plants, and organisms, and they require unique attributes, including three dimensionality, heterogeneous materials integration, flexibility, motion, and shape change. Integrated nanotechnology 2.0 focuses on the design, fabrication, and assembly of nanostructured devices that could significantly impact human life through artificial intelligence, smart medicine, and robotics. In this article, a few examples, principles, and perspectives are outlined.","PeriodicalId":44724,"journal":{"name":"IEEE Nanotechnology Magazine","volume":"16 1","pages":"11-15"},"PeriodicalIF":1.6,"publicationDate":"2022-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"45559081","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-02-01DOI: 10.1109/mnano.2021.3126094
N. Onizawa, T. Hanyu
Recently, CMOS invertible logic has been presented and is one of the new computing paradigms based on a probabilistic device model. It is designed based on stochastic computing that provides bidirectional operations between inputs and outputs and has been applied for several critical issues, such as integer factorization and machine learning (ML). This article presents an overview of CMOS invertible logic from principle to application. First, the principle is explained with a simple design example, and a design flow is introduced, as is an automatic design tool. Second, the hardware of CMOS invertible logic is designed using stochastic computing and then evaluated in two applications implemented on a field-programmable gate array (FPGA) or application-specific integrated circuits (ASICs). Finally, this article ends with future challenges.
{"title":"CMOS Invertible Logic: Bidirectional operation based on the probabilistic device model and stochastic computing","authors":"N. Onizawa, T. Hanyu","doi":"10.1109/mnano.2021.3126094","DOIUrl":"https://doi.org/10.1109/mnano.2021.3126094","url":null,"abstract":"Recently, CMOS invertible logic has been presented and is one of the new computing paradigms based on a probabilistic device model. It is designed based on stochastic computing that provides bidirectional operations between inputs and outputs and has been applied for several critical issues, such as integer factorization and machine learning (ML). This article presents an overview of CMOS invertible logic from principle to application. First, the principle is explained with a simple design example, and a design flow is introduced, as is an automatic design tool. Second, the hardware of CMOS invertible logic is designed using stochastic computing and then evaluated in two applications implemented on a field-programmable gate array (FPGA) or application-specific integrated circuits (ASICs). Finally, this article ends with future challenges.","PeriodicalId":44724,"journal":{"name":"IEEE Nanotechnology Magazine","volume":"16 1","pages":"33-46"},"PeriodicalIF":1.6,"publicationDate":"2022-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"42640048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-02-01DOI: 10.1109/mnano.2021.3126096
Qin Li, Zheyu Liu, Xinghua Yang, Fei Qiao
Always-on speech recognition terminals (ASRTs), which detect a user’s speech all the time and convert it into text for the speech interaction system, have broad prospects. However, the conventional implementations of ASRTs, which are always based on accurate computing design, suffer from redundant power consumption, high processing latency, and extensive memory access. Since the processing of the algorithms used for ASRTs has an error-tolerance property in its nature, this article adopts analog and digital approximate computing techniques to solve these challenges.
{"title":"Always-On Speech Recognition Terminals: Designs based on approximate computing methods","authors":"Qin Li, Zheyu Liu, Xinghua Yang, Fei Qiao","doi":"10.1109/mnano.2021.3126096","DOIUrl":"https://doi.org/10.1109/mnano.2021.3126096","url":null,"abstract":"Always-on speech recognition terminals (ASRTs), which detect a user’s speech all the time and convert it into text for the speech interaction system, have broad prospects. However, the conventional implementations of ASRTs, which are always based on accurate computing design, suffer from redundant power consumption, high processing latency, and extensive memory access. Since the processing of the algorithms used for ASRTs has an error-tolerance property in its nature, this article adopts analog and digital approximate computing techniques to solve these challenges.","PeriodicalId":44724,"journal":{"name":"IEEE Nanotechnology Magazine","volume":"16 1","pages":"57-74"},"PeriodicalIF":1.6,"publicationDate":"2022-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"48551918","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-02-01DOI: 10.1109/mnano.2021.3126092
Shanshan Liu, P. Reviriego, P. Junsangsri, Fabrizio Lombardi
The slowdown of CMOS technology scaling has placed architectures and algorithms on focus for future performance improvements in nanoscale computing systems. Two promising approaches at algorithmic level are approximate computing (AC) and probabilistic data structures (PDSs) that employ the tolerance of an application to small deviations in the results for reducing the complexity of the hardware implementation. AC focuses on applications that process numerical data and relies mostly on approximate (or inexact) low-level arithmetic operations. Instead, PDSs target categorical data and rely on shared data structures and other higher-level simplifications that introduce probabilistic deviations even when all operations are exact. Both AC and PDSs have been able to dramatically reduce the cost in some applications, but they are so far completely disconnected in the application domains, the abstraction levels, and the research communities. In this article, we introduce probabilistic approximate computing (PAC), a new paradigm to use application tolerance for small deviations to reduce the implementation complexity of data structures and hardware when implemented with nanoscale memory technologies. Its goal is to have data structures on which both AC and probabilistic techniques are used in a synergetic way to improve efficiency, while keeping deviations within acceptable margins.
{"title":"Probabilistic Approximate Computing at Nanoscales: From data structures to memories","authors":"Shanshan Liu, P. Reviriego, P. Junsangsri, Fabrizio Lombardi","doi":"10.1109/mnano.2021.3126092","DOIUrl":"https://doi.org/10.1109/mnano.2021.3126092","url":null,"abstract":"The slowdown of CMOS technology scaling has placed architectures and algorithms on focus for future performance improvements in nanoscale computing systems. Two promising approaches at algorithmic level are approximate computing (AC) and probabilistic data structures (PDSs) that employ the tolerance of an application to small deviations in the results for reducing the complexity of the hardware implementation. AC focuses on applications that process numerical data and relies mostly on approximate (or inexact) low-level arithmetic operations. Instead, PDSs target categorical data and rely on shared data structures and other higher-level simplifications that introduce probabilistic deviations even when all operations are exact. Both AC and PDSs have been able to dramatically reduce the cost in some applications, but they are so far completely disconnected in the application domains, the abstraction levels, and the research communities. In this article, we introduce probabilistic approximate computing (PAC), a new paradigm to use application tolerance for small deviations to reduce the implementation complexity of data structures and hardware when implemented with nanoscale memory technologies. Its goal is to have data structures on which both AC and probabilistic techniques are used in a synergetic way to improve efficiency, while keeping deviations within acceptable margins.","PeriodicalId":44724,"journal":{"name":"IEEE Nanotechnology Magazine","volume":"16 1","pages":"16-24"},"PeriodicalIF":1.6,"publicationDate":"2022-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"45226247","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-02-01DOI: 10.1109/mnano.2021.3126093
You Wang, Kaili Zhang, Bo Wu, Deming Zhang, Hao Cai, Weisheng Zhao
This article presents an overview of the recent developments in the magnetic random access memory (MRAM) for approximate computing. The key technique of approximate computing is to trade off limited accuracy for improvements in other metrics, such as speed, power, and area. With intrinsic current-induced threshold operation and random process variation, MRAM is regarded as a promising candidate for approximate computing. Beginning with the background of approximate computing, this article reviews prior design techniques at the circuit level and recent development trends. Then the physical mechanisms of randomness in MRAM are detailed. Several designs based on MRAM are comprehensively studied and compared in terms of performance. Finally, an outline of possible challenges and future research directions are given.
{"title":"Magnetic Random-Access Memory-Based Approximate Computting: An overview","authors":"You Wang, Kaili Zhang, Bo Wu, Deming Zhang, Hao Cai, Weisheng Zhao","doi":"10.1109/mnano.2021.3126093","DOIUrl":"https://doi.org/10.1109/mnano.2021.3126093","url":null,"abstract":"This article presents an overview of the recent developments in the magnetic random access memory (MRAM) for approximate computing. The key technique of approximate computing is to trade off limited accuracy for improvements in other metrics, such as speed, power, and area. With intrinsic current-induced threshold operation and random process variation, MRAM is regarded as a promising candidate for approximate computing. Beginning with the background of approximate computing, this article reviews prior design techniques at the circuit level and recent development trends. Then the physical mechanisms of randomness in MRAM are detailed. Several designs based on MRAM are comprehensively studied and compared in terms of performance. Finally, an outline of possible challenges and future research directions are given.","PeriodicalId":44724,"journal":{"name":"IEEE Nanotechnology Magazine","volume":"16 1","pages":"25-32"},"PeriodicalIF":1.6,"publicationDate":"2022-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"48075684","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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