Pub Date : 2000-03-13DOI: 10.1109/ICMTS.2000.844411
A. Gotz, I. Gràcia, C. Cané, M. Lozano, E. Lora-Tamayo
Thermal and mechanical characterisation has been carried out on simple test structures that allow the optimisation of the size, power consumption and mechanical robustness of thermally isolated membranes for semiconductor gas sensors fabricated on silicon micromachined substrates. Breakdown pressure, working temperature and heat distribution are the parameters that have been considered of interest for the development of the sensor structures.
{"title":"Thermo-mechanical structures for the optimisation of silicon micromachined gas sensors","authors":"A. Gotz, I. Gràcia, C. Cané, M. Lozano, E. Lora-Tamayo","doi":"10.1109/ICMTS.2000.844411","DOIUrl":"https://doi.org/10.1109/ICMTS.2000.844411","url":null,"abstract":"Thermal and mechanical characterisation has been carried out on simple test structures that allow the optimisation of the size, power consumption and mechanical robustness of thermally isolated membranes for semiconductor gas sensors fabricated on silicon micromachined substrates. Breakdown pressure, working temperature and heat distribution are the parameters that have been considered of interest for the development of the sensor structures.","PeriodicalId":447680,"journal":{"name":"ICMTS 2000. Proceedings of the 2000 International Conference on Microelectronic Test Structures (Cat. No.00CH37095)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124028204","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-03-13DOI: 10.1109/ICMTS.2000.844431
J. Klootwijk, G.C. Muda, D. Terpstra
We have developed and characterized new test structures for deep trench isolation in deep submicron BiCMOS technologies. These structures enable accurate characterization of the influence of trench isolation on device performance, without the necessity of fully processed lots. In particular capacitances, breakdown and leakage mechanisms can be investigated. This paper discusses the test structures, measurement methods (in particular separation of capacitance contributions) as well as some technological conclusions that were derived from measurement results that were obtained with the test structures.
{"title":"Characterization of trench isolation for BiCMOS technologies","authors":"J. Klootwijk, G.C. Muda, D. Terpstra","doi":"10.1109/ICMTS.2000.844431","DOIUrl":"https://doi.org/10.1109/ICMTS.2000.844431","url":null,"abstract":"We have developed and characterized new test structures for deep trench isolation in deep submicron BiCMOS technologies. These structures enable accurate characterization of the influence of trench isolation on device performance, without the necessity of fully processed lots. In particular capacitances, breakdown and leakage mechanisms can be investigated. This paper discusses the test structures, measurement methods (in particular separation of capacitance contributions) as well as some technological conclusions that were derived from measurement results that were obtained with the test structures.","PeriodicalId":447680,"journal":{"name":"ICMTS 2000. Proceedings of the 2000 International Conference on Microelectronic Test Structures (Cat. No.00CH37095)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132720749","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-03-13DOI: 10.1109/ICMTS.2000.844429
N. Rankin, A. Walton, J. McGinty, M. Fallon
This paper presents a methodology for predicting the effect of process input parameter variation on SPICE parameters early in the development of a new process. This is achieved by using TCAD generated measurement data calibrated from test structure measurement data gathered from an initial process. This methodology enables the same extraction strategy to be performed on TCAD and physical measurement data throughout the development of a semiconductor process ensuring data integrity. This assists both the process integration engineer and the design engineer in the optimisation of a process.
{"title":"SPICE sensitivity analysis of a bipolar test structure during process development","authors":"N. Rankin, A. Walton, J. McGinty, M. Fallon","doi":"10.1109/ICMTS.2000.844429","DOIUrl":"https://doi.org/10.1109/ICMTS.2000.844429","url":null,"abstract":"This paper presents a methodology for predicting the effect of process input parameter variation on SPICE parameters early in the development of a new process. This is achieved by using TCAD generated measurement data calibrated from test structure measurement data gathered from an initial process. This methodology enables the same extraction strategy to be performed on TCAD and physical measurement data throughout the development of a semiconductor process ensuring data integrity. This assists both the process integration engineer and the design engineer in the optimisation of a process.","PeriodicalId":447680,"journal":{"name":"ICMTS 2000. Proceedings of the 2000 International Conference on Microelectronic Test Structures (Cat. No.00CH37095)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133399056","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-03-13DOI: 10.1109/ICMTS.2000.844415
T. Kolding
This paper presents a unit test structure for investigation of bulk effects critical to scalable MOSFET models at gigahertz frequencies. The results are transformed into a generalized representation which may be used in conjunction with existing compact models. The gate-modified test structure is compatible with standard CMOS technology and reveals the dependence of diffusion bias on substrate effects. Several MOSFET layout guidelines are suggested for improved consistency between simulation and actual performance. Measuring examples are provided to illustrate bulk effects as well as the applicability of the method in a practical modeling situation.
{"title":"Test structure for universal estimation of MOSFET substrate effects at gigahertz frequencies","authors":"T. Kolding","doi":"10.1109/ICMTS.2000.844415","DOIUrl":"https://doi.org/10.1109/ICMTS.2000.844415","url":null,"abstract":"This paper presents a unit test structure for investigation of bulk effects critical to scalable MOSFET models at gigahertz frequencies. The results are transformed into a generalized representation which may be used in conjunction with existing compact models. The gate-modified test structure is compatible with standard CMOS technology and reveals the dependence of diffusion bias on substrate effects. Several MOSFET layout guidelines are suggested for improved consistency between simulation and actual performance. Measuring examples are provided to illustrate bulk effects as well as the applicability of the method in a practical modeling situation.","PeriodicalId":447680,"journal":{"name":"ICMTS 2000. Proceedings of the 2000 International Conference on Microelectronic Test Structures (Cat. No.00CH37095)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128026357","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-03-13DOI: 10.1109/ICMTS.2000.844436
D. Gloria, S. Gellida, G. Morin
High Frequency (HF) test structures for SiGe HBT and a parameter extraction methodology are described to obtain HF merit figures (Ft, Fmax, minimum noise figure NFmin, optimum source reflection coefficient GammaOPT, and noise equivalent resistance RN) in the temperature range -55/150 deg. The frequency range is 45 MHz-110 GHz for S parameters and 800 MHz-4 GHz for noise ones. Thanks to low substrate losses in these structures, a new fast de-embedding method for HF noise measurement is presented. Experimental data show an increase of base resistance, NFmin, GammaOPT, Rn and a decrease of Ft, Fmax with increasing temperatures because of the electron mobility evolution.
{"title":"A new extraction method of high frequency noise parameters in the temperature range -55/150 deg. for SiGe HBT in BiCMOS process","authors":"D. Gloria, S. Gellida, G. Morin","doi":"10.1109/ICMTS.2000.844436","DOIUrl":"https://doi.org/10.1109/ICMTS.2000.844436","url":null,"abstract":"High Frequency (HF) test structures for SiGe HBT and a parameter extraction methodology are described to obtain HF merit figures (Ft, Fmax, minimum noise figure NFmin, optimum source reflection coefficient GammaOPT, and noise equivalent resistance RN) in the temperature range -55/150 deg. The frequency range is 45 MHz-110 GHz for S parameters and 800 MHz-4 GHz for noise ones. Thanks to low substrate losses in these structures, a new fast de-embedding method for HF noise measurement is presented. Experimental data show an increase of base resistance, NFmin, GammaOPT, Rn and a decrease of Ft, Fmax with increasing temperatures because of the electron mobility evolution.","PeriodicalId":447680,"journal":{"name":"ICMTS 2000. Proceedings of the 2000 International Conference on Microelectronic Test Structures (Cat. No.00CH37095)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121374945","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-03-13DOI: 10.1109/ICMTS.2000.844395
S. AbuGhazaleh, P. Christie, S. Smith, A. Gundlach, J. Stevenson, A. Walton
This paper presents data characterizing alignment offsets in a commercial 1 /spl mu/m fabrication process using a combination of null wire segment holograms and a progressive offset technique. The test structure is essentially a binary computer generated hologram constructed from wire segments and is designed to project a null image when the masks for the process are in prefect alignment. Characterization using the technique indicates a mask misalignment of between 0.1 and 0.3 /spl mu/m, and this is confirmed using atomic force microscopy.
{"title":"Characterization of mask alignment offsets using null wire segment holograms and a progressive offset technique","authors":"S. AbuGhazaleh, P. Christie, S. Smith, A. Gundlach, J. Stevenson, A. Walton","doi":"10.1109/ICMTS.2000.844395","DOIUrl":"https://doi.org/10.1109/ICMTS.2000.844395","url":null,"abstract":"This paper presents data characterizing alignment offsets in a commercial 1 /spl mu/m fabrication process using a combination of null wire segment holograms and a progressive offset technique. The test structure is essentially a binary computer generated hologram constructed from wire segments and is designed to project a null image when the masks for the process are in prefect alignment. Characterization using the technique indicates a mask misalignment of between 0.1 and 0.3 /spl mu/m, and this is confirmed using atomic force microscopy.","PeriodicalId":447680,"journal":{"name":"ICMTS 2000. Proceedings of the 2000 International Conference on Microelectronic Test Structures (Cat. No.00CH37095)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115663240","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-03-13DOI: 10.1109/ICMTS.2000.844404
K. Doong, S. Hsieh, Sheng-che Lin, Binson Shen, Wang Chien-Jung, Yen-Hen Ho, J.Y. Cheng, Yeu-Haw Yang, K. Miyamoto, C. Hsu
Two types of addressable failure site test structures are developed. In-house program is coded to extract the electrical information and simulate the failure mode. A complete set of test structure modules for 0.25 um logic backend of line process is implemented in a test chip of 22/spl times/6.6 mm/sup 2/. By using the novel test structure, the yield analysis and defect tracking of BEOL process development as well as low-k Fluorinated SiO/sub 2/ (FSG) process optimization are demonstrated.
{"title":"Addressable failure site test structures (AFS-TS) for process development and optimization","authors":"K. Doong, S. Hsieh, Sheng-che Lin, Binson Shen, Wang Chien-Jung, Yen-Hen Ho, J.Y. Cheng, Yeu-Haw Yang, K. Miyamoto, C. Hsu","doi":"10.1109/ICMTS.2000.844404","DOIUrl":"https://doi.org/10.1109/ICMTS.2000.844404","url":null,"abstract":"Two types of addressable failure site test structures are developed. In-house program is coded to extract the electrical information and simulate the failure mode. A complete set of test structure modules for 0.25 um logic backend of line process is implemented in a test chip of 22/spl times/6.6 mm/sup 2/. By using the novel test structure, the yield analysis and defect tracking of BEOL process development as well as low-k Fluorinated SiO/sub 2/ (FSG) process optimization are demonstrated.","PeriodicalId":447680,"journal":{"name":"ICMTS 2000. Proceedings of the 2000 International Conference on Microelectronic Test Structures (Cat. No.00CH37095)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125874105","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-03-13DOI: 10.1109/ICMTS.2000.844410
G. Dalla Betta, G. Verzellesi, T. Boscardin, G. Pignatel, L. Bosisio, G. Soncini
The accuracy of the gated-diode method for extracting bulk generation lifetime and surface generation velocity in high resistivity silicon is shown to depend critically on the gate length of the adopted test device, as a result of nonidealities which are not accounted for by the measurement technique. Minimization of the surface generation velocity measurement error requires the gate length to be suitably reduced, while long gate devices are needed for accurate bulk generation lifetime extraction. Both parameters can be measured from a single test structure obtained by compenetrating a short gate device with a long gate one.
{"title":"Gate-length dependence of bulk generation lifetime and surface generation velocity measurement in high-resistivity silicon using gated diodes","authors":"G. Dalla Betta, G. Verzellesi, T. Boscardin, G. Pignatel, L. Bosisio, G. Soncini","doi":"10.1109/ICMTS.2000.844410","DOIUrl":"https://doi.org/10.1109/ICMTS.2000.844410","url":null,"abstract":"The accuracy of the gated-diode method for extracting bulk generation lifetime and surface generation velocity in high resistivity silicon is shown to depend critically on the gate length of the adopted test device, as a result of nonidealities which are not accounted for by the measurement technique. Minimization of the surface generation velocity measurement error requires the gate length to be suitably reduced, while long gate devices are needed for accurate bulk generation lifetime extraction. Both parameters can be measured from a single test structure obtained by compenetrating a short gate device with a long gate one.","PeriodicalId":447680,"journal":{"name":"ICMTS 2000. Proceedings of the 2000 International Conference on Microelectronic Test Structures (Cat. No.00CH37095)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130166137","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-03-13DOI: 10.1109/ICMTS.2000.844406
A. Skumanich, Man-Ping Cai, J. Educato, D. Yost
A methodology is described where wafers with specialized test structures are inspected with wafer metrology tools to assist process development for Cu BEOL fabrication. A Cu damascene interconnect process is examined from oxide deposition to final electrical test and the defects are tracked. E-test prioritizes the defects by the electrical impact. The inspection and tracking of defects facilitates defect sourcing, assists root cause analysis, and allows for more effective corrective action to be implemented.
{"title":"Use of test structures for Cu interconnect process development and yield enhancement","authors":"A. Skumanich, Man-Ping Cai, J. Educato, D. Yost","doi":"10.1109/ICMTS.2000.844406","DOIUrl":"https://doi.org/10.1109/ICMTS.2000.844406","url":null,"abstract":"A methodology is described where wafers with specialized test structures are inspected with wafer metrology tools to assist process development for Cu BEOL fabrication. A Cu damascene interconnect process is examined from oxide deposition to final electrical test and the defects are tracked. E-test prioritizes the defects by the electrical impact. The inspection and tracking of defects facilitates defect sourcing, assists root cause analysis, and allows for more effective corrective action to be implemented.","PeriodicalId":447680,"journal":{"name":"ICMTS 2000. Proceedings of the 2000 International Conference on Microelectronic Test Structures (Cat. No.00CH37095)","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131735803","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-03-13DOI: 10.1109/ICMTS.2000.844405
C. Hess, D. Stashower, B. Stine, G. Verna, L. Weiland, K. Miyamoto, K. Inoue
Defect inspection is required for process control and to enhance chip yield. Electrical measurements of test structures are commonly used to detect faults. To improve accuracy of electrically based determination of defect densities and defect size distributions, we present a novel NEST structure. There, many nested serpentine lines will be placed within a single layer only. This mask will be used as a short flow to guarantee a short turn around time for fast process data extraction. Data analysis procedures will provide densities and size distributions of killer defects that will have an impact on product chip yield.
{"title":"Fast extraction of killer defect density and size distribution using a single layer short flow NEST structure","authors":"C. Hess, D. Stashower, B. Stine, G. Verna, L. Weiland, K. Miyamoto, K. Inoue","doi":"10.1109/ICMTS.2000.844405","DOIUrl":"https://doi.org/10.1109/ICMTS.2000.844405","url":null,"abstract":"Defect inspection is required for process control and to enhance chip yield. Electrical measurements of test structures are commonly used to detect faults. To improve accuracy of electrically based determination of defect densities and defect size distributions, we present a novel NEST structure. There, many nested serpentine lines will be placed within a single layer only. This mask will be used as a short flow to guarantee a short turn around time for fast process data extraction. Data analysis procedures will provide densities and size distributions of killer defects that will have an impact on product chip yield.","PeriodicalId":447680,"journal":{"name":"ICMTS 2000. Proceedings of the 2000 International Conference on Microelectronic Test Structures (Cat. No.00CH37095)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130636297","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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