Pub Date : 2000-03-13DOI: 10.1109/ICMTS.2000.844435
P. Bellutti, G. Dalla Betta, N. Zorzi, R. Versari, A. Pieracci, B. Riccò, M. Manfredi, G. Soncini
Light emission from MOS tunnel diodes biased in the Fowler-Nordheim regime has been investigated by using especially designed test structures which avoid the obscuring effect of the poly-Si layer, thus allowing an efficient light emission from the Si substrate. The measured photon energy distribution of the emitted light is consistent with a hot carrier radiation model.
{"title":"Fowler Nordheim induced light emission from MOS diodes","authors":"P. Bellutti, G. Dalla Betta, N. Zorzi, R. Versari, A. Pieracci, B. Riccò, M. Manfredi, G. Soncini","doi":"10.1109/ICMTS.2000.844435","DOIUrl":"https://doi.org/10.1109/ICMTS.2000.844435","url":null,"abstract":"Light emission from MOS tunnel diodes biased in the Fowler-Nordheim regime has been investigated by using especially designed test structures which avoid the obscuring effect of the poly-Si layer, thus allowing an efficient light emission from the Si substrate. The measured photon energy distribution of the emitted light is consistent with a hot carrier radiation model.","PeriodicalId":447680,"journal":{"name":"ICMTS 2000. Proceedings of the 2000 International Conference on Microelectronic Test Structures (Cat. No.00CH37095)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126236172","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-03-13DOI: 10.1109/ICMTS.2000.844419
H. Tuinhout
This paper presents a study on MOSFET transconductance mismatch characterisation using MOSFET pairs with intentional 1% dimensional offsets. Furthermore, a new mismatch phenomenon is introduced that is attributed to mechanical strain associated with CMP dummy tiles.
{"title":"Characterisation of systematic MOSFET transconductance mismatch","authors":"H. Tuinhout","doi":"10.1109/ICMTS.2000.844419","DOIUrl":"https://doi.org/10.1109/ICMTS.2000.844419","url":null,"abstract":"This paper presents a study on MOSFET transconductance mismatch characterisation using MOSFET pairs with intentional 1% dimensional offsets. Furthermore, a new mismatch phenomenon is introduced that is attributed to mechanical strain associated with CMP dummy tiles.","PeriodicalId":447680,"journal":{"name":"ICMTS 2000. Proceedings of the 2000 International Conference on Microelectronic Test Structures (Cat. No.00CH37095)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131453696","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-03-13DOI: 10.1109/ICMTS.2000.844426
C. McAndrew, S. Sekine, A. Cassagnes, Zhicheng Wu
This paper presents effective DC electrical width models for MOSFETs and diffused resistors. The models account for the geometric width dependence on the LOCOS effect and the dog-bone (or webbing) effect, for devices defined by field oxide, and on the finite dopant source effect, for lowly doped resistors. The models are physically-based, C/sub /spl infin//-continuous functions of geometry, and significantly improve modeling of MOSFETs and resistors over geometry.
{"title":"Physically-based effective width modeling of MOSFETs and diffused resistors","authors":"C. McAndrew, S. Sekine, A. Cassagnes, Zhicheng Wu","doi":"10.1109/ICMTS.2000.844426","DOIUrl":"https://doi.org/10.1109/ICMTS.2000.844426","url":null,"abstract":"This paper presents effective DC electrical width models for MOSFETs and diffused resistors. The models account for the geometric width dependence on the LOCOS effect and the dog-bone (or webbing) effect, for devices defined by field oxide, and on the finite dopant source effect, for lowly doped resistors. The models are physically-based, C/sub /spl infin//-continuous functions of geometry, and significantly improve modeling of MOSFETs and resistors over geometry.","PeriodicalId":447680,"journal":{"name":"ICMTS 2000. Proceedings of the 2000 International Conference on Microelectronic Test Structures (Cat. No.00CH37095)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124382789","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-03-13DOI: 10.1109/ICMTS.2000.844421
J. Hunter, P. Gudem, S. Winters
This paper describes a differential floating gate capacitance matching measurement technique that offers a significant improvement in resolution over those previously reported. It's smaller differential output voltage can be measured to a much higher precision than that of a standard structure. In addition, the differential technique offers superior cancellation of parasitic overlap capacitance effects. Our technique was successfully demonstrated on a 0.50 /spl mu/m analog BiCMOS technology.
{"title":"A differential floating gate capacitance mismatch measurement technique","authors":"J. Hunter, P. Gudem, S. Winters","doi":"10.1109/ICMTS.2000.844421","DOIUrl":"https://doi.org/10.1109/ICMTS.2000.844421","url":null,"abstract":"This paper describes a differential floating gate capacitance matching measurement technique that offers a significant improvement in resolution over those previously reported. It's smaller differential output voltage can be measured to a much higher precision than that of a standard structure. In addition, the differential technique offers superior cancellation of parasitic overlap capacitance effects. Our technique was successfully demonstrated on a 0.50 /spl mu/m analog BiCMOS technology.","PeriodicalId":447680,"journal":{"name":"ICMTS 2000. Proceedings of the 2000 International Conference on Microelectronic Test Structures (Cat. No.00CH37095)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128421960","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-03-13DOI: 10.1109/ICMTS.2000.844396
R. Allen, L. W. Linholm, M. Cresswell, C. Ellenwood
A technique has been developed to fabricate 100-nm critical dimension (CD) reference features with i-line lithography by utilizing a unique characteristic of single-crystal silicon-on-insulator films: under certain etch conditions, the edges of features align to crystallographic surfaces. In this paper we describe this technique, show results of the process, and present electrical CD measurements that support the use of this technique for producing current and future generations of reference materials for the semiconductor industry.
{"title":"A novel method for fabricating CD reference materials with 100 nm linewidths","authors":"R. Allen, L. W. Linholm, M. Cresswell, C. Ellenwood","doi":"10.1109/ICMTS.2000.844396","DOIUrl":"https://doi.org/10.1109/ICMTS.2000.844396","url":null,"abstract":"A technique has been developed to fabricate 100-nm critical dimension (CD) reference features with i-line lithography by utilizing a unique characteristic of single-crystal silicon-on-insulator films: under certain etch conditions, the edges of features align to crystallographic surfaces. In this paper we describe this technique, show results of the process, and present electrical CD measurements that support the use of this technique for producing current and future generations of reference materials for the semiconductor industry.","PeriodicalId":447680,"journal":{"name":"ICMTS 2000. Proceedings of the 2000 International Conference on Microelectronic Test Structures (Cat. No.00CH37095)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126399870","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-03-13DOI: 10.1109/ICMTS.2000.844402
D. W. Travis, C. Reeves, A. Walton, A. Gundlach, J. Stevenson
A focused ion beam system has been used to demonstrate the modification of the effective electrical width of a MOS transistor. The internal structure of the transistor test structure is modified using two distinct approaches, where the cut axis is either parallel or orthogonal to the source-drain axis. This paper demonstrates the feasibility of modifying transistor characteristics which can be used to evaluate processes and to modify circuit designs.
{"title":"Characterization of sub-micron MOS transistors, modified using a focused ion beam system","authors":"D. W. Travis, C. Reeves, A. Walton, A. Gundlach, J. Stevenson","doi":"10.1109/ICMTS.2000.844402","DOIUrl":"https://doi.org/10.1109/ICMTS.2000.844402","url":null,"abstract":"A focused ion beam system has been used to demonstrate the modification of the effective electrical width of a MOS transistor. The internal structure of the transistor test structure is modified using two distinct approaches, where the cut axis is either parallel or orthogonal to the source-drain axis. This paper demonstrates the feasibility of modifying transistor characteristics which can be used to evaluate processes and to modify circuit designs.","PeriodicalId":447680,"journal":{"name":"ICMTS 2000. Proceedings of the 2000 International Conference on Microelectronic Test Structures (Cat. No.00CH37095)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134343388","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-03-13DOI: 10.1109/ICMTS.2000.844412
G. Knoblinger, P. Klein, U. Baumann
We present a simple and efficient method for the extraction of thermal channel noise of MOSFET's in quarter and sub-quarter micron technologies from NF50 (noise figure at 50 ohm source resistance) measurements. For shorter channel lengths the experimental results shows a continuously rising deviation from the classical long channel theory. For a 0.18 /spl mu/m technology a /spl phi//spl ap/6 instead of 2/3 in saturation was extracted (increase of factor 9 compared to the long channel theory).
{"title":"Thermal channel noise of quarter and sub-quarter micron NMOSFET's","authors":"G. Knoblinger, P. Klein, U. Baumann","doi":"10.1109/ICMTS.2000.844412","DOIUrl":"https://doi.org/10.1109/ICMTS.2000.844412","url":null,"abstract":"We present a simple and efficient method for the extraction of thermal channel noise of MOSFET's in quarter and sub-quarter micron technologies from NF50 (noise figure at 50 ohm source resistance) measurements. For shorter channel lengths the experimental results shows a continuously rising deviation from the classical long channel theory. For a 0.18 /spl mu/m technology a /spl phi//spl ap/6 instead of 2/3 in saturation was extracted (increase of factor 9 compared to the long channel theory).","PeriodicalId":447680,"journal":{"name":"ICMTS 2000. Proceedings of the 2000 International Conference on Microelectronic Test Structures (Cat. No.00CH37095)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134601285","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-03-13DOI: 10.1109/ICMTS.2000.844420
R. Thewes, C. Linnenbank, U. Kollmer, S. Burges, M. Dileo, M. Clincy, U. Schaper, R. Brederlow, R. Seibert, W. Weber
An array test structure for precise characterization of the matching behavior of MOSFETs is presented. Besides the standard mismatch parameter drain current I/sub D/, the high resolution measurement principle allows the characterization of the small signal parameters transconductance g/sub m/ and in particular differential output conductance g/sub DS/. Measured data are shown to demonstrate the performance of the method. Whereas for the normalized standard deviations of I/sub D/ and g/sub m/ the well known proportionality to (WL)/sup -1/2/ is obtained, the normalized standard deviation of g/sub DS/ clearly deviates from this width and length dependence. For this parameter, proportionality to W/sup -1/2/ is found.
{"title":"On the matching behavior of MOSFET small signal parameters","authors":"R. Thewes, C. Linnenbank, U. Kollmer, S. Burges, M. Dileo, M. Clincy, U. Schaper, R. Brederlow, R. Seibert, W. Weber","doi":"10.1109/ICMTS.2000.844420","DOIUrl":"https://doi.org/10.1109/ICMTS.2000.844420","url":null,"abstract":"An array test structure for precise characterization of the matching behavior of MOSFETs is presented. Besides the standard mismatch parameter drain current I/sub D/, the high resolution measurement principle allows the characterization of the small signal parameters transconductance g/sub m/ and in particular differential output conductance g/sub DS/. Measured data are shown to demonstrate the performance of the method. Whereas for the normalized standard deviations of I/sub D/ and g/sub m/ the well known proportionality to (WL)/sup -1/2/ is obtained, the normalized standard deviation of g/sub DS/ clearly deviates from this width and length dependence. For this parameter, proportionality to W/sup -1/2/ is found.","PeriodicalId":447680,"journal":{"name":"ICMTS 2000. Proceedings of the 2000 International Conference on Microelectronic Test Structures (Cat. No.00CH37095)","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124658790","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-03-13DOI: 10.1109/ICMTS.2000.844425
S. Chetlur, J. Zaneski, L. Mullin, A. Oates, R. Ashton, H. Chew, J. Zhou
Self-stressing testers are used to study the impact of input voltage swing on the aging behavior of 0.18 NMOS devices in inverters. When the frequency and rise/fall time of the input pulse are altered, we demonstrate that the effective aging time 't/sub eff/' per clock cycle varies with the rise/fall transitions and is the main factor in deciding NMOS degradation.
{"title":"Influence of input voltage swing on 0.18 /spl mu/m NMOS aging estimated by self-stressing testers","authors":"S. Chetlur, J. Zaneski, L. Mullin, A. Oates, R. Ashton, H. Chew, J. Zhou","doi":"10.1109/ICMTS.2000.844425","DOIUrl":"https://doi.org/10.1109/ICMTS.2000.844425","url":null,"abstract":"Self-stressing testers are used to study the impact of input voltage swing on the aging behavior of 0.18 NMOS devices in inverters. When the frequency and rise/fall time of the input pulse are altered, we demonstrate that the effective aging time 't/sub eff/' per clock cycle varies with the rise/fall transitions and is the main factor in deciding NMOS degradation.","PeriodicalId":447680,"journal":{"name":"ICMTS 2000. Proceedings of the 2000 International Conference on Microelectronic Test Structures (Cat. No.00CH37095)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121786840","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-03-13DOI: 10.1109/ICMTS.2000.844400
X. Ouyang, T. Deeter, C. N. Berglund, R. Pease, M. McCord
SRAM circuits have been used as electrical test structures to study short range spatial variations of MOS transistor effective gate length. Layout-dependent periodic errors were found to take up 30% to 90% of the total observed error variance, depending on the spatial frequency range and specific measurement grid used. Peaks in the measured gate-length error spatial spectrum were related to the periodicities existing in the circuit layout, and lithography simulations were done to identify the error sources. It was found that proximity effects, overlay errors due to stepper lens aberration, and pattern dependent coma effects contributed to a large percentage of the high spatial frequency errors observed.
{"title":"High-spatial-frequency MOS transistor gate length variations in SRAM circuits","authors":"X. Ouyang, T. Deeter, C. N. Berglund, R. Pease, M. McCord","doi":"10.1109/ICMTS.2000.844400","DOIUrl":"https://doi.org/10.1109/ICMTS.2000.844400","url":null,"abstract":"SRAM circuits have been used as electrical test structures to study short range spatial variations of MOS transistor effective gate length. Layout-dependent periodic errors were found to take up 30% to 90% of the total observed error variance, depending on the spatial frequency range and specific measurement grid used. Peaks in the measured gate-length error spatial spectrum were related to the periodicities existing in the circuit layout, and lithography simulations were done to identify the error sources. It was found that proximity effects, overlay errors due to stepper lens aberration, and pattern dependent coma effects contributed to a large percentage of the high spatial frequency errors observed.","PeriodicalId":447680,"journal":{"name":"ICMTS 2000. Proceedings of the 2000 International Conference on Microelectronic Test Structures (Cat. No.00CH37095)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115250978","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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