Pub Date : 2000-03-13DOI: 10.1109/ICMTS.2000.844416
H. Aoki, M. Ikeda, K. Asada
With increasing interconnect densities, voltage bounce noise in power supply lines is becoming an important problem. In this paper, we describe a method to measure voltage bounce in a power supply line on a chip. We use a voltage comparator circuit to make the output a digital value. We connect this circuit in series to output the results with less pins.
{"title":"On-chip voltage noise monitor for measuring voltage bounce in power supply lines using a digital tester","authors":"H. Aoki, M. Ikeda, K. Asada","doi":"10.1109/ICMTS.2000.844416","DOIUrl":"https://doi.org/10.1109/ICMTS.2000.844416","url":null,"abstract":"With increasing interconnect densities, voltage bounce noise in power supply lines is becoming an important problem. In this paper, we describe a method to measure voltage bounce in a power supply line on a chip. We use a voltage comparator circuit to make the output a digital value. We connect this circuit in series to output the results with less pins.","PeriodicalId":447680,"journal":{"name":"ICMTS 2000. Proceedings of the 2000 International Conference on Microelectronic Test Structures (Cat. No.00CH37095)","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115379172","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-03-13DOI: 10.1109/ICMTS.2000.844407
F. Caignet, S. Dhia, E. Sicard
The benefits expected by the decreases of feature sizes in high-speed electronic's circuits are limited by the increased parasitic effects of interconnect. This paper details the application of an on-chip time domain technique to the characterization of propagation delay, crosstalk and crosstalk-induced delay, along interconnects in deep submicron technology. The measurement system is detailed, together with the signal integrity patterns and their implementation in 0.18 CMOS technology. Measurement obtained with this technique are presented and compared with simulations.
{"title":"A microelectronic test structure for signal integrity characterization in deep submicron technology","authors":"F. Caignet, S. Dhia, E. Sicard","doi":"10.1109/ICMTS.2000.844407","DOIUrl":"https://doi.org/10.1109/ICMTS.2000.844407","url":null,"abstract":"The benefits expected by the decreases of feature sizes in high-speed electronic's circuits are limited by the increased parasitic effects of interconnect. This paper details the application of an on-chip time domain technique to the characterization of propagation delay, crosstalk and crosstalk-induced delay, along interconnects in deep submicron technology. The measurement system is detailed, together with the signal integrity patterns and their implementation in 0.18 CMOS technology. Measurement obtained with this technique are presented and compared with simulations.","PeriodicalId":447680,"journal":{"name":"ICMTS 2000. Proceedings of the 2000 International Conference on Microelectronic Test Structures (Cat. No.00CH37095)","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115681903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-02-29DOI: 10.1109/ICMTS.2000.844393
M. Cresswell, R. Allen, R. Ghoshtagore, N. Guillaume, P. Shea, S. C. Everist, L. W. Linholm
This paper describes the fabrication and measurement of the linewidths of the reference segments of cross-bridge resistors patterned in [100] Bonded and Etched Back Silicon-on-Insulator (BESOI) material. The critical dimensions (CD) of the reference segments of a selection of the cross-bridge resistor test structures were measured both electrically and by Scanning-Electron Microscopy (SEM) cross-section imaging.
{"title":"Characterization of electrical linewidth test structures patterned in [100] silicon-on-insulator for use as CD standards","authors":"M. Cresswell, R. Allen, R. Ghoshtagore, N. Guillaume, P. Shea, S. C. Everist, L. W. Linholm","doi":"10.1109/ICMTS.2000.844393","DOIUrl":"https://doi.org/10.1109/ICMTS.2000.844393","url":null,"abstract":"This paper describes the fabrication and measurement of the linewidths of the reference segments of cross-bridge resistors patterned in [100] Bonded and Etched Back Silicon-on-Insulator (BESOI) material. The critical dimensions (CD) of the reference segments of a selection of the cross-bridge resistor test structures were measured both electrically and by Scanning-Electron Microscopy (SEM) cross-section imaging.","PeriodicalId":447680,"journal":{"name":"ICMTS 2000. Proceedings of the 2000 International Conference on Microelectronic Test Structures (Cat. No.00CH37095)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-02-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116888626","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-04-25DOI: 10.1109/ICMTS.2000.844408
T. Ohzone, M. Yuzaki, T. Matsuda, E. Kameda
Two dimensional photoemission profiles from n-MOSFETs supplying various pulse waveforms to the gate were measured and analyzed by a photoemission microscope. TPC (Total Photon Counts) were proportional to average drain and substrate currents under dynamic operation as observed under DC operation. TPC profiles of wide channel width MOSFETs, however, varied along the channel width direction under dynamic operation. It suggests that the substrate current distribution fluctuates along the channel width direction and affects the device lifetime.
{"title":"A study on hot-carrier-induced photoemission in n-MOSFETs under dynamic operation","authors":"T. Ohzone, M. Yuzaki, T. Matsuda, E. Kameda","doi":"10.1109/ICMTS.2000.844408","DOIUrl":"https://doi.org/10.1109/ICMTS.2000.844408","url":null,"abstract":"Two dimensional photoemission profiles from n-MOSFETs supplying various pulse waveforms to the gate were measured and analyzed by a photoemission microscope. TPC (Total Photon Counts) were proportional to average drain and substrate currents under dynamic operation as observed under DC operation. TPC profiles of wide channel width MOSFETs, however, varied along the channel width direction under dynamic operation. It suggests that the substrate current distribution fluctuates along the channel width direction and affects the device lifetime.","PeriodicalId":447680,"journal":{"name":"ICMTS 2000. Proceedings of the 2000 International Conference on Microelectronic Test Structures (Cat. No.00CH37095)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131371248","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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