In this paper we are interested in safety-critical real-time applications implemented on distributed architectures using the Time-Sensitive Networking (TSN) standard. The ongoing standardization of TSN is an IEEE effort to bring deterministic real-time capabilities into the IEEE 802.1 Ethernet standard supporting safety-critical systems and guaranteed Quality-of-Service. TSN will support Time-Triggered (TT) communication based on schedule tables, Audio-Video-Bridging (AVB) streams with bounded end-to-end latency as well as Best-Effort messages. We consider that we know the topology of the network as well as the routes and schedules of the TT streams. We are interested to determine the routing of the AVB streams such that all frames are schedulable and their worst-case end-to-end delay is minimized. We have proposed a search-space reduction technique and a Greedy Randomized Adaptive Search Procedure (GRASP)-based heuristic for this routing optimization problem. The proposed approaches has been evaluated using several test cases.
{"title":"Routing optimization of AVB streams in TSN networks","authors":"Sune Mølgaard Laursen, P. Pop, W. Steiner","doi":"10.1145/3015037.3015044","DOIUrl":"https://doi.org/10.1145/3015037.3015044","url":null,"abstract":"In this paper we are interested in safety-critical real-time applications implemented on distributed architectures using the Time-Sensitive Networking (TSN) standard. The ongoing standardization of TSN is an IEEE effort to bring deterministic real-time capabilities into the IEEE 802.1 Ethernet standard supporting safety-critical systems and guaranteed Quality-of-Service. TSN will support Time-Triggered (TT) communication based on schedule tables, Audio-Video-Bridging (AVB) streams with bounded end-to-end latency as well as Best-Effort messages. We consider that we know the topology of the network as well as the routes and schedules of the TT streams. We are interested to determine the routing of the AVB streams such that all frames are schedulable and their worst-case end-to-end delay is minimized. We have proposed a search-space reduction technique and a Greedy Randomized Adaptive Search Procedure (GRASP)-based heuristic for this routing optimization problem. The proposed approaches has been evaluated using several test cases.","PeriodicalId":447904,"journal":{"name":"SIGBED Rev.","volume":"224 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133584189","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper we present a compositional model for distributed virtualized systems communicating over on-chip/off-chip deterministic networks implementing an end-to-end or partial time-triggered paradigm. We derive system-level constraints for combined task-, virtualization-and network-level static scheduling enabling the end-to-end composition of schedules for systems featuring table-driven (guest) operating systems. In the absence of a time-triggered run-time system, we analyze the composition problem with the aid of hierarchical scheduling methods for abstract resources. Moreover, we identify and discuss possible tradeoffs and optimization opportunities that arise when scheduling across multiple (virtualized) software layers in tandem with the deterministic network.
{"title":"Hierarchical scheduling over off- and on-chip deterministic networks","authors":"Ramon Serna Oliver, Silviu S. Craciunas","doi":"10.1145/3015037.3015039","DOIUrl":"https://doi.org/10.1145/3015037.3015039","url":null,"abstract":"In this paper we present a compositional model for distributed virtualized systems communicating over on-chip/off-chip deterministic networks implementing an end-to-end or partial time-triggered paradigm. We derive system-level constraints for combined task-, virtualization-and network-level static scheduling enabling the end-to-end composition of schedules for systems featuring table-driven (guest) operating systems. In the absence of a time-triggered run-time system, we analyze the composition problem with the aid of hierarchical scheduling methods for abstract resources. Moreover, we identify and discuss possible tradeoffs and optimization opportunities that arise when scheduling across multiple (virtualized) software layers in tandem with the deterministic network.","PeriodicalId":447904,"journal":{"name":"SIGBED Rev.","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114458990","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Nassima Benammar, Henri Bauer, F. Ridouard, P. Richard
The AFDX (Avionics Full DupleX Switched Ethernet) is the backbone network of most recent avionic communication systems. These systems require deterministic buffer dimensioning for certification reasons. As in such systems, static design is often preferred over dynamic allocation, a dimensioning in terms of frames rather than in terms of bits can be required. A common approach consists in deriving the worst-case buffer size in terms of frames from the worst-case in bits. However, we show that this can lead to an overestimation of the buffer size. Thus, we propose a dedicated approach for a tighter dimensioning. Eventually, the two approaches are compared on a sample AFDX configuration.
{"title":"Tighter buffer dimensioning in AFDX networks","authors":"Nassima Benammar, Henri Bauer, F. Ridouard, P. Richard","doi":"10.1145/3015037.3015043","DOIUrl":"https://doi.org/10.1145/3015037.3015043","url":null,"abstract":"The AFDX (Avionics Full DupleX Switched Ethernet) is the backbone network of most recent avionic communication systems. These systems require deterministic buffer dimensioning for certification reasons. As in such systems, static design is often preferred over dynamic allocation, a dimensioning in terms of frames rather than in terms of bits can be required.\u0000 A common approach consists in deriving the worst-case buffer size in terms of frames from the worst-case in bits. However, we show that this can lead to an overestimation of the buffer size. Thus, we propose a dedicated approach for a tighter dimensioning. Eventually, the two approaches are compared on a sample AFDX configuration.","PeriodicalId":447904,"journal":{"name":"SIGBED Rev.","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130204642","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Cloud computing technology provides the means to share physical resources among multiple users and data center tenants by exposing them as virtual resources. There is a strong industrial drive to use similar technology and concepts to provide timing sensitive services. One such is virtual networking services, so called services chains, which consist of several interconnected virtual network functions. This allows for the capacity to be scaled up and down by adding or removing virtual resources. In this work, we develop a model of a service chain and pose the dynamic allocation of resources as an optimization problem. We design and present a set of strategies to allot virtual network nodes in an optimal fashion subject to latency and buffer constraints.
{"title":"Cost minimization of network services with buffer and end-to-end deadline constraints","authors":"Victor Millnert, Enrico Bini, J. Eker","doi":"10.1145/3177803.3177810","DOIUrl":"https://doi.org/10.1145/3177803.3177810","url":null,"abstract":"Cloud computing technology provides the means to share physical resources among multiple users and data center tenants by exposing them as virtual resources. There is a strong industrial drive to use similar technology and concepts to provide timing sensitive services. One such is virtual networking services, so called services chains, which consist of several interconnected virtual network functions. This allows for the capacity to be scaled up and down by adding or removing virtual resources. In this work, we develop a model of a service chain and pose the dynamic allocation of resources as an optimization problem. We design and present a set of strategies to allot virtual network nodes in an optimal fashion subject to latency and buffer constraints.","PeriodicalId":447904,"journal":{"name":"SIGBED Rev.","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125292048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Many solutions for composability and compositionality rely on specifying the interface for a component using bandwidth. Some previous works specify period (P) and budget (Q) as an interface for a component. Q/P provides us with a bandwidth (the share of a processor that this component may request); P specifies the time-granularity of the allocation of this processing capacity. Other works add another parameter deadline which can help to provide tighter bounds on how this processing capacity is distributed. Yet other works use the parameters α and Δ where α is the bandwidth and Δ specifies how smoothly this bandwidth is distributed. It is known [4] that such bandwidth-like interfaces carry a cost: there are tasksets that could be guaranteed to be schedulable if tasks were scheduled directly on the processor, but with bandwidth-like interfaces, it is impossible to guarantee the taskset to be schedulable. And it is also known that this penalty can be infinite, i.e., the use of bandwidth-like interfaces may require the use of a processor that has a speed that is k times faster, and one can show this for any k. This brings the question: "What is the average-case performance penalty of bandwidth-like interfaces?" This paper addresses this question. We answer the question by randomly generating tasksets and then for each of these tasksets, compute a lower bound on how much faster a processor needs to be when a bandwidth-like scheme is used. We do not consider any specific bandwidth-like scheme; instead, we derive an expression that states a lower bound on how much faster a processor needs to be when a bandwidth-like scheme is used. For the distributions considered in this paper, we find that (i) the experimental results depend on the experimental setup, (ii) this lower bound on the penalty was never larger than 4.0, (iii) for one experimental setup, for each taskset, it was greater than 2.4, (iv) the histogram of this penalty appears to be unimodal, and (v) for implicit-deadline sporadic tasks, this lower bound on the penalty was exactly 1.
{"title":"Evaluating the average-case performance penalty of bandwidth-like interfaces","authors":"Björn Andersson","doi":"10.1145/2983185.2983191","DOIUrl":"https://doi.org/10.1145/2983185.2983191","url":null,"abstract":"Many solutions for composability and compositionality rely on specifying the interface for a component using bandwidth. Some previous works specify period (P) and budget (Q) as an interface for a component. Q/P provides us with a bandwidth (the share of a processor that this component may request); P specifies the time-granularity of the allocation of this processing capacity. Other works add another parameter deadline which can help to provide tighter bounds on how this processing capacity is distributed. Yet other works use the parameters α and Δ where α is the bandwidth and Δ specifies how smoothly this bandwidth is distributed. It is known [4] that such bandwidth-like interfaces carry a cost: there are tasksets that could be guaranteed to be schedulable if tasks were scheduled directly on the processor, but with bandwidth-like interfaces, it is impossible to guarantee the taskset to be schedulable. And it is also known that this penalty can be infinite, i.e., the use of bandwidth-like interfaces may require the use of a processor that has a speed that is k times faster, and one can show this for any k. This brings the question: \"What is the average-case performance penalty of bandwidth-like interfaces?\" This paper addresses this question. We answer the question by randomly generating tasksets and then for each of these tasksets, compute a lower bound on how much faster a processor needs to be when a bandwidth-like scheme is used. We do not consider any specific bandwidth-like scheme; instead, we derive an expression that states a lower bound on how much faster a processor needs to be when a bandwidth-like scheme is used. For the distributions considered in this paper, we find that (i) the experimental results depend on the experimental setup, (ii) this lower bound on the penalty was never larger than 4.0, (iii) for one experimental setup, for each taskset, it was greater than 2.4, (iv) the histogram of this penalty appears to be unimodal, and (v) for implicit-deadline sporadic tasks, this lower bound on the penalty was exactly 1.","PeriodicalId":447904,"journal":{"name":"SIGBED Rev.","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121451581","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Sara Afshar, N. Khalilzad, M. Behnam, R. J. Bril, Thomas Nolte
Component-based software development facilitates the development process of large and complex software systems. By the advent of multiprocessors, the independently developed components can be integrated on a multi-core platform to achieve an efficient use of system hardware and a decrease in system power consumption and costs. In this paper, we consider a virtual multiprocessor platform where each component can be dynamically allocated to any set of processors of the platform with a maximum concurrency level. Global-EDF is used for intra-component scheduling. The existing analysis for such systems have assumed that tasks are independent. In this paper, we enable intra-component resource sharing for this platform. We investigate using a spin-based resource sharing protocol with the accompanying analysis that extends the existing analysis for independent tasks. We briefly illustrate and evaluate our initial results with an example.
{"title":"Intra-component resource sharing on a virtual multiprocessor platform","authors":"Sara Afshar, N. Khalilzad, M. Behnam, R. J. Bril, Thomas Nolte","doi":"10.1145/2983185.2983190","DOIUrl":"https://doi.org/10.1145/2983185.2983190","url":null,"abstract":"Component-based software development facilitates the development process of large and complex software systems. By the advent of multiprocessors, the independently developed components can be integrated on a multi-core platform to achieve an efficient use of system hardware and a decrease in system power consumption and costs. In this paper, we consider a virtual multiprocessor platform where each component can be dynamically allocated to any set of processors of the platform with a maximum concurrency level. Global-EDF is used for intra-component scheduling. The existing analysis for such systems have assumed that tasks are independent. In this paper, we enable intra-component resource sharing for this platform. We investigate using a spin-based resource sharing protocol with the accompanying analysis that extends the existing analysis for independent tasks. We briefly illustrate and evaluate our initial results with an example.","PeriodicalId":447904,"journal":{"name":"SIGBED Rev.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116088897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Interface-based compositional analysis is by now a fairly established area of research in real-time systems. However, current research has not yet fully considered practical aspects, such as the effects of cache interferences on multicore platforms. This position paper discusses the analysis challenges and motivates the need for cache scheduling in this setting, and it highlights several research questions towards cache-aware interfaces for compositional systems on multicore platforms.
{"title":"Cache-aware interfaces for compositional real-time systems: invited paper","authors":"L. T. Phan, Meng Xu, Insup Lee","doi":"10.1145/2983185.2983194","DOIUrl":"https://doi.org/10.1145/2983185.2983194","url":null,"abstract":"Interface-based compositional analysis is by now a fairly established area of research in real-time systems. However, current research has not yet fully considered practical aspects, such as the effects of cache interferences on multicore platforms. This position paper discusses the analysis challenges and motivates the need for cache scheduling in this setting, and it highlights several research questions towards cache-aware interfaces for compositional systems on multicore platforms.","PeriodicalId":447904,"journal":{"name":"SIGBED Rev.","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132540348","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Time-constrained networks have demanded so far for deterministic modeling and analysis in order to guarantee their worst-case behavior. With this work we intend to apply both probabilistic modeling and probabilistic analyses to investigate such networks. The probabilistic framework we propose aims at guaranteeing confidence levels, in the form of probabilities, to the network timing constraints; the deterministic case remain a particular case, the worst-case, within the probabilistic framework. We focus on probabilistic bounds for defining probabilistic interfaces to network components and we study the way that probabilities propagate within networks by accounting for the dependences and the interactions between network components. Finally, we define and apply probabilistic performance metrics for evaluating network behavior with different degree of confidence due to the probabilities.
{"title":"Probabilistic component-based analysis for networks: invited paper","authors":"L. Santinelli","doi":"10.1145/2983185.2983197","DOIUrl":"https://doi.org/10.1145/2983185.2983197","url":null,"abstract":"Time-constrained networks have demanded so far for deterministic modeling and analysis in order to guarantee their worst-case behavior. With this work we intend to apply both probabilistic modeling and probabilistic analyses to investigate such networks. The probabilistic framework we propose aims at guaranteeing confidence levels, in the form of probabilities, to the network timing constraints; the deterministic case remain a particular case, the worst-case, within the probabilistic framework. We focus on probabilistic bounds for defining probabilistic interfaces to network components and we study the way that probabilities propagate within networks by accounting for the dependences and the interactions between network components. Finally, we define and apply probabilistic performance metrics for evaluating network behavior with different degree of confidence due to the probabilities.","PeriodicalId":447904,"journal":{"name":"SIGBED Rev.","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124868269","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Compositional theories and technologies facilitate the decomposition of a complex system into components, as well as their integration via interfaces. Component interfaces hide the internal details of the components, thereby reducing integration complexity. A system is said to be composable if the properties established and validated for components in isolation hold once the components are integrated to form the system. This brings us the question: "Is compositionality related to composability?" This paper answers this question in the affirmative; it considers a previously known interface for compositionality and shows that it can be used for composability. It also presents a run-time policing mechanism for this interface.
{"title":"Turning compositionality into composability","authors":"Björn Andersson","doi":"10.1145/2983185.2983189","DOIUrl":"https://doi.org/10.1145/2983185.2983189","url":null,"abstract":"Compositional theories and technologies facilitate the decomposition of a complex system into components, as well as their integration via interfaces. Component interfaces hide the internal details of the components, thereby reducing integration complexity. A system is said to be composable if the properties established and validated for components in isolation hold once the components are integrated to form the system. This brings us the question: \"Is compositionality related to composability?\" This paper answers this question in the affirmative; it considers a previously known interface for compositionality and shows that it can be used for composability. It also presents a run-time policing mechanism for this interface.","PeriodicalId":447904,"journal":{"name":"SIGBED Rev.","volume":"138 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122918678","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The Internet of Things (IoT) refers to extending the reach of the Internet into the physical world. The realization of IoT applications involves the integrated operation of many subsystems that retain their private function. This makes IoT application deployment and integration a Systems of Systems (SoS) problem. In this paper we collect SoS properties and characteristics from the literature in order to understand common integration problems in IoT better, for which we use two running examples. We show that in particular for safety critical systems there must be means to compute and predict integrated behavior based on specifications at interfaces. We give a general coordination architecture that supports this.
{"title":"A systems of systems perspective on the internet of things: invited paper","authors":"J. Lukkien","doi":"10.1145/2983185.2983195","DOIUrl":"https://doi.org/10.1145/2983185.2983195","url":null,"abstract":"The Internet of Things (IoT) refers to extending the reach of the Internet into the physical world. The realization of IoT applications involves the integrated operation of many subsystems that retain their private function. This makes IoT application deployment and integration a Systems of Systems (SoS) problem. In this paper we collect SoS properties and characteristics from the literature in order to understand common integration problems in IoT better, for which we use two running examples. We show that in particular for safety critical systems there must be means to compute and predict integrated behavior based on specifications at interfaces. We give a general coordination architecture that supports this.","PeriodicalId":447904,"journal":{"name":"SIGBED Rev.","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127248230","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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