Martin Törngren, M. Grimheden, Jonas Gustafsson, W. Birk
Embedded and Cyber-Physical Systems education faces several challenges as well as opportunities as every-"thing" becomes connected, and as technology development accelerates. Initiatives such as CDIO, as well as several other academic and industry initiatives to create new CPS programs illustrate strong interests and awareness of these challenges. We provide an overview of foreseen educational needs, existing state of the art in education and an analysis of the subject of CPS with the purpose of understanding the implications for education. The investigation points to key issues in curriculum design regarding balancing depth and breadth, theory and practices, academic and industrial needs, and core technical skills with complementary skills. Curricula in CPS could, if the right balance is achieved, educate CPS engineers of the future that are "ready to engineer". We conclude by synthesizing high level guidelines in terms of strategies and considerations for CPS curriculum development.
{"title":"Strategies and considerations in shaping cyber-physical systems education","authors":"Martin Törngren, M. Grimheden, Jonas Gustafsson, W. Birk","doi":"10.1145/3036686.3036693","DOIUrl":"https://doi.org/10.1145/3036686.3036693","url":null,"abstract":"Embedded and Cyber-Physical Systems education faces several challenges as well as opportunities as every-\"thing\" becomes connected, and as technology development accelerates. Initiatives such as CDIO, as well as several other academic and industry initiatives to create new CPS programs illustrate strong interests and awareness of these challenges. We provide an overview of foreseen educational needs, existing state of the art in education and an analysis of the subject of CPS with the purpose of understanding the implications for education. The investigation points to key issues in curriculum design regarding balancing depth and breadth, theory and practices, academic and industrial needs, and core technical skills with complementary skills. Curricula in CPS could, if the right balance is achieved, educate CPS engineers of the future that are \"ready to engineer\". We conclude by synthesizing high level guidelines in terms of strategies and considerations for CPS curriculum development.","PeriodicalId":447904,"journal":{"name":"SIGBED Rev.","volume":"63 1-3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-01-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132908770","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
C. Maxim, A. Gogonel, I. Asavoae, Mihail Asavoae, L. Cucu-Grosjean
The increased number of systems consisting of multiple interacting components imposes the evolution of timing analyses towards methods able to estimate the timing behavior of an entire system by aggregating timings bounds of its components. In this paper we propose the first discussion on the properties required by measurement-based timing analyses to ensure such compositionality. We identify the properties of reproducibility and representativity as necessary conditions to ensure the convergence of any measurement protocol allowing a compositional measurement-based timing analysis.
{"title":"Reproducibility and representativity: mandatory properties for the compositionality of measurement-based WCET estimation approaches","authors":"C. Maxim, A. Gogonel, I. Asavoae, Mihail Asavoae, L. Cucu-Grosjean","doi":"10.1145/3166227.3166230","DOIUrl":"https://doi.org/10.1145/3166227.3166230","url":null,"abstract":"The increased number of systems consisting of multiple interacting components imposes the evolution of timing analyses towards methods able to estimate the timing behavior of an entire system by aggregating timings bounds of its components. In this paper we propose the first discussion on the properties required by measurement-based timing analyses to ensure such compositionality. We identify the properties of reproducibility and representativity as necessary conditions to ensure the convergence of any measurement protocol allowing a compositional measurement-based timing analysis.","PeriodicalId":447904,"journal":{"name":"SIGBED Rev.","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133940053","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Several methods have been proposed for performing schedulability analysis for both uni-processor and multi-processor real-time systems. Very few of these works use the power of formal logic to write unambiguous specifications and to allow the usage of theorem provers for building the proofs of interest with greater correctness guarantees. In this paper we address this challenge by: 1) defining a formal language that allows to specify periodic resource models; 2) describe a transformational approach to reasoning about timing properties of resource models by transforming the latter specifications into a satisfiability modulo theories problem.
{"title":"SMT-based schedulability analysis using RMTL-∫","authors":"A. Pedro, David Pereira, L. M. Pinho, J. Pinto","doi":"10.1145/3166227.3166234","DOIUrl":"https://doi.org/10.1145/3166227.3166234","url":null,"abstract":"Several methods have been proposed for performing schedulability analysis for both uni-processor and multi-processor real-time systems. Very few of these works use the power of formal logic to write unambiguous specifications and to allow the usage of theorem provers for building the proofs of interest with greater correctness guarantees. In this paper we address this challenge by: 1) defining a formal language that allows to specify periodic resource models; 2) describe a transformational approach to reasoning about timing properties of resource models by transforming the latter specifications into a satisfiability modulo theories problem.","PeriodicalId":447904,"journal":{"name":"SIGBED Rev.","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121022162","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paperpresents a LazyDVS scheduling algorithm that offers higher acceptance ratio (number of tasks able to meet their deadline is to number of tasks appearing) with equivalent orlesser energy consumption for battery powered dynamic real time system. It is modeled for aperiodic workload by utilizing the concept of late start and dynamic voltage scaling. In this paper, with a motivational example we show that existing approaches have poor energy and aperiodic workload management, thus, are not suitable for scheduling aperiodic workload on limited source of energy. Based on this motivation we propose a Lazy DVS scheduling algorithm that tradeoffs between timing constraint and the available energy to provide better acceptance ratio with lower energy. The extensive examples and simulation results illustrate that our approach can effectively improve the acceptance ratio while consuming lower energy.
{"title":"A lazy DVS approach for dynamic real time system","authors":"S. Agrawal","doi":"10.1145/3015037.3015038","DOIUrl":"https://doi.org/10.1145/3015037.3015038","url":null,"abstract":"This paperpresents a LazyDVS scheduling algorithm that offers higher acceptance ratio (number of tasks able to meet their deadline is to number of tasks appearing) with equivalent orlesser energy consumption for battery powered dynamic real time system. It is modeled for aperiodic workload by utilizing the concept of late start and dynamic voltage scaling. In this paper, with a motivational example we show that existing approaches have poor energy and aperiodic workload management, thus, are not suitable for scheduling aperiodic workload on limited source of energy. Based on this motivation we propose a Lazy DVS scheduling algorithm that tradeoffs between timing constraint and the available energy to provide better acceptance ratio with lower energy. The extensive examples and simulation results illustrate that our approach can effectively improve the acceptance ratio while consuming lower energy.","PeriodicalId":447904,"journal":{"name":"SIGBED Rev.","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126916422","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper we are interested in mixed-criticality applications, which have functions with different timing requirements, i.e., hard real-time (HRT), soft real-time (SRT) and functions that are not time-critical (NC). The applications are implemented on distributed architectures that use the TTEthernet protocol for communication. TTEthernet supports three traffic classes: Time-Triggered (TT), where frames are transmitted based on static schedule tables; Rate Constrained (RC), for dynamic frames with a guaranteed bandwidth and bounded delays; and Best Effort (BE), for which no timing guarantees are provided. HRT messages have deadlines, whereas for SRT messages we capture the quality-of-service using "utility functions". Given the network topology, the set of application messages and their routing, we are interested to determine the traffic class of each message, such that all HRT messages are schedulable and the total utility for SRT messages is maximized. For the TT frames we decide their schedule tables, and for the RC frames we decide their bandwidth allocation. We propose aTabu Search-based metaheuristic to solve this optimization problem. The proposed approach has been evaluated using several benchmarks, including two realistic test cases.
{"title":"Traffic class assignment for mixed-criticality frames in TTEthernet","authors":"Voica Gavriluţ, P. Pop","doi":"10.1145/3015037.3015042","DOIUrl":"https://doi.org/10.1145/3015037.3015042","url":null,"abstract":"In this paper we are interested in mixed-criticality applications, which have functions with different timing requirements, i.e., hard real-time (HRT), soft real-time (SRT) and functions that are not time-critical (NC). The applications are implemented on distributed architectures that use the TTEthernet protocol for communication. TTEthernet supports three traffic classes: Time-Triggered (TT), where frames are transmitted based on static schedule tables; Rate Constrained (RC), for dynamic frames with a guaranteed bandwidth and bounded delays; and Best Effort (BE), for which no timing guarantees are provided. HRT messages have deadlines, whereas for SRT messages we capture the quality-of-service using \"utility functions\". Given the network topology, the set of application messages and their routing, we are interested to determine the traffic class of each message, such that all HRT messages are schedulable and the total utility for SRT messages is maximized. For the TT frames we decide their schedule tables, and for the RC frames we decide their bandwidth allocation. We propose aTabu Search-based metaheuristic to solve this optimization problem. The proposed approach has been evaluated using several benchmarks, including two realistic test cases.","PeriodicalId":447904,"journal":{"name":"SIGBED Rev.","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134279437","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The logical execution time (LET) model increases the compositionality of real-time task sets. Removal or addition of tasks does not influence the communication behavior of other tasks. In this work, we extend a multicore operating system running on a time-predictable multicore processor to support the LET model. For communication between tasks we use message passing on a time-predictable network-on-chip to avoid the bottleneck of shared memory. We report our experiences and present results on the costs in terms of memory and execution time.
{"title":"Support for the logical execution time model on a time-predictable multicore processor","authors":"Florian Kluge, Martin Schoeberl, T. Ungerer","doi":"10.1145/3015037.3015047","DOIUrl":"https://doi.org/10.1145/3015037.3015047","url":null,"abstract":"The logical execution time (LET) model increases the compositionality of real-time task sets. Removal or addition of tasks does not influence the communication behavior of other tasks. In this work, we extend a multicore operating system running on a time-predictable multicore processor to support the LET model. For communication between tasks we use message passing on a time-predictable network-on-chip to avoid the bottleneck of shared memory. We report our experiences and present results on the costs in terms of memory and execution time.","PeriodicalId":447904,"journal":{"name":"SIGBED Rev.","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132224336","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Time-triggered networks are widely used for safety-critical applications. Being offline scheduled, flexibility and adaptivity typically come at the price of very low resource utilization, if possible at all. In this paper, we present the Stacked Scheduling Approach (SSA) for time-triggered networks to enable mode changes and implicit adaptation in such networks by enabling reuse of network bandwidth reservations. We describe SSA in detail and conduct a case study to show that SSA can be implemented in COTS time-triggered network hardware and validate the approach by implementing an example in a COTS TTEthernet network.
{"title":"Mode-changes in COTS time-triggered network hardware without online reconfiguration","authors":"Florian Heilmann, Ali Syed, G. Fohler","doi":"10.1145/3015037.3015046","DOIUrl":"https://doi.org/10.1145/3015037.3015046","url":null,"abstract":"Time-triggered networks are widely used for safety-critical applications. Being offline scheduled, flexibility and adaptivity typically come at the price of very low resource utilization, if possible at all. In this paper, we present the Stacked Scheduling Approach (SSA) for time-triggered networks to enable mode changes and implicit adaptation in such networks by enabling reuse of network bandwidth reservations. We describe SSA in detail and conduct a case study to show that SSA can be implemented in COTS time-triggered network hardware and validate the approach by implementing an example in a COTS TTEthernet network.","PeriodicalId":447904,"journal":{"name":"SIGBED Rev.","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128669430","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Alexander Stegmeier, Jörg Mische, Martin Frieb, T. Ungerer
This paper applies several variants of application independent time-division multiplexing to MPI primitives and investigates their applicability for different scopes of communication. Thereby, the scopes are characterized by the size of the network-on-chip, the number of participating nodes and the message size sent to each receiver or received from each sender, respectively. The evaluation shows that none of the observed variants feature the lowest worst-case traversal time in all situations. Instead there are multiple schedule variants which each perform best in a different scope of communication parameters.
{"title":"WCTT bounds for MPI primitives in the PaterNoster NoC","authors":"Alexander Stegmeier, Jörg Mische, Martin Frieb, T. Ungerer","doi":"10.1145/3015037.3015041","DOIUrl":"https://doi.org/10.1145/3015037.3015041","url":null,"abstract":"This paper applies several variants of application independent time-division multiplexing to MPI primitives and investigates their applicability for different scopes of communication. Thereby, the scopes are characterized by the size of the network-on-chip, the number of participating nodes and the message size sent to each receiver or received from each sender, respectively. The evaluation shows that none of the observed variants feature the lowest worst-case traversal time in all situations. Instead there are multiple schedule variants which each perform best in a different scope of communication parameters.","PeriodicalId":447904,"journal":{"name":"SIGBED Rev.","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129580417","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Meng Liu, Matthias Becker, M. Behnam, Thomas Nolte
Network-on-Chip (NoC) is the interconnect of choice for many-core processors and system-on-chips in general. Most of the existing NoC designs focus on the performance with respect to average throughput, which makes them less applicable for real-time applications especially when applications have hard timing requirements on the worst-case scenarios. In this paper, we focus on a Round-Robin Arbitration (RRA) based wormhole-switched NoC which is a common architecture used in most of the existing implementations. We propose a novel segmentation algorithm targeting RRA-based NoCs in order to improve the schedulability of real-time traffic without modifying the hardware architecture. According to the evaluation results, the proposed segmentation solution can significantly improve the schedulability of the whole network.
{"title":"Using segmentation to improve schedulability of real-time traffic over RRA-based NoCs","authors":"Meng Liu, Matthias Becker, M. Behnam, Thomas Nolte","doi":"10.1145/3015037.3015040","DOIUrl":"https://doi.org/10.1145/3015037.3015040","url":null,"abstract":"Network-on-Chip (NoC) is the interconnect of choice for many-core processors and system-on-chips in general. Most of the existing NoC designs focus on the performance with respect to average throughput, which makes them less applicable for real-time applications especially when applications have hard timing requirements on the worst-case scenarios. In this paper, we focus on a Round-Robin Arbitration (RRA) based wormhole-switched NoC which is a common architecture used in most of the existing implementations. We propose a novel segmentation algorithm targeting RRA-based NoCs in order to improve the schedulability of real-time traffic without modifying the hardware architecture. According to the evaluation results, the proposed segmentation solution can significantly improve the schedulability of the whole network.","PeriodicalId":447904,"journal":{"name":"SIGBED Rev.","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132620403","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, we explore a new approach for the security of flow transmission in a Network-on-Chip. This approach is based on a dual mixed criticality approach where the criticality of a flow (HI or LO) is associated to timeliness and security constraints on flow transmission. Flow of HI criticality should be protected from Denial of Service (DoS) and side channel attacks while LO flows are assumed to be non secured. We propose a solution to detect abnormal flow profiles in a Network-on-Chip, that can result from a security attack and we provide a mixed criticality approach to mitigate the impact of an attack. This is done by switching the nodes of a Network-on-Chip subject to a security attack from LO to HI criticality and taking protection measures in HI mode to contain the security attack. Our solution relies on a mechanism, configured and managed by a hypervisor applied in all IPs connected to the Network-on-Chip.
{"title":"A mixed criticality approach for the security of critical flows in a network-on-chip","authors":"Ermis Papastefanakis, Xiaoting Li, L. George","doi":"10.1145/3015037.3015048","DOIUrl":"https://doi.org/10.1145/3015037.3015048","url":null,"abstract":"In this paper, we explore a new approach for the security of flow transmission in a Network-on-Chip. This approach is based on a dual mixed criticality approach where the criticality of a flow (HI or LO) is associated to timeliness and security constraints on flow transmission. Flow of HI criticality should be protected from Denial of Service (DoS) and side channel attacks while LO flows are assumed to be non secured. We propose a solution to detect abnormal flow profiles in a Network-on-Chip, that can result from a security attack and we provide a mixed criticality approach to mitigate the impact of an attack. This is done by switching the nodes of a Network-on-Chip subject to a security attack from LO to HI criticality and taking protection measures in HI mode to contain the security attack. Our solution relies on a mechanism, configured and managed by a hypervisor applied in all IPs connected to the Network-on-Chip.","PeriodicalId":447904,"journal":{"name":"SIGBED Rev.","volume":"191 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123388759","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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