Journal of Electronic Testing最新文献

A universal number (Unum) is a number representation format that can reduce the memory contention issues in multicore processors and parallel computing systems by optimizing the bit storage in the arithmetic operations. Given the safety-critical nature of applications of Unum format, there is a dire need to rigorously assess the correctness of the Unum based arithmetic operations. Unums are of three types, namely, Unum-I, Unum-II and Unum-III (commonly known as Posits). In this paper, we provide a higher-order-logic formalization of Unum-III (posits). In particular, we formally model a posit format (binary encoding of a posit), which is comprised of the sign, exponent, regime and fraction bits, using the HOL Light theorem prover. In order to prove the correctness of a posit format, we formally verify various properties regarding conversions of a real number to a posit and a posit to a real number and the scaling factors of the regime, exponent and fraction bits of a posit using HOL Light.

Hardware Trojans (HT) are tiny circuits designed to exploit electronic devices, posing risks such as device malfunction or leakage of sensitive information. The adversary aims to implant these HTs specifically targeting nets with minimal signal transition (rare gates) within a circuit, evading detection during functional tests. Some Trojan variants are activated by adversaries under specific periodic conditions. Logic testing, a well-established method for test generation in HT detection, faces challenges due to the impractical scale of the search space, whereas Genetic Algorithms (GA) excel in efficiently navigating extensive solution spaces. This paper presents a GA-based technique that integrates information on effective inputs, along with an adequate fitness function defined based on combinational controllability and structural features, for detecting conditionally triggered ultrasmall HTs. Upon assessing the ITC 99 and ISCAS 85 and 89 benchmarks, we note significant enhancements in trigger coverage and reduced run-time requirements in comparison to state-of-the-art methods like MERO and TRIAGE.

Test Case Generation (TCG) generates various types of tests, including functional tests, performance tests, security tests, and reliability tests to ensure software quality, while Test Case Prioritization (TCP) prioritizes the generated tests. However, the previous studies had challenges, including resource constraints, detecting crucial requirements, and automating the Test Case (TC) process efficiently. Additionally, the process is costlier and takes a maximum time duration that affects the effective performance. Therefore, an effective framework is proposed to overcome such issues by optimizing TCG and TCP processes effectively. The proposed work starts with the generation of a Unified Modeling Language (UML) diagram from historical project source code, which is then converted into a Comma-Separated Value (CSV) format. Then, the feature extraction is performed on this CSV file, followed by optimal TCG using the Entropy-based Locust Swarm Optimization Algorithm (Ent-LSOA). Additionally, factors are extracted and reduced from the historical project source code using Pearson Correlation Coefficient-Generalized Discriminant Analysis (PCC-GDA). Finally, the optimal TCs and selected factors are prioritized with the highest accuracy and recall of 96.89% and 96.92%, respectively using an Interpolated Multiple Time scale Recurrent Neural Network (IMTRNN). Thus, the proposed work outperformed the existing techniques by providing an efficient solution for TCG and TCP in software testing.

This paper studies the fault propagation and the correctness rate calculation of combinatorial circuits. We rely on circuit partitioning and on a probabilistic approach close to a binomial distribution, assuming some simultaneous faults have a certain probability to occur in the circuit’s gates. We extend the results of our Clusterized Probabilistic Binomial Reliability model (CPBR), in which we obtained the results for several combinatorial multiplier designs, as seen in our previous publication. We now target non-arithmetic combinatorial netlists and, among them, a few circuits with flip-flop instances. We use the graph representation of the combinatorial netlists and we generalize our approach with a generic algorithm for CPBR. To develop this algorithm, we use some existing work on multilevel acyclic hypergraph partitioning, that we adapt to acyclic directed graphs. Furthermore, we address the problem of calculating correctness rates of circuits in cases where sequential flip-flops induce cycles in the graph. Our experiments show that our approach is capable of analysing the error and the correctness rates of significant non-arithmetic circuits, with an automatized and generic tool.

The present article proposes a novel method to reduce phase noise in a PLL based X-Band source consisting of oscillating and non-oscillating components for the use in Pulse Doppler radar. It also provides phase noise performance stabilization under random vibration. The method consists of improved electrical design and PCB layout, noise filtering technique and passive isolation scheme to suppress vibration-induced noise. Acceleration sensitivity is an important requirement for radars and sensors mounted in unmanned aerial vehicles, aircrafts, missiles and other dynamic platforms. These systems provide superior performance when subjected to severe environmental condition. However, mechanical vibration and acceleration can introduce physical deformation that thereby degrades the frequency source generated signal phase noise. It effects the complete radar system that depends on frequency source performance. The development and testing of a stable X-Band source at 10.64 GHz using indirect method has been carried out which proved that the phase noise is stable both in steady state and under random vibration of 7g magnitude. The study of critical design aspects of test fixture, test object mounting arrangement, investigation on vibration response and performance stabilization along with description of test setup and measurement procedure has been reported. An improvement of around 35-40 dB in phase noise is achieved at close-in offset frequencies. Few challenges and suggestions for the accurate measurement of random vibration testing for frequency sources have also been mentioned.

A radiation-hardened-by-design (RHBD) current-starved-ring voltage-controlled oscillator (CSR-VCO) design is proposed based on the separation of gate input technique to mitigate single event effects (SEEs) for phase-locked loop (PLL) implementation. A double-exponential (DE) current model is used to analyze the effect of single event transient (SET) at the output of the proposed RHBD CSR-VCO. The proposed RHBD CSR-VCO is implemented in United Microelectronics Corporation (UMC) 65 nm CMOS technology and a 71.6% improvement is achieved in phase displacement as compared to conventional VCO. The oscillation frequency of 1.75 GHz is obtained for the proposed RHBD CSR-VCO with a tuning range from 0.40 GHz to 2.23 GHz and power dissipation of 1.368 mW. The proposed RHBD CSR-VCO is protected against radiation with deposited charges up to 1050 fC and achieved a higher figure-of-merit (FOM) when compared to the recently reported VCOs and PLLs. This shows that even in a radiation-prone environment, the RHBD PLL can achieve excellent performance and be employed successfully in low-power, high-speed communication applications.

Fault diagnosis of analog circuits is a classical problem, and its difficulty lies in the similarity between fault features. To address the issue, an end-to-end mutually exclusive autoencoder (EEMEAE) fault diagnosis method for analog circuits is proposed. In order to make full use of the advantages of Fourier transform(FT) and wavelet packet transform(WPT) for extracting signal features, the original signals processed by FT and WPT are fed into two autoencoders respectively. The hidden layers of the autoencoders are mutually exclusive by Euclidean distance restriction. And the reconstruction layer is replaced by a softmax layer and 1-norm combined with cross-entropy that can effectively enhance the discriminability of features. Finally, the learning rate is adjusted adaptively by the difference of loss function to further improve the convergence speed and diagnostic performance of the model. The proposed method is verified by the simulation circuit and actual circuit and the experimental results illustrate that it is effective.

Integrated circuit (IC) testing presents complex problems that for large circuits are exceptionally difficult to solve by traditional computing techniques. To deal with unmanageable time complexity, engineers often rely on human “hunches" and “heuristics" learned through experience. Training computers to adopt these human skills is referred to as machine intelligence (MI) or machine learning (ML). This survey examines applications of such methods to test analog, radio frequency (RF), digital, and memory circuits. It also summarizes ML applications to hardware security and emerging technologies, highlighting challenges and potential research directions. The present work is an extension of a recent paper from IEEE VLSI Test Symposium (VTS’21), and includes recent applications of artificial neural network (ANN) and principal component analysis (PCA) to automatic test pattern generation (ATPG).

Software is playing a growing role in many safety-critical applications, and software systems dependability is a major concern. Predicting faulty modules of software before the testing phase is one method for enhancing software reliability. The ability to predict and identify the faulty modules of software can lower software testing costs. Machine learning algorithms can be used to solve software fault prediction problem. Identifying the faulty modules of software with the maximum accuracy, precision, and performance are the main objectives of this study. A hybrid method combining the autoencoder and the K-means algorithm is utilized in this paper to develop a software fault predictor. The autoencoder algorithm, as a preprocessor, is used to select the effective attributes of the training dataset and consequently to reduce its size. Using an autoencoder with the K-means clustering method results in lower clustering error and time. Tests conducted on the standard NASA PROMIS data sets demonstrate that by removing the inefficient elements from the training data set, the proposed fault predictor has increased accuracy (96%) and precision (93%). The recall criteria provided by the proposed method is about 87%. Also, reducing the time necessary to create the software fault predictor is the other merit of this study.

As the central control component in aerospace products, SRAM-based FPGA finds extensive application in space. In its operational context, the space radiation environment introduces single event effect (SEE) and space electrostatic discharge effect (SESD) in FPGAs. This paper investigates SEE and SESD in SRAM-based FPGA using an integrated simulation method that combines device-level and circuit-level analyses. The findings reveal that the distinction in signal transmission primarily lies in the number of upsets and their correlation with the initial state. SEE can lead to single-bit or multi-bit upsets in SRAM, while SESD typically induces multi-bit upsets (MBU) in SRAM. Furthermore, the logic upset caused by SEE exhibits almost no correlation with the initial state of SRAM. Conversely, the upset caused by SESD is linked to the initial state, and the threshold voltage of Single Event Upsets (SEU) in different initial states is not uniform.