Journal of Electronic Testing最新文献

Abstract

A faulty Through Silicon Via (TSV) could spoil a 3D IC and cause hefty loss as the potentially expensive known-good-dies bonded together must be discarded. This work presents a Fault-tolerant TSV scheme to avoid such a disastrous situation. Our method uses two differential TSVs for each binary signal to be transmitted. Compared to the previous Fault-tolerant TSV schemes, our test and repair scheme is not only instant and much more simplified, requiring no global test result analysis and complex reconfiguration process, thereby making it especially suitable for some situations when the more involved TSV test and repair schemes cannot be easily supported by some die providers in multi-vendor 3D-IC design environment.

With feature size scaling down, the effect of single event transient (SET) on the reliability of circuits is necessary to be considered. The bipolar amplification effect plays a key role in the charge collection of SET of nano-meter FinFET devices. It is important taking into account the bipolar amplification to calculate deposited charge, which is always obtained by a linear model dependency on linear energy transfer (LET) and silicon film thickness. Based on radiation-induced generation rate model and genetic arithmetic, an accurate analytical for the deposited charge of SET in FinFET is proposed. The effects of LET, volume of particle hit, characteristic radius and decay time of Gaussian function on the deposited charge are analyzed by the proposed model. The dependence of the device structure on the deposited charge is also discussed by the model. The results indicate that the presented model agrees with TCAD well. Compared with TCAD, the proposed model has an average relative error 0.002% while the linear model has an average relative error 50.5% for LET ranging from 3 to 110 MeV·cm²/mg. Due to large sensitive volume of the particle hit in source and drain areas, the deposited charge has two maxima in source and drain areas and a minimum round the gate-drain junction of fin. The deposited charge increases with the characteristic radius and decay time decrease and the relative error between TCAD and the proposed model represent a reduction trend.

Abstract

Memristive devices have become promising candidates to complement the CMOS technology, due to their CMOS manufacturing process compatibility, zero standby power consumption, high scalability, as well as their capability to implement high-density memories and new computing paradigms. Despite these advantages, memristive devices are susceptible to manufacturing defects that may cause faulty behaviors not observed in CMOS technology, significantly increasing the challenge of testing these novel devices after manufacturing. This work proposes an optimized Design-for-Testability (DfT) strategy based on the introduction of a DfT circuitry that measures the current consumption of Resistive Random Access Memory (ReRAM) cells to detect not only traditional but also unique faults. The new DfT circuitry was validated using a case study composed of a 3x3 word-based ReRAM with peripheral circuitry implemented based on a 130 nm Predictive Technology Model (PTM) library. The obtained results demonstrate the fault detection capability of the proposed strategy with respect to traditional and unique faults. In addition, this paper evaluates the impact related to the DfT circuitry’s introduced overheads as well as the impact of process variation on the resolution of the proposed DfT circuitry.

Ensuring the reliability of GPUs and their internal components is paramount, especially in safety-critical domains like autonomous machines and self-driving cars. These cutting-edge applications heavily rely on GPUs to implement complex algorithms due to their implicit programming flexibility and parallelism, which is crucial for efficient operation. However, as integration technologies advance, there is a growing concern regarding the potential increase in fault sensitivity of the internal components of current GPU generations. In particular, Special Function Unit (SFU) cores inside GPUs are used in multimedia, High-Performance Computing, and neural network training. Despite their frequent usage and critical role in several domains, reliability evaluations on SFUs and the development of effective mitigation solutions have yet to be studied and remain unexplored. This work evaluates the impact of transient faults in the main hardware structures of SFUs in GPUs. In addition, we analyze the main overhead costs and benefits of developing selective-hardening mechanisms for SFUs. We focus on evaluating and analyzing two SFU architectures for GPUs (’fused’ and ’modular’) and their relations to energy, area, and reliability impact on parallel applications. The experiments resort to fine-grain fault injection campaigns on an RTL GPU model (FlexGripPlus) instrumented with both SFUs. The results on both SFU architectures indicate that fused SFUs (in commercial-grade devices) require lower area overhead (about 27%) for their integration in GPUs but are more vulnerable to transient faults (in up to 47% for the analyzed cases) and less power efficient (in up to 36.6%) than modular SFUs. Moreover, the reliability estimation shows that Modular SFUs are structurally more resilient than Fused ones in up to one order of magnitude. Similarly, selective-hardening mechanism based on Triple-Modular Redundancy (TMR) shows that coarse-grain strategies might increase the reliability of the overall SFUs under feasible overhead costs.

In modern chip designs, shared resources are used extensively. Arbiters usage is crucial to settle conflicts when multiple requests compete for these shared resources. Making sure these arbiter circuits work correctly is vital not just for their proper functionality, but also for security reasons. The work in this paper introduces a method based on formal verification to thoroughly assess the proper functional aspects of various arbiter setups. This is achieved through SystemVerilog assertions and model checking. Additionally, we explore a non-invasive method for the modeling and insertion of different types of hardware Trojans. These Trojans, with their unique triggers and payloads, are modeled formally without the need for any alterations to the actual circuit. The results provide a detailed analysis of the cost involved in running the formal verification environment on versions of arbiters that are free from Trojans. This analysis is carried out using Questa PropCheck formal analysis tool, which offers valuable insights into the time and memory resources required. Furthermore, the results highlights how the formally modeled and inserted Trojans interfere with hold criteria of the arbiters’ properties, where at least a single property fires due to the inserted Trojan. This work can be extended to be a generic approach with the potential to validate both the proper operation and security aspects of complex systems.

Abstract

Biological assays around “lab-on-a-chip (LoC)” are required in multiple concentration (or dilution) factors, satisfying specific sample concentrations. Unfortunately, most of them suffer from non-locality and are non-protectable, requiring a large footprint and high purchase cost. A digital geometric technique can generate arbitrary gradient profiles for digital microfluidic biochips (DMFBs). A next- generation DMFB has been proposed based on the microelectrode-dot-array (MEDA) architectures are shown to produce and disperse droplets by channel dispensing and lamination mixing. Prior work in this area must address the problem of reactant and waste minimization and concurrent sample preparation for multiple target concentrations. This paper proposes the first splitting-droplet sharing algorithm for reactant and waste minimization of multiple target concentrations on MEDAs. The proposed algorithm not only minimizes the consumption of reagents but also reduces the number of waste droplets by preparing the target concentrations concurrently. Experimental results on a sequence of exponential gradients are presented in support of the proposed method and demonstrate its effectiveness and efficiency. Compared to prior work, the proposed algorithm can achieve up to a 24.8% reduction in sample usage and reach an average of 50% reduction in waste droplets.

With the development of semiconductor technology, the shrinking of feature size in integrated circuits has made them more sensitive to multiple-node-upsets (MNUs). Researchers have proposed various circuit-hardened methods, such as hardened latches, to address this issue. Currently, the reliability verification of latches relies on complex EDA tools, such as HSPICE, Cadence Virtuoso, and other tools for error injection. Therefore, this article proposes a high-performance quadruple-node-upset (QNU) tolerant latch design, called the HQNUT latch, based on 32 nm CMOS technology. Additionally, an algorithm-based latch verification process is proposed to enhance the efficiency and reliability of latch verification. This approach enables a fast and accurate assessment of the latch’s fault-tolerant capability. Due to clock gating technology and high-speed path technology, HQNUT’s power consumption and delay are reduced. Simulation results show that the proposed algorithm can certify the soft-error-tolerability of hardened Latches. Compared with existing QNU-tolerable hardened latches, the proposed latch reduced power consumption, area, delay, and power-delay product (PDP) by about 36.9%, 5.6%, 19.8%, and 46.4%, respectively.

Abstract

The recent expansion of the Internet of Things (IoT) owes a lot to the significant contribution of the 6LoWPAN protocol, which has been extensively employed in low-power and lossy networks. To facilitate communication in 6LoWPAN networks, the Internet Engineering Task Force (IETF) has suggested the usage of the Routing Protocol for Low-Power and Lossy Networks (RPL). Despite its usefulness, the open and restricted nature of the RPL protocol renders it susceptible to both internal and external attacks. Since IoT devices connected through the RPL protocol have limited resources like processing power, battery life, memory, and bandwidth, ensuring their security is of the utmost importance. One of the primary obstacles to IoT networks is RPL routing attacks, which disrupt the network's normal routing activities and structure. This study investigates the impact of five RPL routing attacks, namely Blackhole, Sybil, Selective Forwarding (SF), Sinkhole, DIO suppression, and DIS flooding, on the IoT networks’ performance. The study evaluated the network's performance for normal and five routing attack scenarios using numerous performance metrics including Link throughput, No. of packets generated (control and data), Sensor data throughput, Packet Delivery Ratio (PDR), and Delay in packet delivery. This work conducted simulations using the Tetcos NetSim v12.1 IoT network simulator tool and is the first to analyze IoT network performance under multiple routing assault scenarios with various performance measures. The analysis showed that the performance metrics of PDR, Sensor data throughput, and No. of data packets transmitted decreased significantly in attack scenarios compared to the normal scenario, with an average decreased percentage of 70%, 70%, and 39.4%, respectively. In contrast, the metrics Link throughput, Delay, and No. of control packets transmitted increased in attack scenarios compared to the normal scenario, with average values supplemented by a factor of 35, 255, and 36, respectively. Additionally, the Destination-Oriented Directed Acyclic Graph (DODAG) real-time formation under different scenarios was provided.

This work studies radiation-induced effects in FinFET technology, the leading technology in advanced nodes for high-end embedded systems. As the fin height (HFIN) and the number of fins (NFIN) are two critical parameters in the development of newer technologies, the soft-error robustness to radiation-induced effects in FinFET SRAM cells with HFIN and NFIN) is evaluated using Technology Computer-Aided Design (TCAD) tools. The ion strike direction and the process variations are considered. An analytical method to evaluate the failure probability of the memory cell due to radiation-induced effects under process variations is proposed. The amount of critical and collected charges of the memory cell are obtained with TCAD tools. The proposed method can be used to get insight into the robustness behavior of the memory cell with HFIN and NFIN and to guide the obtention of HFIN and NFIN parameters in developing new FinFET technologies.