Journal of Electronic Testing最新文献

With the continuous scaling of CMOS technology, single-event multi-node upsets (MNU) induced by charge sharing has continued to occur in latches when hit by high-energy particles. This paper presents a quadruple-node upset (QNU) tolerant latch design (referred to as P-DICE latch) to achieve both high reliability and low area overhead. The P-DICE latch takes advantage of the error-blocking properties of Cross-Coupled Element and C Element to tolerate QNU, and achieves 100% self-recovery of SNU and DNU. Compared with previous eight MNU hardened latches, the P-DICE latch has the lowest overhead in terms of area, area-power-delay product (APDP), and area-power-delay soft error rate ratio product (APDSP), and has the highest critical charge. Moreover, the proposed P-DICE latch can tolerate QNU caused by high-energy particles to ensure the reliability of the circuit. Compared with eight MNU hardened latches, the proposed P-DICE latch achieves 24.58% reduction in area, 33.05% reduction in power, 17.19% reduction in delay, 48.29% reduction in area-power-delay product, 61.60% reduction in APDSP, and 142.82% improvement in critical charge on average.

The increasing multi-core system complexity with technology scaling introduces new constraints and challenges to interconnection network design. Consequently, the research community has a converging trend toward an asynchronous design paradigm for Network-on-Chip (NoC) architecture as a promising solution to these challenges. This paper addresses the design and functional verification aspects of an asynchronous NoC router microarchitecture for a Globally Asynchronous Locally Synchronous (GALS) system. Firstly, the paper introduces a novel mixed-level abstract simulation approach for faster functional verification of the asynchronous architecture using the commercially available Spectre Analog and mixed-signal simulation (AMS) Designer tool. This simulation methodology intends to ensure the feasibility of the design and identify shortcomings, if any, before the subsequent implementation stages of the design. Also, the paper proposes a new baseline asynchronous router built on a domino logic pipeline template with a novel hybrid encoding scheme. The new hybrid encoding scheme facilitates simple architecture with no additional timing constraints. The proposed verification methodology evaluates the baseline asynchronous router’s functional verification in Cadence’s AMS designer tool. Preliminary simulation results conform to the objectives of the paper. Further, the same verification setup establishes the design validation in subsequent stages of the design implementation.

In this paper, the reliability of copper pillar micro-bump under random vibration is investigated. Three kinds of copper pillar solder joints with different morphologies were obtained by changing the hot press bonding process, and the random vibration fatigue simulation of flip-flop interconnect solder joints was carried out by using Ansys to obtain the stress–strain distribution law of the solder joints and predict the vibration fatigue life of the solder joints. It is found that the outermost solder joints of flip-flop bonding are most likely to fail; the fatigue life of copper pillar solder joints is predicted based on the three interval method, the Miner linear cumulative damage criterion and the high cycle fatigue formula; reliability experiments are conducted, and it is found that the drum solder joints are most prone to cracking, followed by hourglass and columnar shapes and that all cracks are caused by the substrate side of copper pillar. Cracks are sprouted from the contact surface between the copper pillar and solder on the substrate side and expand internally in the intermetallic compound (IMC) layer, while the presence of voids aggravates the generation of cracks.

The lifecycles of vehicular resistor lead in random vibration environment were analyzed in this technical note and the finite element model of a vehicular printed circuit board (PCB) was established. It is with two short edges of PCB fixed for boundary condition to simulate the actual working conditions of the vehicle driving on the road, the constrained modal analysis was simulated and experimental verification were carried out. Both the PCB and the vehicular resistor which soldered on PCB were excited vertically according to Standard GJB150. Based on simulated vibration excitation environment, the power spectral density (PSD) stress value of the resistor lead was calculated. The lifecycles of the resistor lead were calculated theoretically and were verified by following failure-oriented accelerated testing (FOAT). Finally, in order to extend the lifecycles of resistor lead, an improved solution for PCB is put forward.

A Phase-Locked Loop (PLL) is indispensable in producing high-speed on-chip clock signals in an IC. For safety–critical applications, fault and soft-error tolerance are often desirable. However, how to achieve this goal for a PLL is still a challenge. In this paper, we address this challenge with a TMR-based FET-PLL design. Our unique contribution is a “synchronization-before-voting” scheme so that the fault and soft-error tolerance and the jitter performance can be maintained at the same time. Post-layout simulation using a 90 nm CMOS process demonstrates that our PLL can indeed withstand the attack of online faults as well as soft errors without suffering from significant jitter performance loss.

The quantity of bugs that a software test-data finds determines its effectiveness. A useful technique for assessing the efficacy of a test set is mutation testing. The primary issues with the mutation test are cost and time requirements. Close to 40% of the injected bugs in the mutation test are effect-less (equivalent). Reducing the number of generated total mutants by decreasing equivalent mutants and reducing the execution time of the mutation test are the main objectives of this study. An error-propagation aware mutation test approach has been suggested in this research. Three steps make up the process. To find a collection of instruction-level characteristics effective on the error propagation rate, the data and instructions of the input program were evaluated in the first step. Utilizing supervised machine learning techniques, an instruction classifier was developed using the prepared dataset in the second step. After classifying the program instructions automatically by the created classifier, the mutation test is performed only on the identified error-propagating instructions; the identified non-error-propagating instructions are avoided to mutate in the proposed mutation testing. The conducted experiments on the set of standard benchmark programs indicate that the proposed method causes about 19% reduction in the number of generated mutants. Furthermore, the proposed method causes a 32.24% reduction in the live mutants. It should be noted that the proposed method eliminated only the affectless mutants. The key technical benefit of the suggested solution is that mutation of the instructions that don't propagate errors is avoided. These findings can lead to a performance improvement in the existing mutation-test methods and tools.

Fault tolerant adders are an important design paradigm to improve the robustness of the adder while at the same time improving the yield. The major downside of fault tolerant adders are the additional modules that are intrinsic to this design. On the other hand, approximate adders take the advantage of computing resilience and inherently improve the area, delay & power metrics. A combination of these two seemingly contradictory approaches are juxtaposed to put forth a design for robust fault tolerant approximate adders that mitigate the effects of redundancy and would help improve the yield. The fault tolerant schemes included are the Triple Modular Redundancy and Partial Triple Modular Redundancy. These are used in conjunction with the approximate Lower part-OR Adder (LOA). The designed fault tolerant approximate adder along with the fault intolerant precise and fault intolerant imprecise adder is used for image sharpening using the Gaussian filter. The results analyzed in the presence and absence of faults indicate that the visual quality of the image in the presence of a single stuck-at fault is almost as good as that obtained without a fault and maintains a PSNR of above 27 in case of fault tolerant approximate adder. There is a significant loss in the image quality if a fault occurs in a non-redundant precise or approximate adder. The deterioration in image quality is more significant if a stuck-at-one fault occurs, as the image becomes visually indecipherable.

Since 2007, methods that utilize side-channel data to detect hardware Trojan (HT) problems have been widely studied. Machine learning methods are widely used for hardware Trojan detection, but with the development of integrated circuits (ICs), better results are usually obtained using deep learning methods. In this paper, we propose an architecture inspired by Residual-Block and Dense-Block and combine it with SE Attention Mechanism, which we named the Res-Dense-SE-Net network. By combining residual connectivity, dense connectivity, and attention mechanism, the Res-Dense-SE-Net network can enjoy the advantages of these three network architectures at the same time, which can improve the expressiveness and performance of the model. The Res-Dense-SE-Net network can capture the key features in the image better, and it can solve the problems of gradient vanishing and feature transfer efficiently, which can in turn improve the classification accuracy and the generalization ability of the model. Based on the publicly available AES series of hardware Trojans from TrustHub and the publicly available hardware Trojan-side channel data by Faezi et al., we evaluate the effectiveness of the method proposed in this paper. The experimental results show that when a single Trojan exists, the method proposed in this paper has a high accuracy rate; and when multiple types of hardware Trojans exist at the same time and need to be categorized, the categories of hardware Trojans can also be effectively identified, and the categorization accuracy is high compared with the existing deep learning methods.