International Journal of Numerical Modelling-Electronic Networks Devices and Fields最新文献

In this manuscript, a new indirect internal model control (IMC)-based proportional-integral-derivative (PID) controller is designed for stable, integral, and unstable processes with time delay. A zero relative order (ZRO)–IMC filter is introduced, which acts as a lead compensator, enhancing the controller's performance. The proposed method ensures a higher phase margin and improves transient performance. The tuning method allows flexibility in changing system robustness by adjusting the value of the proposed tuning variable $��\left(p\right)�$, resulting in good set-point tracking and disturbance rejection. This tuning parameter has a monotonous relationship with system robustness within the specified range. The efficacy of the proposed tuning method is validated through simulation studies and an experimental case study on a DC motor for speed control, and the results are compared with existing IMC-PID controllers.

In this article, a particle swarm optimization algorithm with dynamic variable hyperparameter is proposed and applied to the optimization design of a wideband asymmetric Doherty power amplifier (DPA). Compared with the optimization algorithm in the common electronic design automation software and the traditional PSO algorithm, the proposed algorithm has stronger convergence and higher optimization performance. The test results show that in the operating frequency band of 1.5–2.2 GHz, the saturation output power (Pout) reaches 43.9–45.1 dBm, and the saturation drain efficiency (DE) reaches 60.3%–64.9%. Additionally, the DE can reach 48%–56% when the back-off is greater than 9 dB. An evaluation of linearity and digital predistortion has also been conducted under the excitation of a 20-MHz 5G new radio (NR) signal. For this DPA, excellent linearity is demonstrated.

Power amplifiers (PAs) in mobile handsets are sensitive to changes in antenna impedance, thus suffering from load mismatch and generating complicated nonlinear distortion frequently. To solve this issue, a complexity-reduced time domain poly-harmonic distortion (CR-TD-PHD) model is proposed for the digital predistortion (DPD) linearization of handset PAs with load mismatch. By implementing a set of modified dual-input magnitude-selective affine (MSA) functions, the proposed CR-TD-PHD model can describe the inter-modulation terms of the input signal and reflection signal accurately while avoiding the use of high-order polynomial functions. Experimental tests are carried out on a load-mismatched PA with a 100-MHz 5G NR signal, and the results demonstrate that the proposed CR-TD-PHD model not only successfully reduces the complexity but also retains high linearization accuracy.

This work proposes three configurations of memcapacitor emulators based on operational amplifiers. The first two configurations utilize two operational amplifiers, three memristors, one resistor, and one capacitor. The third configuration requires two operational amplifiers, one capacitor, one memristor, and three resistors for its realization. The key innovation of the proposed circuits lies in integrating a memristor, which introduces non-linearity and memory capabilities, making it ideal for emulating memcapacitive behavior. The proposed circuits demonstrate simplified structures compared to most existing designs while achieving reliable performance across a frequency range of up to 6 kHz. The LTspice tool has been utilized to perform all simulations. The pinched hysteresis loops are plotted to validate the memcapacitive behavior, the memory-retaining property is evaluated using a non-volatile plot, and robustness is verified by performing the Monte Carlo simulations. The proposed emulators are validated utilizing both the SPICE model of the memristor and a memristor emulator circuit. Experimental results have been included to validate the key fingerprint, that is, pinched hysteresis loop of the circuit using commercially available AD711 ICs. Additionally, three applications—neural spike generation, adaptive learning circuit, and chaotic oscillator—are demonstrated, highlighting the emulator's versatility in neuromorphic computing and adaptive systems.

This report presents a performance comparison between two types of β-Ga₂O₃-based high electron mobility transistors (BGO-HEMTs), where channel doping is achieved through either polarization-induced doping (PID) or delta-doped (DD) modulation doping. The study evaluates and contrasts the performance characteristics of these two types of BGO-HEMTs. Using an optical phonon model to capture enhanced electron–phonon interactions in wide bandgap semiconductors, the maximum current density is estimated in both devices. Highly polarized AlN employed as barrier layers in PID BGO-HEMTs results in significantly higher conduction band offsets, thus achieving an order of magnitude higher sheet carrier density compared to DD BGO-HEMTs. Higher 2-DEG density ensures 2.5× higher current density and one order lower on-resistance in PID over DD BGO-HEMTs. Furthermore, PID BGO-HEMTs outperform as DC switches and require 13× lower gate periphery compared to DD BGO-HEMTs for the equal power rating. In addition, AlN as a gate barrier in PID BGO-HEMTs facilitates better thermal conductivity over DD BGO-HEMTs. The achieved results show the potential of PID β-Ga₂O₃ HEMTs for emerging DC power switching and compact high-power RF electronics applications.

This paper introduces a novel multilayer neural network technique to solve partial differential equations with non-integer derivatives (FPDEs). The proposed model is a deep feed-forward multiple layer neural network (DFMLNN) that is trained using advanced optimization approaches, namely adaptive moment estimation (Adam) and limited-memory Broyden-Fletcher-Goldfarb-Shanno (L-BFGS), which integrate neural networks. First, the Adam method is employed for training, and then the model is further improved using L-BFGS. The Laplace transform is used, concentrating on the Caputo fractional derivative, to approximate the FPDE. The efficacy of this strategy is confirmed through rigorous testing, which involves making predictions and comparing the outcomes with exact solutions. The results illustrate that this combined approach greatly improves both precision and effectiveness. This proposed multilayer neural network offers a robust and reliable framework for solving FPDEs.

The simulation of nanotransistors and the inclusion of all relevant physics is a challenging task, especially when working with one-dimensional (1D) nanomaterials in which quantum confinement strongly influences the material properties and device performance. Several groups have already developed state-of-the-art quantum transport simulators based on the first principles non-equilibrium Green's function (NEGF) formalism, and a few have been commercialized. However, these tools are computationally demanding as they require solving the NEGF and the 3D Poisson equation. Here we present an open-source quantum-transport solver for the first principles device engineering for nanoelectronics (QUDEN) implemented in Matlab. QUDEN uses NEGF and the ballistic top-of-the-barrier model to simulate ultrascaled field-effect transistors (FETs) with channels made of nanoribbons of 2D materials, while the device Hamiltonian is obtained using first principles density functional theory (DFT) in combination with maximally localized Wannier functions (MLWFs). This approach preserves the accuracy of the full NEGF-3D Poisson simulation in the on-state while using a simplified self-consistent electrostatics that leads to a much lower computational burden. Taking monolayer germanium-selenide (GeSe) nanoribbons as an example, we show that QUDEN can be used for fast screening and accurate evaluation of numerous 2D/1D materials for future FETs.

Growing concerns about electromagnetic radiation from communication technologies such as 5G have prompted a search for effective microwave-absorbing materials to mitigate potential health risks. This study focuses on the development of Fe-based amorphous/nanocrystalline alloys as microwave absorbers, with specific emphasis on achieving cost-effectiveness, reduced thickness, and superior absorption capabilities. FePC alloy powders, treated through thermal annealing and ball milling (synergistic processing), exhibit enhanced saturation magnetization and superior microwave absorption properties. The powders, with small particle sizes and high surface areas, demonstrate excellent absorption, achieving a minimum reflection loss (RL) of −30.1 dB at 12.8 GHz with a 5.3 GHz absorption bandwidth at 2 mm thickness. The results highlight the promising potential of these materials for practical applications in reducing electromagnetic interference, offering a combination of high performance, low cost, and easy processing.

In this work, utilising the MultiObjective Optimisation (MOO) framework, III–V tunnel field effect transistors with surrounding gate (III–V TFETs [SG]) have been designed to optimise speed, power and variation for improved device logic parameters. III–V TFET are enhanced by combining the advantages of high-k Hafnium dioxide (HfO₂) dielectric and surrounding gate technologies. III–V TFETs (SG) have collaborated with indium arsenide (InAs) and gallium antimonide (GaSb) to offer better electron mobility, which further improves device performance. By augmenting the MOO framework and machine learning (ML) methods, we have performed the optimisation of III–V high-k TFETs with surrounding gate (III–V high-k TFETs [SG]) by efficiently handling the competing targets. Two advanced MOO algorithms—Non-Dominated Sorting (NS) Genetic Algorithm-III (GA-III) and Pareto Active-Learning Algorithm (PA-L)—are examined. Moreover, it has been demonstrated that ML-based MOO can automatically identify the best solutions for III–V high-k TFETs with Surrounding Gate, influencing the development of the next generation of nanoscale transistors.

The objective of this study is to examine how interface trap charges (ITC) influence the logic performance of a p-type heterojunction vertical TFET structure without and with gate overlap (HJVTFET-WOG and HJVTFET-WG). The logic gates can be realized with the help of the HJ-VTFET that uses germanium as the source material. Using HJVTFET-WOG and HJVTFET-WG structures, our simulations have proven that two-input universal logic functions like NAND and NOR gates may be realized. By adjusting the gate-source overlap region and choosing the right silicon body thickness, the suggested vertical TFET is able to perform logic operations. For verifying the universal gate functionality, the HJVTFET drain current characteristic and energy band diagram are analyzed by considering the effect of trapped charges. The tunneling width of logic functions is narrower when the ITC is positive and wider when it is negative, and the effective sub-threshold slopes (SS) have been examined. It has been discovered that positive ITCs can enhance device capabilities, while negative ITCs lead to diminishing functionality. The suggested HJVTFET-WOG structure is a promising structure for implementing the logic gates for digital application under the influence of interface trap charges because its electrical performance is less vulnerable to ITC than HJVTFET-WG.