International Journal of Numerical Modelling-Electronic Networks Devices and Fields最新文献

This report presents a performance comparison between two types of β-Ga₂O₃-based high electron mobility transistors (BGO-HEMTs), where channel doping is achieved through either polarization-induced doping (PID) or delta-doped (DD) modulation doping. The study evaluates and contrasts the performance characteristics of these two types of BGO-HEMTs. Using an optical phonon model to capture enhanced electron–phonon interactions in wide bandgap semiconductors, the maximum current density is estimated in both devices. Highly polarized AlN employed as barrier layers in PID BGO-HEMTs results in significantly higher conduction band offsets, thus achieving an order of magnitude higher sheet carrier density compared to DD BGO-HEMTs. Higher 2-DEG density ensures 2.5× higher current density and one order lower on-resistance in PID over DD BGO-HEMTs. Furthermore, PID BGO-HEMTs outperform as DC switches and require 13× lower gate periphery compared to DD BGO-HEMTs for the equal power rating. In addition, AlN as a gate barrier in PID BGO-HEMTs facilitates better thermal conductivity over DD BGO-HEMTs. The achieved results show the potential of PID β-Ga₂O₃ HEMTs for emerging DC power switching and compact high-power RF electronics applications.

This paper introduces a novel multilayer neural network technique to solve partial differential equations with non-integer derivatives (FPDEs). The proposed model is a deep feed-forward multiple layer neural network (DFMLNN) that is trained using advanced optimization approaches, namely adaptive moment estimation (Adam) and limited-memory Broyden-Fletcher-Goldfarb-Shanno (L-BFGS), which integrate neural networks. First, the Adam method is employed for training, and then the model is further improved using L-BFGS. The Laplace transform is used, concentrating on the Caputo fractional derivative, to approximate the FPDE. The efficacy of this strategy is confirmed through rigorous testing, which involves making predictions and comparing the outcomes with exact solutions. The results illustrate that this combined approach greatly improves both precision and effectiveness. This proposed multilayer neural network offers a robust and reliable framework for solving FPDEs.

The simulation of nanotransistors and the inclusion of all relevant physics is a challenging task, especially when working with one-dimensional (1D) nanomaterials in which quantum confinement strongly influences the material properties and device performance. Several groups have already developed state-of-the-art quantum transport simulators based on the first principles non-equilibrium Green's function (NEGF) formalism, and a few have been commercialized. However, these tools are computationally demanding as they require solving the NEGF and the 3D Poisson equation. Here we present an open-source quantum-transport solver for the first principles device engineering for nanoelectronics (QUDEN) implemented in Matlab. QUDEN uses NEGF and the ballistic top-of-the-barrier model to simulate ultrascaled field-effect transistors (FETs) with channels made of nanoribbons of 2D materials, while the device Hamiltonian is obtained using first principles density functional theory (DFT) in combination with maximally localized Wannier functions (MLWFs). This approach preserves the accuracy of the full NEGF-3D Poisson simulation in the on-state while using a simplified self-consistent electrostatics that leads to a much lower computational burden. Taking monolayer germanium-selenide (GeSe) nanoribbons as an example, we show that QUDEN can be used for fast screening and accurate evaluation of numerous 2D/1D materials for future FETs.

Growing concerns about electromagnetic radiation from communication technologies such as 5G have prompted a search for effective microwave-absorbing materials to mitigate potential health risks. This study focuses on the development of Fe-based amorphous/nanocrystalline alloys as microwave absorbers, with specific emphasis on achieving cost-effectiveness, reduced thickness, and superior absorption capabilities. FePC alloy powders, treated through thermal annealing and ball milling (synergistic processing), exhibit enhanced saturation magnetization and superior microwave absorption properties. The powders, with small particle sizes and high surface areas, demonstrate excellent absorption, achieving a minimum reflection loss (RL) of −30.1 dB at 12.8 GHz with a 5.3 GHz absorption bandwidth at 2 mm thickness. The results highlight the promising potential of these materials for practical applications in reducing electromagnetic interference, offering a combination of high performance, low cost, and easy processing.

In this work, utilising the MultiObjective Optimisation (MOO) framework, III–V tunnel field effect transistors with surrounding gate (III–V TFETs [SG]) have been designed to optimise speed, power and variation for improved device logic parameters. III–V TFET are enhanced by combining the advantages of high-k Hafnium dioxide (HfO₂) dielectric and surrounding gate technologies. III–V TFETs (SG) have collaborated with indium arsenide (InAs) and gallium antimonide (GaSb) to offer better electron mobility, which further improves device performance. By augmenting the MOO framework and machine learning (ML) methods, we have performed the optimisation of III–V high-k TFETs with surrounding gate (III–V high-k TFETs [SG]) by efficiently handling the competing targets. Two advanced MOO algorithms—Non-Dominated Sorting (NS) Genetic Algorithm-III (GA-III) and Pareto Active-Learning Algorithm (PA-L)—are examined. Moreover, it has been demonstrated that ML-based MOO can automatically identify the best solutions for III–V high-k TFETs with Surrounding Gate, influencing the development of the next generation of nanoscale transistors.

The objective of this study is to examine how interface trap charges (ITC) influence the logic performance of a p-type heterojunction vertical TFET structure without and with gate overlap (HJVTFET-WOG and HJVTFET-WG). The logic gates can be realized with the help of the HJ-VTFET that uses germanium as the source material. Using HJVTFET-WOG and HJVTFET-WG structures, our simulations have proven that two-input universal logic functions like NAND and NOR gates may be realized. By adjusting the gate-source overlap region and choosing the right silicon body thickness, the suggested vertical TFET is able to perform logic operations. For verifying the universal gate functionality, the HJVTFET drain current characteristic and energy band diagram are analyzed by considering the effect of trapped charges. The tunneling width of logic functions is narrower when the ITC is positive and wider when it is negative, and the effective sub-threshold slopes (SS) have been examined. It has been discovered that positive ITCs can enhance device capabilities, while negative ITCs lead to diminishing functionality. The suggested HJVTFET-WOG structure is a promising structure for implementing the logic gates for digital application under the influence of interface trap charges because its electrical performance is less vulnerable to ITC than HJVTFET-WG.

In this research, a machine learning method based on physics informed neural network and fractional-order Genocchi wavelets (FGWs) as activation function is explored to solve delay Hilfer fractional differential equations (DHFDEs). In this machine learning algorithm, the FGWs and $��\sinh �$ functions are used as kernel functions to approximate the solution of DHFDEs. In fact, the solution of DHFDEs is approximated as a combination of the mentioned kernel functions and a set of weights that are learned during the fitting process. We apply the roots of the Legendre functions as training data to develop the algorithm. Then, the training is proposed using the optimizer algorithm. In addition, the error bound of the presented strategy is discussed. Finally, to illustrate the validity and feasibility of our results, three numerical simulation along with several tables and figures are utilized.

The temperature-dependent self-heating effect (SHE) is critical for both accurate modeling and selecting optimal operating conditions, as elevated temperatures can compromise device reliability. These days, technology trends toward the miniaturization of electronic devices. As a result, device size decreases, and the packing density of a circuit at the integrated level increases. The combination of these two trends leads to an increase in power density and circuit temperature. For these reasons, our work aims to develop an electrothermal simulation of 20-nm SOI-FinFET. To rigorously analyze electrical behavior, we developed a mathematical framework integrating the ballistic-diffusive equation (BDE). The proposed model is validated by comparing simulated IDS-VGS characteristics with experimental data, demonstrating strong agreement. The SHE is related to thermal design, which is considered a basic procedure in modern microelectronics technology, measuring devices, and a series of modeling simulations and computer analysis of devices. “OFF” is not totally “OFF,” we have demonstrated the evolution of OFF-current (I_off) with device temperature and the impact of temperature in 20-nm SOI-FinFET on the subthreshold swing (SS) with both V_GS = 0.8 V and V_DS = 0.8 V.

This study presents an innovative approach leveraging TCAD simulations and a Convolutional Artificial Neural Network (C-ANN) to address challenges in VLSI design. A statistical sample of 4000 distinct values was simulated to predict drain current (I_ds), achieving a dramatic reduction in runtime from 46 to 48 days (conventional TCAD) to just 100–120 s using the proposed ML-based C-ANN. The proposed gate-stacking SiO₂ + HfO₂ FE-MOSFET device demonstrates significant advancements, including reductions in short-channel effects (SCEs), subthreshold swing (SS) by 3.12%–4.04%, and drain-induced barrier lowering (DIBL) by 10.19%. Enhanced performance metrics include 52.95% higher I_ON, 90% reduced gate leakage, and improved transconductance g_m, transconductance generation function (TGF), early voltage (V_EA), and intrinsic gain (A_v) by 26.18%, 27.12%, 29.35%, and 101.24%, respectively. RF parameters such as gate capacitance (C_gg), unity gain frequency (f_t), and gain frequency product (GFP) improved by 34.53%, 48.74%, and 21.18%, making this device ideal for high-speed switching and RF applications, promoting efficiency in low-power VLSI designs.