Alok Mishra, Urvashi Chopra, Vaithiyanathan D., B. Kaur
Purpose A low power flip-flop circuit is designed for energy-efficient devices. Digital sequential circuits are in huge demand because every processor has most of the parts of digital circuit. The sequential circuits consist of a basic data storing element, a latch is used to store single bit data. The flip-flop takes a sufficient portion of the total chip area and overall power consumption as well. This study aims to the low power energy-efficient applications like laptops, mobile phones and palmtops. Design/methodology/approach This paper proposes a new type of flip-flop that consists of the only 16 transistors with a single-phase clock. The flip-flop has two blocks, master and slave latch. In this design, the authors have focused on only master latch, which includes a level restoring circuit. It is used to help the master latch in data retention process. The latch circuit has two inverters in back-to-back arrangement. The proposed flip-flop is implemented on 65 nm complementary metal oxide semiconductor technology using Cadence Virtuoso environment and compared with other reported flip-flops. Findings The proposed flip-flop architecture outperformed the peak percentage, i.e. 79.25% as compared to transmission gate flip-flop and a minimum of 20.02% compared to 18 T true single phase clocking (TSPC) improvement in terms of power. It also improved C to Q delay and power delay product. In addition, by reducing the number of transistors the total area of the proposed flip-flop is reduced by a minimum of 13.76% with respect to 18TSPC and existing flip-flop. For reliability checking the Monte Carlo simulation is performed for thousand samples and it is compared with the recently reported 18TSPC flip-flop. Originality/value This work is tested by using a test circuit with a load capacitor of 0.2 fF. The proposed work uses a new topology to work as master-slave. Power consumption of this technique is very less and it is best suitable for low power applications. This circuit is working properly up to 2 GHz frequency.
{"title":"A low power high speed single phase clock level restoring 16T master-slave flip-flop","authors":"Alok Mishra, Urvashi Chopra, Vaithiyanathan D., B. Kaur","doi":"10.1108/cw-08-2020-0196","DOIUrl":"https://doi.org/10.1108/cw-08-2020-0196","url":null,"abstract":"\u0000Purpose\u0000A low power flip-flop circuit is designed for energy-efficient devices. Digital sequential circuits are in huge demand because every processor has most of the parts of digital circuit. The sequential circuits consist of a basic data storing element, a latch is used to store single bit data. The flip-flop takes a sufficient portion of the total chip area and overall power consumption as well. This study aims to the low power energy-efficient applications like laptops, mobile phones and palmtops.\u0000\u0000\u0000Design/methodology/approach\u0000This paper proposes a new type of flip-flop that consists of the only 16 transistors with a single-phase clock. The flip-flop has two blocks, master and slave latch. In this design, the authors have focused on only master latch, which includes a level restoring circuit. It is used to help the master latch in data retention process. The latch circuit has two inverters in back-to-back arrangement. The proposed flip-flop is implemented on 65 nm complementary metal oxide semiconductor technology using Cadence Virtuoso environment and compared with other reported flip-flops.\u0000\u0000\u0000Findings\u0000The proposed flip-flop architecture outperformed the peak percentage, i.e. 79.25% as compared to transmission gate flip-flop and a minimum of 20.02% compared to 18 T true single phase clocking (TSPC) improvement in terms of power. It also improved C to Q delay and power delay product. In addition, by reducing the number of transistors the total area of the proposed flip-flop is reduced by a minimum of 13.76% with respect to 18TSPC and existing flip-flop. For reliability checking the Monte Carlo simulation is performed for thousand samples and it is compared with the recently reported 18TSPC flip-flop.\u0000\u0000\u0000Originality/value\u0000This work is tested by using a test circuit with a load capacitor of 0.2 fF. The proposed work uses a new topology to work as master-slave. Power consumption of this technique is very less and it is best suitable for low power applications. This circuit is working properly up to 2 GHz frequency.\u0000","PeriodicalId":50693,"journal":{"name":"Circuit World","volume":" ","pages":""},"PeriodicalIF":0.9,"publicationDate":"2022-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"41684634","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Yifeng Zhu, Ziyang Zhang, Hailong Zhao, Shaoling Li
Purpose Five-level rectifiers have received widespread attention because of their excellent performance in high-voltage and high-power applications. Taking a five-level rectifier with only four-IGBT for this study, a sliding mode predictive control (SMPC) algorithm is proposed to solve the problem of poor dynamic performance and poor anti-disturbance ability under the traditional model predictive control with the PI outer loop. Design/methodology/approach First, mathematical models under the two-phase stationary coordinate system and two-phase synchronous rotating coordinate system are established. Then, the design of the outer-loop sliding mode controller is completed by establishing the sliding mode surface and design approach rate. The design of the inner-loop model predictive controller was completed by discretizing the mathematical model equations. The modulation part uses a space vector modulation technique to generate the PWM wave. Findings The sliding mode predictive control strategy is compared with the control strategy with a PI outer loop and a model predictive inner loop. The proposed control strategy has a faster dynamic response and stronger anti-interference ability. Originality/value For the five-level rectifier, the advantages of fast dynamic influence and parameter insensitivity of sliding mode control are used in the voltage outer loop to replace the traditional PI control, and which is integrated with the model predictive control used in the current inner loop to form a novel control strategy with a faster dynamic response and stronger immunity to disturbances. This novel strategy is called sliding mode predictive control (SMC).
{"title":"Sliding mode predictive control of a five-level rectifier with only four–IGBT","authors":"Yifeng Zhu, Ziyang Zhang, Hailong Zhao, Shaoling Li","doi":"10.1108/cw-05-2022-0125","DOIUrl":"https://doi.org/10.1108/cw-05-2022-0125","url":null,"abstract":"\u0000Purpose\u0000Five-level rectifiers have received widespread attention because of their excellent performance in high-voltage and high-power applications. Taking a five-level rectifier with only four-IGBT for this study, a sliding mode predictive control (SMPC) algorithm is proposed to solve the problem of poor dynamic performance and poor anti-disturbance ability under the traditional model predictive control with the PI outer loop.\u0000\u0000\u0000Design/methodology/approach\u0000First, mathematical models under the two-phase stationary coordinate system and two-phase synchronous rotating coordinate system are established. Then, the design of the outer-loop sliding mode controller is completed by establishing the sliding mode surface and design approach rate. The design of the inner-loop model predictive controller was completed by discretizing the mathematical model equations. The modulation part uses a space vector modulation technique to generate the PWM wave.\u0000\u0000\u0000Findings\u0000The sliding mode predictive control strategy is compared with the control strategy with a PI outer loop and a model predictive inner loop. The proposed control strategy has a faster dynamic response and stronger anti-interference ability.\u0000\u0000\u0000Originality/value\u0000For the five-level rectifier, the advantages of fast dynamic influence and parameter insensitivity of sliding mode control are used in the voltage outer loop to replace the traditional PI control, and which is integrated with the model predictive control used in the current inner loop to form a novel control strategy with a faster dynamic response and stronger immunity to disturbances. This novel strategy is called sliding mode predictive control (SMC).\u0000","PeriodicalId":50693,"journal":{"name":"Circuit World","volume":" ","pages":""},"PeriodicalIF":0.9,"publicationDate":"2022-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"47748770","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Kaiyuan Wu, Hao Huang, Ziwei Chen, M. Zeng, Tong Yin
Purpose This paper aims to overcome the limitations of low efficiency, low power density and strong electromagnetic interference (EMI) of the existing pulsed melt inert gas (MIG) welding power supply. So a novel and simplified implementation of digital high-power pulsed MIG welding power supply with LLC resonant converter is proposed in this work. Design/methodology/approach A simple parallel full-bridge LLC resonant converter structure is used to design the digital power supply with high welding current, low arc voltage, high open-circuit voltage and a wide range of arc loads, by effectively exploiting the variable load and high-power applications of LLC resonant converter. Findings The efficiency of each converter can reach up to 92.3%, under the rated operating condition. Notably, with proposed scheme, a short-circuit current mutation of 300 A can stabilize at 60 A within 8 ms. Furthermore, the pulsed MIG welding test shows that a stable welding process with 280 A peak current can be realized and a well-formed weld bead can be obtained, thereby verifying the feasibility of LLC resonant converter for pulsed MIG welding power supply. Originality/value The high efficiency, high power density and weak EMI of LLC resonant converter are conducive to the further optimization of pulsed MIG welding power supply. Consequently, a high performance welding power supply is implemented by taking adequate advantages of LLC resonant converter, which can provide equipment support for exploring better pulsed MIG welding processes.
{"title":"Novel and simplified implementation of digital high-power pulsed MIG welding power supply with LLC resonant converter","authors":"Kaiyuan Wu, Hao Huang, Ziwei Chen, M. Zeng, Tong Yin","doi":"10.1108/cw-03-2022-0068","DOIUrl":"https://doi.org/10.1108/cw-03-2022-0068","url":null,"abstract":"\u0000Purpose\u0000This paper aims to overcome the limitations of low efficiency, low power density and strong electromagnetic interference (EMI) of the existing pulsed melt inert gas (MIG) welding power supply. So a novel and simplified implementation of digital high-power pulsed MIG welding power supply with LLC resonant converter is proposed in this work.\u0000\u0000\u0000Design/methodology/approach\u0000A simple parallel full-bridge LLC resonant converter structure is used to design the digital power supply with high welding current, low arc voltage, high open-circuit voltage and a wide range of arc loads, by effectively exploiting the variable load and high-power applications of LLC resonant converter.\u0000\u0000\u0000Findings\u0000The efficiency of each converter can reach up to 92.3%, under the rated operating condition. Notably, with proposed scheme, a short-circuit current mutation of 300 A can stabilize at 60 A within 8 ms. Furthermore, the pulsed MIG welding test shows that a stable welding process with 280 A peak current can be realized and a well-formed weld bead can be obtained, thereby verifying the feasibility of LLC resonant converter for pulsed MIG welding power supply.\u0000\u0000\u0000Originality/value\u0000The high efficiency, high power density and weak EMI of LLC resonant converter are conducive to the further optimization of pulsed MIG welding power supply. Consequently, a high performance welding power supply is implemented by taking adequate advantages of LLC resonant converter, which can provide equipment support for exploring better pulsed MIG welding processes.\u0000","PeriodicalId":50693,"journal":{"name":"Circuit World","volume":" ","pages":""},"PeriodicalIF":0.9,"publicationDate":"2022-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"47347851","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Purpose The purpose of this paper through the redundant monitoring unit reflecting the real-time temperature change of the array, an adaptive refresh circuit based on temperature is designed. Design/methodology/approach This paper proposed a circuit design for temperature-adaptive refresh with a fixed refresh frequency of traditional memory, high refresh power consumption at low temperature and low refresh frequency at high temperature. Findings Adding a metal oxide semiconductor (MOS) redundancy monitoring unit consistent with the storage unit to the storage bank can monitor the temperature change of the storage bank in real time, so that temperature-based memory adaptive refresh can be implemented. Originality/value According to the characteristics that the data holding time of dynamic random access memory storage unit decreases with the increase of temperature, a MOS redundant monitoring unit which is consistent with the storage unit is added to the storage array with the 2T storage unit as the core.
{"title":"Design of temperature-based adaptive refresh circuit for 2T array memory","authors":"W. Yin, Lin Jiang","doi":"10.1108/cw-11-2020-0310","DOIUrl":"https://doi.org/10.1108/cw-11-2020-0310","url":null,"abstract":"\u0000Purpose\u0000The purpose of this paper through the redundant monitoring unit reflecting the real-time temperature change of the array, an adaptive refresh circuit based on temperature is designed.\u0000\u0000\u0000Design/methodology/approach\u0000This paper proposed a circuit design for temperature-adaptive refresh with a fixed refresh frequency of traditional memory, high refresh power consumption at low temperature and low refresh frequency at high temperature.\u0000\u0000\u0000Findings\u0000Adding a metal oxide semiconductor (MOS) redundancy monitoring unit consistent with the storage unit to the storage bank can monitor the temperature change of the storage bank in real time, so that temperature-based memory adaptive refresh can be implemented.\u0000\u0000\u0000Originality/value\u0000According to the characteristics that the data holding time of dynamic random access memory storage unit decreases with the increase of temperature, a MOS redundant monitoring unit which is consistent with the storage unit is added to the storage array with the 2T storage unit as the core.\u0000","PeriodicalId":50693,"journal":{"name":"Circuit World","volume":"1 1","pages":""},"PeriodicalIF":0.9,"publicationDate":"2022-09-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62058530","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Purpose The purpose of this paper is to check the Solar Photovoltaic (PV) inverter working condition with modified unipolar switching pulse. The gate pulse for the inverter switches is generated in MATLAB simulation and interfaced with hardware protype. Simulation results can be compared with hardware results. Design/methodology/approach A considerable amount of research has been done on different Pulse Width Modulation (PWM) techniques. Based on the findings, a modified Unipolar Sinusoidal PWM technique was created with one reference signal and two carrier signals+ (one for the positive half cycle and the other for the negative half cycle) and simulated in the MATLAB/Simulink platform. The prototype inverter module receives the simulated switching pulses via dSPACE DS1104 hardware software interfacing board. The hardware implementation has been done, and the hardware results compared with simulation results for various input voltage levels using resistive load. Findings This modified switching pulse has dead band and additional hardware setup is not required. 3-phase multi-level inverter output waveform has been achieved with six switches in this method and with low filter values, pure sine wave output can be obtained in simulation. By this method of switching pulse generation and testing, for every modification in switching pulse hardware gate driver is not required. Resulting time consumption and money investment are lower. Originality/value Modified Unipolar SPWM pulse generation technique is novel method for solar PV inverter. The switching pulse has been designed and tested in both MATLAB/Simulation and hardware prototype inverter. Hardware and software results are identical. This method of pulse generation and hardware implementation has not been done anywhere before.
{"title":"Modified unipolar SPWM inverter for solar PV applications using MATLAB/Simulink model interfaced with dSPACE DS1104","authors":"Ashok Kumar L., K. R.","doi":"10.1108/cw-07-2020-0165","DOIUrl":"https://doi.org/10.1108/cw-07-2020-0165","url":null,"abstract":"\u0000Purpose\u0000The purpose of this paper is to check the Solar Photovoltaic (PV) inverter working condition with modified unipolar switching pulse. The gate pulse for the inverter switches is generated in MATLAB simulation and interfaced with hardware protype. Simulation results can be compared with hardware results.\u0000\u0000\u0000Design/methodology/approach\u0000A considerable amount of research has been done on different Pulse Width Modulation (PWM) techniques. Based on the findings, a modified Unipolar Sinusoidal PWM technique was created with one reference signal and two carrier signals+ (one for the positive half cycle and the other for the negative half cycle) and simulated in the MATLAB/Simulink platform. The prototype inverter module receives the simulated switching pulses via dSPACE DS1104 hardware software interfacing board. The hardware implementation has been done, and the hardware results compared with simulation results for various input voltage levels using resistive load.\u0000\u0000\u0000Findings\u0000This modified switching pulse has dead band and additional hardware setup is not required. 3-phase multi-level inverter output waveform has been achieved with six switches in this method and with low filter values, pure sine wave output can be obtained in simulation. By this method of switching pulse generation and testing, for every modification in switching pulse hardware gate driver is not required. Resulting time consumption and money investment are lower.\u0000\u0000\u0000Originality/value\u0000Modified Unipolar SPWM pulse generation technique is novel method for solar PV inverter. The switching pulse has been designed and tested in both MATLAB/Simulation and hardware prototype inverter. Hardware and software results are identical. This method of pulse generation and hardware implementation has not been done anywhere before.\u0000","PeriodicalId":50693,"journal":{"name":"Circuit World","volume":" ","pages":""},"PeriodicalIF":0.9,"publicationDate":"2022-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"47600134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Purpose The primary aim of this paper is to present a novel design approach for a ring voltage-controlled oscillator (VCO) suitable for L-band applications, whose oscillation frequency is less sensitive to power supply variations. In a few decades, with the advancement of modern wireless communication equipment, there has been an increasing demand for low-power and robust communication systems for longer battery life. A sudden drop in power significantly affects the performance of the VCO. Supply insensitive circuit design is the backbone of uninterrupted VCO performance. Because of their important roles in a variety of applications, VCOs and phase locked loops (PLLs) have been the subject of significant research for decades. For a few decades, the VCO has been one of the major components used to provide a local frequency signal to the PLL. Design/methodology/approach First, this paper chose to present recent developments on implemented techniques of ring VCO design for various applications. A complementary metal oxide semiconductor (CMOS)-based supply compensation technique is presented, which aims to reduce the change in oscillation frequency with the supply. The proposed circuit is designed and simulated on Cadence Virtuoso in 0.18 µm CMOS process under 1.8 V power supply. Active differential configuration with a cross-coupled NMOS structure is designed, which eliminates losses and negates supply noise. The proposed VCO is designed for excellent performance in many areas, including the L-band microwave frequency range, supply sensitivity, occupied area, power consumption and phase noise. Findings This work provides the complete design aspect of a novel ring VCO design for the L-band frequency range, low phase noise, low occupied area and low power applications. The maximum value of the supply sensitivity for the proposed ring VCO is 1.31, which is achieved by changing the VDD by ±0.5%. A tuning frequency range of 1.47–1.81 GHz is achieved, which falls within the L-band frequency range. This frequency range is achieved by varying the control voltage from 0.0 to 0.8 V, which shows that the proposed ring VCO is also suitable for low voltage regions. The total power consumed by the proposed ring VCO is 14.70 mW, a remarkably low value using this large transistor count. The achievable value of phase noise is −88.76 dBc/Hz @ 1 MHz offset frequency, which is a relatively small value. The performance of the proposed ring VCO is also evaluated by the figure of merit, achieving −163.13 dBc/Hz, which assures the specificity of the proposed design. The process and temperature variation simulations also validate the proposed design. The proposed oscillator occupied an extremely small area of only 0.00019 mm2 compared to contemporary designs. Originality/value The proposed CMOS-based supply compensation method is a unique design with the size and other parameters of the components used. All the data and results obtained show its originality in compar
{"title":"Supply less sensitive ring voltage-controlled oscillator for microwave L-band frequencies","authors":"Parul Trivedi, B. Tiwari","doi":"10.1108/cw-08-2020-0170","DOIUrl":"https://doi.org/10.1108/cw-08-2020-0170","url":null,"abstract":"\u0000Purpose\u0000The primary aim of this paper is to present a novel design approach for a ring voltage-controlled oscillator (VCO) suitable for L-band applications, whose oscillation frequency is less sensitive to power supply variations. In a few decades, with the advancement of modern wireless communication equipment, there has been an increasing demand for low-power and robust communication systems for longer battery life. A sudden drop in power significantly affects the performance of the VCO. Supply insensitive circuit design is the backbone of uninterrupted VCO performance. Because of their important roles in a variety of applications, VCOs and phase locked loops (PLLs) have been the subject of significant research for decades. For a few decades, the VCO has been one of the major components used to provide a local frequency signal to the PLL.\u0000\u0000\u0000Design/methodology/approach\u0000First, this paper chose to present recent developments on implemented techniques of ring VCO design for various applications. A complementary metal oxide semiconductor (CMOS)-based supply compensation technique is presented, which aims to reduce the change in oscillation frequency with the supply. The proposed circuit is designed and simulated on Cadence Virtuoso in 0.18 µm CMOS process under 1.8 V power supply. Active differential configuration with a cross-coupled NMOS structure is designed, which eliminates losses and negates supply noise. The proposed VCO is designed for excellent performance in many areas, including the L-band microwave frequency range, supply sensitivity, occupied area, power consumption and phase noise.\u0000\u0000\u0000Findings\u0000This work provides the complete design aspect of a novel ring VCO design for the L-band frequency range, low phase noise, low occupied area and low power applications. The maximum value of the supply sensitivity for the proposed ring VCO is 1.31, which is achieved by changing the VDD by ±0.5%. A tuning frequency range of 1.47–1.81 GHz is achieved, which falls within the L-band frequency range. This frequency range is achieved by varying the control voltage from 0.0 to 0.8 V, which shows that the proposed ring VCO is also suitable for low voltage regions. The total power consumed by the proposed ring VCO is 14.70 mW, a remarkably low value using this large transistor count. The achievable value of phase noise is −88.76 dBc/Hz @ 1 MHz offset frequency, which is a relatively small value. The performance of the proposed ring VCO is also evaluated by the figure of merit, achieving −163.13 dBc/Hz, which assures the specificity of the proposed design. The process and temperature variation simulations also validate the proposed design. The proposed oscillator occupied an extremely small area of only 0.00019 mm2 compared to contemporary designs.\u0000\u0000\u0000Originality/value\u0000The proposed CMOS-based supply compensation method is a unique design with the size and other parameters of the components used. All the data and results obtained show its originality in compar","PeriodicalId":50693,"journal":{"name":"Circuit World","volume":" ","pages":""},"PeriodicalIF":0.9,"publicationDate":"2022-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43826914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Purpose This paper aims to study a power management circuit for a piezoelectric vibration energy harvester. It presents how to accumulate energy and provide regulated DC voltage for practical applications. Design/methodology/approach Energy storage and extraction circuit are proposed. While the storage stage consists of a full wave rectifier and a storage capacitor, the extraction stage includes a voltage comparator and regulator, which may provide the load steady DC voltage when the voltage of the storage capacitor is higher than the threshold. Findings The numerical analysis and experimental results indicate that it takes a longer time to charge to a specified voltage for the greater storage capacitor and the net charge flowing into the storage capacitor during each period decreases when the voltage of the storage capacitor is higher. The higher threshold voltage of the capacitor has lower harvesting efficiency owing to the rate of charging of the storage capacitor slowing down over time. Research limitations/implications Because of the chosen research method, the power management circuit is only suitable for the piezoelectric vibration energy harvester under resonant conditions. Practical implications This study includes practically useful applications for users to build a power management circuit for piezoelectric energy harvester. Originality/value This study presents results that the charging efficiency of the storage circuit is relative to the storage capacitor and the threshold voltage.
{"title":"Modeling and characterization of capacitor storage circuit for piezoelectric vibration energy harvester","authors":"Sheng Wei","doi":"10.1108/cw-02-2020-0018","DOIUrl":"https://doi.org/10.1108/cw-02-2020-0018","url":null,"abstract":"\u0000Purpose\u0000This paper aims to study a power management circuit for a piezoelectric vibration energy harvester. It presents how to accumulate energy and provide regulated DC voltage for practical applications.\u0000\u0000\u0000Design/methodology/approach\u0000Energy storage and extraction circuit are proposed. While the storage stage consists of a full wave rectifier and a storage capacitor, the extraction stage includes a voltage comparator and regulator, which may provide the load steady DC voltage when the voltage of the storage capacitor is higher than the threshold.\u0000\u0000\u0000Findings\u0000The numerical analysis and experimental results indicate that it takes a longer time to charge to a specified voltage for the greater storage capacitor and the net charge flowing into the storage capacitor during each period decreases when the voltage of the storage capacitor is higher. The higher threshold voltage of the capacitor has lower harvesting efficiency owing to the rate of charging of the storage capacitor slowing down over time.\u0000\u0000\u0000Research limitations/implications\u0000Because of the chosen research method, the power management circuit is only suitable for the piezoelectric vibration energy harvester under resonant conditions.\u0000\u0000\u0000Practical implications\u0000This study includes practically useful applications for users to build a power management circuit for piezoelectric energy harvester.\u0000\u0000\u0000Originality/value\u0000This study presents results that the charging efficiency of the storage circuit is relative to the storage capacitor and the threshold voltage.\u0000","PeriodicalId":50693,"journal":{"name":"Circuit World","volume":" ","pages":""},"PeriodicalIF":0.9,"publicationDate":"2022-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"44859521","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Cet entretien réalisé en septembre 2021 balaye les grands thèmes de l’activité de recherche et de création du compositeur et sociologue français François Ribac, en se focalisant sur le projet collaboratif « Arts de la scène et musique dans l’Anthropocène » (2016-2019), qui associait un programme de recherche (enquêtes de terrain sur la matérialité des instruments de musique et sur les positionnements écologiques de divers groupes et institutions), un séminaire international (Le Son de l’Anthropocène) et des actions collectives (notamment le Grand Orchestre de la Transition) impliquant artistes, activistes et habitant·e·s de Dijon. Ce programme a mené Ribac à distinguer trois grandes approches de l’environnementalisme : les politiques de limitation de l’empreinte matérielle de la production scénique ; la production d’oeuvres alertant ou éduquant le public sur la crise écologique ; enfin, la coconstruction de projets participatifs locaux entremêlant les dimensions matérielle et esthétique. L’entretien aborde également des questions de recherche sur l’histoire environnementale et les représentations de la nature dans la musique classique, ainsi que les enjeux politiques actuels.
{"title":"Agir en chercheur et en musicien dans l’Anthropocène : entretien avec François\u0000 Ribac","authors":"Nicolas Donin, François Ribac","doi":"10.7202/1091906ar","DOIUrl":"https://doi.org/10.7202/1091906ar","url":null,"abstract":"Cet entretien réalisé en septembre 2021 balaye les grands thèmes de\u0000 l’activité de recherche et de création du compositeur et sociologue français\u0000 François Ribac, en se focalisant sur le projet collaboratif « Arts de la scène et\u0000 musique dans l’Anthropocène » (2016-2019), qui associait un programme de recherche\u0000 (enquêtes de terrain sur la matérialité des instruments de musique et sur les\u0000 positionnements écologiques de divers groupes et institutions), un séminaire\u0000 international (Le Son de l’Anthropocène) et des actions collectives (notamment le\u0000 Grand Orchestre de la Transition) impliquant artistes, activistes et habitant·e·s de\u0000 Dijon. Ce programme a mené Ribac à distinguer trois grandes approches de\u0000 l’environnementalisme : les politiques de limitation de l’empreinte matérielle de la\u0000 production scénique ; la production d’oeuvres alertant ou éduquant le public sur la\u0000 crise écologique ; enfin, la coconstruction de projets participatifs locaux\u0000 entremêlant les dimensions matérielle et esthétique. L’entretien aborde également\u0000 des questions de recherche sur l’histoire environnementale et les représentations de\u0000 la nature dans la musique classique, ainsi que les enjeux politiques\u0000 actuels.","PeriodicalId":50693,"journal":{"name":"Circuit World","volume":"50 1","pages":""},"PeriodicalIF":0.9,"publicationDate":"2022-08-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74174953","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The catastrophic impacts of climate change, vanishing biodiversity, and the rapid deterioration of our global ecosystems require urgent attention and aggressive political action. This article explores a body of interdisciplinary research through a series of ecological sound projects designed to draw attention and awareness to changing ecosystems. These projects are framed as participatory acoustic ecology and position the discipline as a socially engaged, inclusive, accessible, interdisciplinary field that inspires communities to listen and act during times of crisis.
{"title":"Sounding Extremes: Ecological Sound Art in the Anthropocene","authors":"Leah Barclay","doi":"10.7202/1091901ar","DOIUrl":"https://doi.org/10.7202/1091901ar","url":null,"abstract":"\u0000 The catastrophic impacts of climate change, vanishing biodiversity, and the rapid deterioration of our global ecosystems require urgent attention and aggressive political action. This article explores a body of interdisciplinary research through a series of ecological sound projects designed to draw attention and awareness to changing ecosystems. These projects are framed as participatory acoustic ecology and position the discipline as a socially engaged, inclusive, accessible, interdisciplinary field that inspires communities to listen and act during times of crisis.\u0000","PeriodicalId":50693,"journal":{"name":"Circuit World","volume":"186 1","pages":""},"PeriodicalIF":0.9,"publicationDate":"2022-08-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77023111","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Paradis en flammes et sensibilités artistiques","authors":"Maxime Mckinley","doi":"10.7202/1091897ar","DOIUrl":"https://doi.org/10.7202/1091897ar","url":null,"abstract":"","PeriodicalId":50693,"journal":{"name":"Circuit World","volume":"7 1","pages":""},"PeriodicalIF":0.9,"publicationDate":"2022-08-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75085101","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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