Linsheng Liu, Q. Lin, Wu Haifeng, Yijun Chen, Liu-lin Hu
Purpose The design and implementation of a broadband quasi-monolithic microwave integrated circuit (q-MMIC) power amplifier (PA) is presented for 0.2 to 2.2 GHz applications. Design/methodology/approach To obtain an efficient, high-gain and high-power performance with in a compact and low-cost size, the prototype is based on Gallium nitride (GaN) on SiC 0.25-µm transistors, whereas the passive matching networks are realized on an AlN substrate as thin film circuit. Findings Measured results of the q-MMIC PA across the 0.2 to 2.2 GHz band show at least 32 ± 3 dB small-signal gains, an output power of 7 to 12 W and an average power add efficiency greater than 54%. The q-MMIC occupies an area of 12.8 × 14.5 mm2. Originality/value To the best of the authors’ knowledge, this work reports the first full integrated PA which covers the frequency range of 0.2 to 2.2 GHz and achieves the combination of highest gain, about 10 W output power, together with the smallest component size among all published GaN PAs to date.
{"title":"A compact broadband high power quasi-MMIC GaN power amplifier","authors":"Linsheng Liu, Q. Lin, Wu Haifeng, Yijun Chen, Liu-lin Hu","doi":"10.1108/cw-07-2020-0157","DOIUrl":"https://doi.org/10.1108/cw-07-2020-0157","url":null,"abstract":"\u0000Purpose\u0000The design and implementation of a broadband quasi-monolithic microwave integrated circuit (q-MMIC) power amplifier (PA) is presented for 0.2 to 2.2 GHz applications.\u0000\u0000\u0000Design/methodology/approach\u0000To obtain an efficient, high-gain and high-power performance with in a compact and low-cost size, the prototype is based on Gallium nitride (GaN) on SiC 0.25-µm transistors, whereas the passive matching networks are realized on an AlN substrate as thin film circuit.\u0000\u0000\u0000Findings\u0000Measured results of the q-MMIC PA across the 0.2 to 2.2 GHz band show at least 32 ± 3 dB small-signal gains, an output power of 7 to 12 W and an average power add efficiency greater than 54%. The q-MMIC occupies an area of 12.8 × 14.5 mm2.\u0000\u0000\u0000Originality/value\u0000To the best of the authors’ knowledge, this work reports the first full integrated PA which covers the frequency range of 0.2 to 2.2 GHz and achieves the combination of highest gain, about 10 W output power, together with the smallest component size among all published GaN PAs to date.\u0000","PeriodicalId":50693,"journal":{"name":"Circuit World","volume":" ","pages":""},"PeriodicalIF":0.9,"publicationDate":"2021-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"42784249","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Purpose This study aims to present two stage pseudomorphic high electron mobility transistor-based low noise amplifier (LNA) designed using low temperature co-fire ceramic (LTCC) technique for ultra-high frequency (UHF) band. The LNA operates in the frequency range of (400∼500) MHz which is suitable for wireless communication applications. Design/methodology/approach This LNA uses resistive capacitive (RC) feedback in the first stage to have wide bandwidth and interstage network for gain enhancement. By using external RC feedback, stability is improved and noise matching in the input stage is isolated by decoupling inductor. The excellent performance parameters including gain, noise figure (NF), wideband and linearity are attained without affecting the power consumption, compactness and cost of the proposed design. Findings Simulation is carried out using advanced design software and the result shows that gain of 33.7 dB, NF 0.416 dB and 1 dB compression point (P1dB) of 18.59 dBm are achieved with a supply voltage of 2.5 V. The return loss of input and output are −19.3 dB and −10.5 dB, respectively. From the above aforementioned parameters, it is confirmed that the proposed LNA is a promising candidate for receivers where high gain and very low NF are always demandable with good linearity for applications operating in the UHF band. Originality/value The innovation of the proposed LNA is that the concurrent attainment of high gain, low NF, wideband, optimum input matching, good stability by RC feedback and interstage network using LTCC technique to achieve robustness, low cost and compactness to prove the applicability of design for wireless applications.
{"title":"An ultra-low noise pseudomorphic high electron mobility transistor (pHEMT)-based low noise amplifier using low temperature co-fire ceramic (LTCC) technique","authors":"Bhuvaneshwari Subburaman, Kanthamani Sundharajan","doi":"10.1108/cw-10-2020-0275","DOIUrl":"https://doi.org/10.1108/cw-10-2020-0275","url":null,"abstract":"\u0000Purpose\u0000This study aims to present two stage pseudomorphic high electron mobility transistor-based low noise amplifier (LNA) designed using low temperature co-fire ceramic (LTCC) technique for ultra-high frequency (UHF) band. The LNA operates in the frequency range of (400∼500) MHz which is suitable for wireless communication applications.\u0000\u0000\u0000Design/methodology/approach\u0000This LNA uses resistive capacitive (RC) feedback in the first stage to have wide bandwidth and interstage network for gain enhancement. By using external RC feedback, stability is improved and noise matching in the input stage is isolated by decoupling inductor. The excellent performance parameters including gain, noise figure (NF), wideband and linearity are attained without affecting the power consumption, compactness and cost of the proposed design.\u0000\u0000\u0000Findings\u0000Simulation is carried out using advanced design software and the result shows that gain of 33.7 dB, NF 0.416 dB and 1 dB compression point (P1dB) of 18.59 dBm are achieved with a supply voltage of 2.5 V. The return loss of input and output are −19.3 dB and −10.5 dB, respectively. From the above aforementioned parameters, it is confirmed that the proposed LNA is a promising candidate for receivers where high gain and very low NF are always demandable with good linearity for applications operating in the UHF band.\u0000\u0000\u0000Originality/value\u0000The innovation of the proposed LNA is that the concurrent attainment of high gain, low NF, wideband, optimum input matching, good stability by RC feedback and interstage network using LTCC technique to achieve robustness, low cost and compactness to prove the applicability of design for wireless applications.\u0000","PeriodicalId":50693,"journal":{"name":"Circuit World","volume":" ","pages":""},"PeriodicalIF":0.9,"publicationDate":"2021-08-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"46564341","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
P. Sumathy, N. Divya, Jagabar Sathik, A. Lavanya, K. Vijayakumar, D. Almakhles
{"title":"A comprehensive study on various dc–dc converter voltage-boosting topologies and their applications","authors":"P. Sumathy, N. Divya, Jagabar Sathik, A. Lavanya, K. Vijayakumar, D. Almakhles","doi":"10.1108/CW-12-2020-0338","DOIUrl":"https://doi.org/10.1108/CW-12-2020-0338","url":null,"abstract":"","PeriodicalId":50693,"journal":{"name":"Circuit World","volume":" ","pages":""},"PeriodicalIF":0.9,"publicationDate":"2021-08-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"44481098","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
D. Fu, Y. Wen, Jida Chen, Lansi Lu, Ting Yan, C. Liao, Wei‐dong He, Shijin Chen, Lizhao Sheng
Purpose The purpose of this paper is to study an electrolytic etching method to prepare fine lines on printed circuit board (PCB). And the influence of organics on the side corrosion protection of PCB fine lines during electrolytic etching is studied in detail. Design/methodology/approach In this paper, the etching factor of PCB fine lines produced by new method and the traditional method was analyzed by the metallographic microscope. In addition, field emission scanning electron microscopy (SEM) and X-ray photoelectron spectroscopy (XPS) were used to study the inhibition of undercut of the four organometallic corrosion inhibitors with 2,5-dimercapto-1,3,4-thiadiazole, benzotriazole, l-phenylalanine and l-tryptophan in the electrolytic etching process. Findings The SEM results show that corrosion inhibitors can greatly inhibit undercut of PCB fine lines during electrolytic etching process. XPS results indicate that N and S atoms on corrosion inhibitors can form covalent bonds with copper during electrolytic etching process, which can be adsorbed on sidewall of PCB fine lines to form a dense protective film, thereby inhibiting undercut of PCB fine lines. Quantum chemical calculations show that four corrosion inhibitor molecules tend to be parallel to copper surface and adsorb on copper surface in an optimal form. COMSOL Multiphysics simulation revealed that there is a significant difference in the amount of corrosion inhibitor adsorbed on sidewall of the fine line and the etching area. Originality/value As a clean production technology, electrolytic etching method has a good development indicator for the production of high-quality fine lines in PCB industry in the future. And it is of great significance in saving resources and reducing environmental pollution.
{"title":"Study on fine lines and undercut suppression of printed circuit board prepared by electrolytic etching","authors":"D. Fu, Y. Wen, Jida Chen, Lansi Lu, Ting Yan, C. Liao, Wei‐dong He, Shijin Chen, Lizhao Sheng","doi":"10.1108/cw-05-2019-0047","DOIUrl":"https://doi.org/10.1108/cw-05-2019-0047","url":null,"abstract":"Purpose The purpose of this paper is to study an electrolytic etching method to prepare fine lines on printed circuit board (PCB). And the influence of organics on the side corrosion protection of PCB fine lines during electrolytic etching is studied in detail. Design/methodology/approach In this paper, the etching factor of PCB fine lines produced by new method and the traditional method was analyzed by the metallographic microscope. In addition, field emission scanning electron microscopy (SEM) and X-ray photoelectron spectroscopy (XPS) were used to study the inhibition of undercut of the four organometallic corrosion inhibitors with 2,5-dimercapto-1,3,4-thiadiazole, benzotriazole, l-phenylalanine and l-tryptophan in the electrolytic etching process. Findings The SEM results show that corrosion inhibitors can greatly inhibit undercut of PCB fine lines during electrolytic etching process. XPS results indicate that N and S atoms on corrosion inhibitors can form covalent bonds with copper during electrolytic etching process, which can be adsorbed on sidewall of PCB fine lines to form a dense protective film, thereby inhibiting undercut of PCB fine lines. Quantum chemical calculations show that four corrosion inhibitor molecules tend to be parallel to copper surface and adsorb on copper surface in an optimal form. COMSOL Multiphysics simulation revealed that there is a significant difference in the amount of corrosion inhibitor adsorbed on sidewall of the fine line and the etching area. Originality/value As a clean production technology, electrolytic etching method has a good development indicator for the production of high-quality fine lines in PCB industry in the future. And it is of great significance in saving resources and reducing environmental pollution.","PeriodicalId":50693,"journal":{"name":"Circuit World","volume":" ","pages":""},"PeriodicalIF":0.9,"publicationDate":"2021-08-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49454986","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Xingquan Wang, Lu Xiuyuan, Wei Chen, Fengpeng Wang, Jun Huang, Lingli Liu, Li Mengchao, Kui Lin
Purpose This paper aims to improve the general circuit of driving and protection based on insulated gate bipolar transistor (IGBT) in dielectric barrier discharge power supply by designing a novel half-bridge inverter circuit with discrete components. Design/methodology/approach With one SG3524 chip, the structure based on discrete components is used to design the IGBT drive circuit. The driving waveform is isolated and sent out by photo-coupler 6N137. The protection circuit is realized by Hall sensor directly detecting the main circuit current, supplemented by a few components, including diodes, resistors, capacitors and triodes. It improves the reliability of the protection circuit. Findings In the driving circuit, the phase difference of signals from two channels are 180°. Moreover, when the duty cycle is set at 40%, it can ensure sufficient pulse width modulation response time. In the protection circuit, when over-current occurs, an intermittent output signal is automatically sent out. Furthermore, the over-current response time can be controlled independently. The peak voltage can be adjusted continuously from 0 to 30 kV with its frequency from 8 to 25 kHz and the power output up to 150 W. Originality/value The novel circuit of driving and protection makes not only its structure simpler and easier to be realized but also key parameters, such as frequency, the duty cycle and the driving voltage, continuously adjustable. Moreover, the power supply is suitable for other discharges such as corona discharge and jet discharge.
{"title":"A half-bridge IGBT drive and protection circuit in dielectric barrier discharge power supply","authors":"Xingquan Wang, Lu Xiuyuan, Wei Chen, Fengpeng Wang, Jun Huang, Lingli Liu, Li Mengchao, Kui Lin","doi":"10.1108/cw-11-2020-0329","DOIUrl":"https://doi.org/10.1108/cw-11-2020-0329","url":null,"abstract":"Purpose This paper aims to improve the general circuit of driving and protection based on insulated gate bipolar transistor (IGBT) in dielectric barrier discharge power supply by designing a novel half-bridge inverter circuit with discrete components. Design/methodology/approach With one SG3524 chip, the structure based on discrete components is used to design the IGBT drive circuit. The driving waveform is isolated and sent out by photo-coupler 6N137. The protection circuit is realized by Hall sensor directly detecting the main circuit current, supplemented by a few components, including diodes, resistors, capacitors and triodes. It improves the reliability of the protection circuit. Findings In the driving circuit, the phase difference of signals from two channels are 180°. Moreover, when the duty cycle is set at 40%, it can ensure sufficient pulse width modulation response time. In the protection circuit, when over-current occurs, an intermittent output signal is automatically sent out. Furthermore, the over-current response time can be controlled independently. The peak voltage can be adjusted continuously from 0 to 30 kV with its frequency from 8 to 25 kHz and the power output up to 150 W. Originality/value The novel circuit of driving and protection makes not only its structure simpler and easier to be realized but also key parameters, such as frequency, the duty cycle and the driving voltage, continuously adjustable. Moreover, the power supply is suitable for other discharges such as corona discharge and jet discharge.","PeriodicalId":50693,"journal":{"name":"Circuit World","volume":" ","pages":""},"PeriodicalIF":0.9,"publicationDate":"2021-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"44097878","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Purpose In parallel sampling method, the size of the sampling capacitor is reduced to improve the bandwidth of the ADC. Design/methodology/approach Various low-power techniques for 10-bit 200MS/s pipelined analog-to-digital converter (ADC) are presented. This work comprises two techniques including parallel sampling and switched op-amp sharing technique. Findings This paper aims to study the effect of parallel sampling and switched op-amp sharing techniques on power consumption in pipelined ADC. In switched op-amp sharing technique, the numbers of op-amps used in the stages are reduced. Because of the reduction in the size of capacitors in parallel sampling technique and op-amps in the switched op-amp sharing technique, the power consumption of the proposed pipelined ADC is reduced to a greater extent. Originality/value Simulated the 10-bit 200MS/s pipelined ADC with complementary metal oxide semiconductor process and the simulation results shows a maximum differential non-linearity of +0.31/−0.31 LSB and the maximum integral non-linearity (of +0.74/−0.74 LSB with 62.9 dB SFDR, 55.90 dB SNDR and ENOB of 8.99 bits, respectively, for 18mW power consumption with the supply voltage of 1.8 V.
目的在并行采样方法中，减小采样电容器的大小以提高ADC的带宽。设计/方法/方法介绍了10位200MS/s流水线模数转换器（ADC）的各种低功耗技术。这项工作包括两种技术，包括并行采样和开关运算放大器共享技术。本文旨在研究并行采样和开关运算放大器共享技术对流水线ADC功耗的影响。在开关运算放大器共享技术中，减少了各级中使用的运算放大器的数量。由于并行采样技术中电容器的大小和开关运算放大器共享技术中运算放大器的大小的减小，所提出的流水线ADC的功耗在更大程度上降低。独创性/数值模拟采用互补金属氧化物半导体工艺的10位200MS/s流水线ADC，模拟结果显示最大微分非线性为+0.31/−0.31 LSB，最大积分非线性为+0.74/−0.74 LSB，62.9 dB SFDR，55.90 dB SNDR和ENOB为8.99 位，分别用于电源电压为1.8时的18mW功耗 五、
{"title":"A 10-bit 200 MS/s pipelined ADC with parallel sampling and switched op-amp sharing technique","authors":"D. Sam, P. Paul","doi":"10.1108/cw-12-2020-0356","DOIUrl":"https://doi.org/10.1108/cw-12-2020-0356","url":null,"abstract":"\u0000Purpose\u0000In parallel sampling method, the size of the sampling capacitor is reduced to improve the bandwidth of the ADC.\u0000\u0000\u0000Design/methodology/approach\u0000Various low-power techniques for 10-bit 200MS/s pipelined analog-to-digital converter (ADC) are presented. This work comprises two techniques including parallel sampling and switched op-amp sharing technique.\u0000\u0000\u0000Findings\u0000This paper aims to study the effect of parallel sampling and switched op-amp sharing techniques on power consumption in pipelined ADC. In switched op-amp sharing technique, the numbers of op-amps used in the stages are reduced. Because of the reduction in the size of capacitors in parallel sampling technique and op-amps in the switched op-amp sharing technique, the power consumption of the proposed pipelined ADC is reduced to a greater extent.\u0000\u0000\u0000Originality/value\u0000Simulated the 10-bit 200MS/s pipelined ADC with complementary metal oxide semiconductor process and the simulation results shows a maximum differential non-linearity of +0.31/−0.31 LSB and the maximum integral non-linearity (of +0.74/−0.74 LSB with 62.9 dB SFDR, 55.90 dB SNDR and ENOB of 8.99 bits, respectively, for 18mW power consumption with the supply voltage of 1.8 V.\u0000","PeriodicalId":50693,"journal":{"name":"Circuit World","volume":" ","pages":""},"PeriodicalIF":0.9,"publicationDate":"2021-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49149455","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Purpose The nano-router would be a mastery device for providing high-speed data delivery. Here nano-router with a space-efficient crossbar scheduler is used for making absolutely less consumption in power. Design/methodology/approach In the emerging modern technology, every one of us is expecting a delivery of data at a high speed. To achieve high-speed delivery the authors are using the router. The router used here is at nanoscale reading which provides a compact size. Findings This can be implemented using the modern tools called Quantum-dot Cellular Automata (QCA) which is operated without the use of a transistor. As conventional complementary metal oxide semiconductor (CMOS) designs have some limitations such as low density, high power consumption and requirement of a large area. Research limitations/implications To overcome these limitations the QCA is used. It characterizes capability is used to substituting CMOS technology. The round-robin fashion is used in a high-speed space-efficient crossbar scheduler. Practical implications The simulation of the planned circuit with notional information established the practical identity of the scheme. Social implications The proposed nano router can be stimulated in the QCA environment using the QCADesigner tool and the power of the router can be calculated with the QCADesigner–E tool. Originality/value The proposed nano router can be stimulated in the QCA environment using the QCADesigner tool and the power of the router can be calculated with the QCADesigner–E tool. In this work, the performance of the router can be done in both the QCA environment and CMOS technology.
{"title":"A novel design of nano router with high-speed crossbar scheduler for digital systems in QCA paradigm","authors":"Kalpana Kasilingam, P. Balaiah","doi":"10.1108/cw-10-2020-0280","DOIUrl":"https://doi.org/10.1108/cw-10-2020-0280","url":null,"abstract":"\u0000Purpose\u0000The nano-router would be a mastery device for providing high-speed data delivery. Here nano-router with a space-efficient crossbar scheduler is used for making absolutely less consumption in power.\u0000\u0000\u0000Design/methodology/approach\u0000In the emerging modern technology, every one of us is expecting a delivery of data at a high speed. To achieve high-speed delivery the authors are using the router. The router used here is at nanoscale reading which provides a compact size.\u0000\u0000\u0000Findings\u0000This can be implemented using the modern tools called Quantum-dot Cellular Automata (QCA) which is operated without the use of a transistor. As conventional complementary metal oxide semiconductor (CMOS) designs have some limitations such as low density, high power consumption and requirement of a large area.\u0000\u0000\u0000Research limitations/implications\u0000To overcome these limitations the QCA is used. It characterizes capability is used to substituting CMOS technology. The round-robin fashion is used in a high-speed space-efficient crossbar scheduler.\u0000\u0000\u0000Practical implications\u0000The simulation of the planned circuit with notional information established the practical identity of the scheme.\u0000\u0000\u0000Social implications\u0000The proposed nano router can be stimulated in the QCA environment using the QCADesigner tool and the power of the router can be calculated with the QCADesigner–E tool.\u0000\u0000\u0000Originality/value\u0000The proposed nano router can be stimulated in the QCA environment using the QCADesigner tool and the power of the router can be calculated with the QCADesigner–E tool. In this work, the performance of the router can be done in both the QCA environment and CMOS technology.\u0000","PeriodicalId":50693,"journal":{"name":"Circuit World","volume":" ","pages":""},"PeriodicalIF":0.9,"publicationDate":"2021-07-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49383275","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Purpose The main purpose of this paper is to propose a quasi-impedance source (QIS) converter fed switched reluctance motor (SRM) drive. The proposed converter topology is configured for DC link capacitance minimization and power factor (PF) correction. Design/methodology/approach A QIS converter is used as a front end converter to reduce the bulk capacitance requirement during current commutation and to decline the power ripple. To improve the PF with reduced total harmonic distortion at the input current, the PF current control loop is merged with the QIS converter control loop. Findings The overall SRM drive speed is regulated over a wide range by controlling the DC link voltage. The voltage regulation can be achieved by pulse width modulation of the QIS converter. Hence, the overall system efficiency has been improved by operating the proposed converter at a low switching frequency. Moreover, the proposed QIS converter uses an advanced repetitive controller to achieve voltage regulation and fewer ripples in torque. Originality/value The steady state and dynamic analyzes have been performed on the proposed drive topology. The performance of the proposed topology has been simulated through MATLAB/Simulink environment. A hardware prototype with a processor of Xilinx SPARTAN 6 field-programmable gate array has been used to validate the experimental response with the simulation results.
{"title":"Performance enhancement of switched reluctance motor drive using front-end converter","authors":"Indira Damarla, Venmathi Mahendran","doi":"10.1108/cw-08-2020-0182","DOIUrl":"https://doi.org/10.1108/cw-08-2020-0182","url":null,"abstract":"\u0000Purpose\u0000The main purpose of this paper is to propose a quasi-impedance source (QIS) converter fed switched reluctance motor (SRM) drive. The proposed converter topology is configured for DC link capacitance minimization and power factor (PF) correction.\u0000\u0000\u0000Design/methodology/approach\u0000A QIS converter is used as a front end converter to reduce the bulk capacitance requirement during current commutation and to decline the power ripple. To improve the PF with reduced total harmonic distortion at the input current, the PF current control loop is merged with the QIS converter control loop.\u0000\u0000\u0000Findings\u0000The overall SRM drive speed is regulated over a wide range by controlling the DC link voltage. The voltage regulation can be achieved by pulse width modulation of the QIS converter. Hence, the overall system efficiency has been improved by operating the proposed converter at a low switching frequency. Moreover, the proposed QIS converter uses an advanced repetitive controller to achieve voltage regulation and fewer ripples in torque.\u0000\u0000\u0000Originality/value\u0000The steady state and dynamic analyzes have been performed on the proposed drive topology. The performance of the proposed topology has been simulated through MATLAB/Simulink environment. A hardware prototype with a processor of Xilinx SPARTAN 6 field-programmable gate array has been used to validate the experimental response with the simulation results.\u0000","PeriodicalId":50693,"journal":{"name":"Circuit World","volume":" ","pages":""},"PeriodicalIF":0.9,"publicationDate":"2021-07-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49398623","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Gande, S. Mallick, B. Biswas, S. Chatterjee, D. R. Poddar
Purpose This paper aims to present a compact, broadband substrate integrated waveguide (SIW) three-way power divider with improved isolation based on six-port SIW coupler. Design/methodology/approach The power coupling among the three output ports occurs due to short openings in the narrow walls of the central SIW channel. Performance improvement in the isolation and return loss among ports is achieved using matching posts placed at the input and output ends of the coupling region. This enhances the coupling between TE10 and TE30 modes. The input matching ports enhance the return loss, whereas the isolation is alleviated by both the input and output matching posts. The bandwidth enhancement is achieved by optimizing the outer SIW channel widths. Findings The measured fractional bandwidth of 27.3% with over 15 dB of isolation and return loss is achieved. The coupling length is 1.55 λg at the centre frequency. The power divider achieves better than 15 dB isolation between non-adjacent output ports. The measured reflection and isolation coefficients are in close agreement with simulated results over 8.2 to 10.8 GHz. Practical implications Isolation between the adjacent and non-adjacent ports is an important parameter as the reflections from these ports will interfere with signals from other ports reducing the fractional bandwidth of the power divider and affecting the overall performance of the transmitters and receivers. Originality/value The authors present the enhancement of isolation between the output non-adjacent ports by optimizing the SIW channel width and matching post in the coupling region to reduce the reflected signals from non-adjacent ports entering into other ports. To the author’s knowledge, this is the only SIW three-way power divider paper showing non-adjacent port isolation among six-port couplers based three-way power dividers.
{"title":"A compact, broadband three-way substrate integrated waveguide power divider with improved isolation","authors":"A. Gande, S. Mallick, B. Biswas, S. Chatterjee, D. R. Poddar","doi":"10.1108/CW-04-2020-0074","DOIUrl":"https://doi.org/10.1108/CW-04-2020-0074","url":null,"abstract":"\u0000Purpose\u0000This paper aims to present a compact, broadband substrate integrated waveguide (SIW) three-way power divider with improved isolation based on six-port SIW coupler.\u0000\u0000\u0000Design/methodology/approach\u0000The power coupling among the three output ports occurs due to short openings in the narrow walls of the central SIW channel. Performance improvement in the isolation and return loss among ports is achieved using matching posts placed at the input and output ends of the coupling region. This enhances the coupling between TE10 and TE30 modes. The input matching ports enhance the return loss, whereas the isolation is alleviated by both the input and output matching posts. The bandwidth enhancement is achieved by optimizing the outer SIW channel widths.\u0000\u0000\u0000Findings\u0000The measured fractional bandwidth of 27.3% with over 15 dB of isolation and return loss is achieved. The coupling length is 1.55 λg at the centre frequency. The power divider achieves better than 15 dB isolation between non-adjacent output ports. The measured reflection and isolation coefficients are in close agreement with simulated results over 8.2 to 10.8 GHz.\u0000\u0000\u0000Practical implications\u0000Isolation between the adjacent and non-adjacent ports is an important parameter as the reflections from these ports will interfere with signals from other ports reducing the fractional bandwidth of the power divider and affecting the overall performance of the transmitters and receivers.\u0000\u0000\u0000Originality/value\u0000The authors present the enhancement of isolation between the output non-adjacent ports by optimizing the SIW channel width and matching post in the coupling region to reduce the reflected signals from non-adjacent ports entering into other ports. To the author’s knowledge, this is the only SIW three-way power divider paper showing non-adjacent port isolation among six-port couplers based three-way power dividers.\u0000","PeriodicalId":50693,"journal":{"name":"Circuit World","volume":" ","pages":""},"PeriodicalIF":0.9,"publicationDate":"2021-07-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"45572539","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Purpose Energy is the major concern in wireless sensor networks (WSNs) for most of the applications. There exist many factors for higher energy consumption in WSNs. The purpose of this work is to increase the coverage area maintaining the minimum possible nodes or sensors. Design/methodology/approach This paper has proposed multilayer (ML) nodes deployment with distributed MAC (DS-MAC) in which nodes listen time is controlled based on communication of neighbors. Game theory optimization helps in addressing path loss constraints while selecting path toward base stations (BS). Findings The simulation is carried out using NS-2.35, and it shows better performance in ML DS-MAC compared to random topology in DS-MAC with same number of BS. The proposed method improves performance of network in terms of energy consumption, network lifetime and better throughput. Research limitations/implications Energy consumption is the major problem in WSNs and for which there exist many reasons, and many approaches are being proposed by researchers based on application in which WSN is used. Node mobility, topology, multitier and ML deployment and path loss constraints are some of the concerns in WSNs. Practical implications Game theory is used in different situations like countries whose army race, business firms that are competing, animals generally fighting for prey, political parties competing for vote, penalty kicks for the players in football and so on. Social implications WSNs find applications in surveillance, monitoring, inspections for wild life, sea life, underground pipes and so on. Originality/value Game theory optimization helps in addressing path loss constraints while selecting path toward BS.
{"title":"Multilayer DS-MAC with game theory optimization","authors":"S. Radha, G. Bala, P. Nagabushanam","doi":"10.1108/cw-08-2020-0197","DOIUrl":"https://doi.org/10.1108/cw-08-2020-0197","url":null,"abstract":"\u0000Purpose\u0000Energy is the major concern in wireless sensor networks (WSNs) for most of the applications. There exist many factors for higher energy consumption in WSNs. The purpose of this work is to increase the coverage area maintaining the minimum possible nodes or sensors.\u0000\u0000\u0000Design/methodology/approach\u0000This paper has proposed multilayer (ML) nodes deployment with distributed MAC (DS-MAC) in which nodes listen time is controlled based on communication of neighbors. Game theory optimization helps in addressing path loss constraints while selecting path toward base stations (BS).\u0000\u0000\u0000Findings\u0000The simulation is carried out using NS-2.35, and it shows better performance in ML DS-MAC compared to random topology in DS-MAC with same number of BS. The proposed method improves performance of network in terms of energy consumption, network lifetime and better throughput.\u0000\u0000\u0000Research limitations/implications\u0000Energy consumption is the major problem in WSNs and for which there exist many reasons, and many approaches are being proposed by researchers based on application in which WSN is used. Node mobility, topology, multitier and ML deployment and path loss constraints are some of the concerns in WSNs.\u0000\u0000\u0000Practical implications\u0000Game theory is used in different situations like countries whose army race, business firms that are competing, animals generally fighting for prey, political parties competing for vote, penalty kicks for the players in football and so on.\u0000\u0000\u0000Social implications\u0000WSNs find applications in surveillance, monitoring, inspections for wild life, sea life, underground pipes and so on.\u0000\u0000\u0000Originality/value\u0000Game theory optimization helps in addressing path loss constraints while selecting path toward BS.\u0000","PeriodicalId":50693,"journal":{"name":"Circuit World","volume":" ","pages":""},"PeriodicalIF":0.9,"publicationDate":"2021-07-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"48458360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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