Purpose This paper aims to investigate the singular Hopf bifurcation and mixed mode oscillations (MMOs) in the perturbed Bonhoeffer-van der Pol (BVP) circuit. There is a singular periodic orbit constructed by the switching between the stable focus and large amplitude relaxation cycles. Using a generalized fast/slow analysis, the authors show the generation mechanism of two distinct kinds of MMOs. Design/methodology/approach The parametric modulation can be used to generate complicated dynamics. The BVP circuit is constructed as an example for second-order differential equation with periodic perturbation. Then the authors draw the bifurcation parameter diagram in terms of a containing two attractive regions, i.e. the stable relaxation cycle and the stable focus. The transition mechanism and characteristic features are investigated intensively by one-fast/two-slow analysis combined with bifurcation theory. Findings Periodic perturbation can suppress nonlinear circuit dynamic to a singular periodic orbit. The combination of these small oscillations with the large amplitude oscillations that occur due to canard cycles yields such MMOs. The results connect the theory of the singular Hopf bifurcation enabling easier calculations of where the oscillations occur. Originality/value By treating the perturbation as the second slow variable, the authors obtain that the MMOs are due to the canards in a supercritical case or in a subcritical case. This study can reveal the transition mechanism for multi-time scale characteristics in perturbed circuit. The information gained from such results can be extended to periodically perturbed circuits.
目的研究微扰Bonhoeffer-van der Pol (BVP)电路中的Hopf奇异分岔和混合模振荡(MMOs)。通过稳定焦点和大振幅弛豫循环的切换，形成了一个奇异周期轨道。作者通过快速/慢速分析，展示了两种不同类型mmo的生成机制。设计/方法/途径参数调制可用于生成复杂的动力学。构造了具有周期扰动的二阶微分方程的BVP电路。然后绘制了包含稳定松弛循环和稳定焦点两个吸引区域的分岔参数图。采用一快两慢分析方法，结合分岔理论，深入研究了其跃迁机理和特征。发现周期扰动可以抑制非线性电路动态到奇异周期轨道。这些小振荡与鸭式循环引起的大振幅振荡相结合，产生了这样的mmo。结果与奇异Hopf分岔理论相联系，使振荡发生位置的计算更加容易。独创性/价值通过将扰动作为第二个慢变量，作者得出了在超临界情况下或在亚临界情况下，模态偏差是由鸭翼引起的。该研究揭示了微扰电路多时间尺度特性的过渡机制。从这样的结果中获得的信息可以扩展到周期性摄动电路。
{"title":"Canard-induced mixed mode oscillations as a mechanism for the Bonhoeffer-van der Pol circuit under parametric perturbation","authors":"Yue Yu, Cong Zhang, Zhenyu Chen, Zhengdi Zhang","doi":"10.1108/cw-07-2020-0132","DOIUrl":"https://doi.org/10.1108/cw-07-2020-0132","url":null,"abstract":"\u0000Purpose\u0000This paper aims to investigate the singular Hopf bifurcation and mixed mode oscillations (MMOs) in the perturbed Bonhoeffer-van der Pol (BVP) circuit. There is a singular periodic orbit constructed by the switching between the stable focus and large amplitude relaxation cycles. Using a generalized fast/slow analysis, the authors show the generation mechanism of two distinct kinds of MMOs.\u0000\u0000\u0000Design/methodology/approach\u0000The parametric modulation can be used to generate complicated dynamics. The BVP circuit is constructed as an example for second-order differential equation with periodic perturbation. Then the authors draw the bifurcation parameter diagram in terms of a containing two attractive regions, i.e. the stable relaxation cycle and the stable focus. The transition mechanism and characteristic features are investigated intensively by one-fast/two-slow analysis combined with bifurcation theory.\u0000\u0000\u0000Findings\u0000Periodic perturbation can suppress nonlinear circuit dynamic to a singular periodic orbit. The combination of these small oscillations with the large amplitude oscillations that occur due to canard cycles yields such MMOs. The results connect the theory of the singular Hopf bifurcation enabling easier calculations of where the oscillations occur.\u0000\u0000\u0000Originality/value\u0000By treating the perturbation as the second slow variable, the authors obtain that the MMOs are due to the canards in a supercritical case or in a subcritical case. This study can reveal the transition mechanism for multi-time scale characteristics in perturbed circuit. The information gained from such results can be extended to periodically perturbed circuits.\u0000","PeriodicalId":50693,"journal":{"name":"Circuit World","volume":" ","pages":""},"PeriodicalIF":0.9,"publicationDate":"2021-12-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"44927889","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Lalléchère, J. Nebhen, Yang Liu, George Chan, G. Fontgalland, W. Rahajandraibe, F. Wan, B. Ravelo
Purpose The purpose of this paper is to study, a bridged-T topology with inductorless passive network used as a bandpass (BP) negative group delay (NGD) function. Design/methodology/approach The BP NGD topology under study is composed of an inductorless passive resistive capacitive network. The circuit analysis is elaborated from the equivalent impedance matrix. Then, the analytical model of the C-shunt bridged-T topology voltage transfer function is established. The BP NGD analysis of the considered topology is developed in function of the bridged-T parameters. The NGD properties and characterizations of the proposed topology are analytically expressed. Moreover, the relevance of the BP NGD theory is verified with the design and fabrication of surface mounted device components-based proof-of-concept (PoC). Findings From measurement results, the BP NGD network with −151 ns at the center frequency of 1 MHz over −6.6 dB attenuation is in very good agreement with the C-shunt bridged-T PoC. Originality/value This paper develops a mathematical modeling theory and measurement of a C-shunt bridged-T network circuit.
本文的目的是研究一种无电感无源网络的桥接t拓扑作为带通(BP)负群延迟(NGD)函数。所研究的BP NGD拓扑由无电感无源电阻容性网络组成。从等效阻抗矩阵出发对电路进行了分析。然后，建立了c -并联桥- t拓扑电压传递函数的解析模型。所考虑的拓扑的BP NGD分析是在桥接- t参数的函数中发展起来的。本文对所提出的拓扑结构的NGD性质和特征进行了解析表达。此外，BP NGD理论的相关性通过基于表面贴装器件组件的概念验证(PoC)的设计和制造得到验证。从测量结果来看，中心频率为1mhz的- 151 ns BP NGD网络在- 6.6 dB衰减下与c分流桥接- t PoC非常吻合。本文提出了c -并联桥接- t网络电路的数学建模理论和测量方法。
{"title":"Suitability of passive RC-network-based inductorless bridged-T as a bandpass NGD circuit","authors":"S. Lalléchère, J. Nebhen, Yang Liu, George Chan, G. Fontgalland, W. Rahajandraibe, F. Wan, B. Ravelo","doi":"10.1108/cw-06-2021-0163","DOIUrl":"https://doi.org/10.1108/cw-06-2021-0163","url":null,"abstract":"\u0000Purpose\u0000The purpose of this paper is to study, a bridged-T topology with inductorless passive network used as a bandpass (BP) negative group delay (NGD) function.\u0000\u0000\u0000Design/methodology/approach\u0000The BP NGD topology under study is composed of an inductorless passive resistive capacitive network. The circuit analysis is elaborated from the equivalent impedance matrix. Then, the analytical model of the C-shunt bridged-T topology voltage transfer function is established. The BP NGD analysis of the considered topology is developed in function of the bridged-T parameters. The NGD properties and characterizations of the proposed topology are analytically expressed. Moreover, the relevance of the BP NGD theory is verified with the design and fabrication of surface mounted device components-based proof-of-concept (PoC).\u0000\u0000\u0000Findings\u0000From measurement results, the BP NGD network with −151 ns at the center frequency of 1 MHz over −6.6 dB attenuation is in very good agreement with the C-shunt bridged-T PoC.\u0000\u0000\u0000Originality/value\u0000This paper develops a mathematical modeling theory and measurement of a C-shunt bridged-T network circuit.\u0000","PeriodicalId":50693,"journal":{"name":"Circuit World","volume":" ","pages":""},"PeriodicalIF":0.9,"publicationDate":"2021-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"44467167","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Purpose This paper aims to offer a hybrid genetic algorithm and the ant colony optimization (GA-ACO) algorithm for task mapping and resource management. The paper aims to reduce the makespan and total response time in fog computing- medical cyber-physical system (FC-MCPS). Design/methodology/approach Swift progress in today’s medical technologies has resulted in a new kind of health-care tool and therapy techniques like the MCPS. The MCPS is a smart and reliable mechanism of entrenched clinical equipment applied to check and manage the patients’ physiological condition. However, the extensive-delay connections among cloud data centers and medical devices are so problematic. FC has been introduced to handle these problems. It includes a group of near-user edge tools named fog points that are collaborating until executing the processing tasks, such as running applications, reducing the utilization of a momentous bulk of data and distributing the messages. Task mapping is a challenging problem for managing fog-based MCPS. As mapping is an non-deterministic pol ynomial-time-hard optimization issue, this paper has proposed a procedure depending on the hybrid GA-ACO to solve this problem in FC-MCPS. ACO and GA, that is applied in their standard formulation and combined as hybrid meta-heuristics to solve the problem. As such ACO-GA is a hybrid meta-heuristic using ACO as the main approach and GA as the local search. GA-ACO is a memetic algorithm using GA as the main approach and ACO as local search. Findings MATLAB is used to simulate the proposed method and compare it to the ACO and MACO algorithms. The experimental results have validated the improvement in makespan, which makes the method a suitable one for use in medical and real-time systems. Research limitations/implications The proposed method can achieve task mapping in FC-MCPS by attaining high efficiency, which is very significant in practice. Practical implications The proposed approach can achieve the goal of task scheduling in FC-MCPS by attaining the highest total computational efficiency, which is very significant in practice. Originality/value This research proposes a GA-ACO algorithm to solve the task mapping in FC-MCPS. It is the most significant originality of the paper.
{"title":"A new approach for task managing in the fog-based medical cyber-physical systems using a hybrid algorithm","authors":"Jiuhong Yu, Mengfei Wang, Yu J.H., Seyedeh Maryam Arefzadeh","doi":"10.1108/cw-03-2020-0035","DOIUrl":"https://doi.org/10.1108/cw-03-2020-0035","url":null,"abstract":"\u0000Purpose\u0000This paper aims to offer a hybrid genetic algorithm and the ant colony optimization (GA-ACO) algorithm for task mapping and resource management. The paper aims to reduce the makespan and total response time in fog computing- medical cyber-physical system (FC-MCPS).\u0000\u0000\u0000Design/methodology/approach\u0000Swift progress in today’s medical technologies has resulted in a new kind of health-care tool and therapy techniques like the MCPS. The MCPS is a smart and reliable mechanism of entrenched clinical equipment applied to check and manage the patients’ physiological condition. However, the extensive-delay connections among cloud data centers and medical devices are so problematic. FC has been introduced to handle these problems. It includes a group of near-user edge tools named fog points that are collaborating until executing the processing tasks, such as running applications, reducing the utilization of a momentous bulk of data and distributing the messages. Task mapping is a challenging problem for managing fog-based MCPS. As mapping is an non-deterministic pol ynomial-time-hard optimization issue, this paper has proposed a procedure depending on the hybrid GA-ACO to solve this problem in FC-MCPS. ACO and GA, that is applied in their standard formulation and combined as hybrid meta-heuristics to solve the problem. As such ACO-GA is a hybrid meta-heuristic using ACO as the main approach and GA as the local search. GA-ACO is a memetic algorithm using GA as the main approach and ACO as local search.\u0000\u0000\u0000Findings\u0000MATLAB is used to simulate the proposed method and compare it to the ACO and MACO algorithms. The experimental results have validated the improvement in makespan, which makes the method a suitable one for use in medical and real-time systems.\u0000\u0000\u0000Research limitations/implications\u0000The proposed method can achieve task mapping in FC-MCPS by attaining high efficiency, which is very significant in practice.\u0000\u0000\u0000Practical implications\u0000The proposed approach can achieve the goal of task scheduling in FC-MCPS by attaining the highest total computational efficiency, which is very significant in practice.\u0000\u0000\u0000Originality/value\u0000This research proposes a GA-ACO algorithm to solve the task mapping in FC-MCPS. It is the most significant originality of the paper.\u0000","PeriodicalId":50693,"journal":{"name":"Circuit World","volume":" ","pages":""},"PeriodicalIF":0.9,"publicationDate":"2021-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"46767012","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Purpose The conventional two-level inverter suffers from harmonics, higher direct current (DC) link voltage requirement, higher dv/dt and heating of the rotor. This study aims to overcome by using a multilevel inverter for brushless DC (BLDC) drive. Design/methodology/approach This paper presents a comparative analysis of the conventional two-level and three-level multilevel inverter for electric vehicle (EV) application using BLDC drive. Findings A three-level Active Neutral Point Clamped Multilevel inverter (ANPCMLI) is proposed in this paper which provides DC link voltage control. Simulation studies of the multilevel inverter and BLDC motor is carried out in MATLAB. Originality/value The ANPCMLI fed BLDC simulation results shows that there is the significant reduction in the BLDC motor torque ripple, switching stress and harmonic distortion in the BLDC motor fed ANPCMLI compared to the conventional two-level inverter. A prototype of ANPCMLI fed BLDC drive along with field programmable gate array (FPGA) control is built and MATLAB simulation results are verified experimentally.
{"title":"Comparative analysis of two-level and three-level multilevel inverter for electric vehicle application using BLDC motor drive","authors":"Bharathi Sankar Ammaiyappan, Seyezhai Ramalingam","doi":"10.1108/cw-08-2020-0186","DOIUrl":"https://doi.org/10.1108/cw-08-2020-0186","url":null,"abstract":"\u0000Purpose\u0000The conventional two-level inverter suffers from harmonics, higher direct current (DC) link voltage requirement, higher dv/dt and heating of the rotor. This study aims to overcome by using a multilevel inverter for brushless DC (BLDC) drive.\u0000\u0000\u0000Design/methodology/approach\u0000This paper presents a comparative analysis of the conventional two-level and three-level multilevel inverter for electric vehicle (EV) application using BLDC drive.\u0000\u0000\u0000Findings\u0000A three-level Active Neutral Point Clamped Multilevel inverter (ANPCMLI) is proposed in this paper which provides DC link voltage control. Simulation studies of the multilevel inverter and BLDC motor is carried out in MATLAB.\u0000\u0000\u0000Originality/value\u0000The ANPCMLI fed BLDC simulation results shows that there is the significant reduction in the BLDC motor torque ripple, switching stress and harmonic distortion in the BLDC motor fed ANPCMLI compared to the conventional two-level inverter. A prototype of ANPCMLI fed BLDC drive along with field programmable gate array (FPGA) control is built and MATLAB simulation results are verified experimentally.\u0000","PeriodicalId":50693,"journal":{"name":"Circuit World","volume":" ","pages":""},"PeriodicalIF":0.9,"publicationDate":"2021-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"44073218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Purpose This paper aims to propose a bidirectional hidden converter (BHC)-based three-phase DC–AC conversion for energy storage application. BHC is the new concept to vary an energy storage device voltage into wide range. Hidden converter power loss and power rating are reduced by using zero-sequence injection-based carrier-based pulse-width modulation (CBPWM) strategy. Design/methodology/approach By using this control strategy, a BHC processes only little amount of power during double-stage conversion, mostly during direct or single-stage conversion of the three-phase three-port converter (TPTPC) only processing the maximum power. Findings TPTPC consists of two sets of positive group switches for inversion process, one set of switches is regular inverter switches called vertical positive group switches, and the second set is anti-series switches, which are horizontally connected for direct or single-stage conversion. Originality/value Characteristics, principles and implementations of proposed DC–AC 3Ø conversion system and its PWM strategy are analyzed. Through experimental outputs, the effectiveness and viability of the proposed solutions are validated.
{"title":"TPTPC and BHC integrated grid connected energy storage system for power loss reduction","authors":"S. Krishnan, P. Pandi, S. Mopidevi","doi":"10.1108/cw-01-2021-0006","DOIUrl":"https://doi.org/10.1108/cw-01-2021-0006","url":null,"abstract":"\u0000Purpose\u0000This paper aims to propose a bidirectional hidden converter (BHC)-based three-phase DC–AC conversion for energy storage application. BHC is the new concept to vary an energy storage device voltage into wide range. Hidden converter power loss and power rating are reduced by using zero-sequence injection-based carrier-based pulse-width modulation (CBPWM) strategy.\u0000\u0000\u0000Design/methodology/approach\u0000By using this control strategy, a BHC processes only little amount of power during double-stage conversion, mostly during direct or single-stage conversion of the three-phase three-port converter (TPTPC) only processing the maximum power.\u0000\u0000\u0000Findings\u0000TPTPC consists of two sets of positive group switches for inversion process, one set of switches is regular inverter switches called vertical positive group switches, and the second set is anti-series switches, which are horizontally connected for direct or single-stage conversion.\u0000\u0000\u0000Originality/value\u0000Characteristics, principles and implementations of proposed DC–AC 3Ø conversion system and its PWM strategy are analyzed. Through experimental outputs, the effectiveness and viability of the proposed solutions are validated.\u0000","PeriodicalId":50693,"journal":{"name":"Circuit World","volume":" ","pages":""},"PeriodicalIF":0.9,"publicationDate":"2021-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"41655365","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Faheem, Shun'an Zhong, Muhammad Basit Azeem, Xinghua Wang
Purpose Successive Approximation Register-Analog to Digital Converter (SAR-ADC) has been achieved notable technological advancement since the past couple of decades. However, it’s not accurate in terms of size, energy, and time consumption. Many projects proposed to make it energy efficient and time-efficient. Such designs are unable to deliver two parallel outputs. Design/methodology/approach To this end, this study introduced an ultra-low-power circuitry for the two blocks (bootstrap and comparator) of 11-bit SAR-ADC. The bootstrap has three sub-parts: back-bone, left-wing and right-wing, named as bat-bootstrap. The comparator block has a circuitry of the two comparators and an amplifier, named as comp-lifier. In a bat-bootstrap, the authors plant two capacitors in the back-bone block to avoid the patristic capacitance. The switching system of the proposed design highly synchronized with the short pulses of the clocks for high accuracy. This study simulates the proposed circuits using a built-in Cadence 90 nm Complementary Metal Oxide Semiconductor library. Findings The results suggested that the response time of two bat-bootstrap wings and comp-lifier are 80 ns, 120 ns, and 90 ns, respectively. The supply voltage is 0.7 V, wherever the power consumption of bat-bootstrap, comp-lifier and SAR-ADC are 0.3561µW, 0.257µW and 35.76µW, respectively. Signal to Noise and Distortion Ratio is 65 dB with 5 MHz frequency and 25 KS/s sampling rate. The input referred noise of the amplifier and two comparators are 98µVrms, 224µVrms and 224µVrms, respectively. Originality/value Two basic circuit blocks for SAR-ADC are introduced, which fulfill the duality approach and delivered two outputs with highly synchronized clock pulses. The circuit sharing concept introduced for the high performance SAR-ADCs.
{"title":"Energy and time-efficient circuitry of bat-bootstrap and comp-lifier for ultra-low power SAR-ADC","authors":"M. Faheem, Shun'an Zhong, Muhammad Basit Azeem, Xinghua Wang","doi":"10.1108/cw-11-2020-0312","DOIUrl":"https://doi.org/10.1108/cw-11-2020-0312","url":null,"abstract":"\u0000Purpose\u0000Successive Approximation Register-Analog to Digital Converter (SAR-ADC) has been achieved notable technological advancement since the past couple of decades. However, it’s not accurate in terms of size, energy, and time consumption. Many projects proposed to make it energy efficient and time-efficient. Such designs are unable to deliver two parallel outputs.\u0000\u0000\u0000Design/methodology/approach\u0000To this end, this study introduced an ultra-low-power circuitry for the two blocks (bootstrap and comparator) of 11-bit SAR-ADC. The bootstrap has three sub-parts: back-bone, left-wing and right-wing, named as bat-bootstrap. The comparator block has a circuitry of the two comparators and an amplifier, named as comp-lifier. In a bat-bootstrap, the authors plant two capacitors in the back-bone block to avoid the patristic capacitance. The switching system of the proposed design highly synchronized with the short pulses of the clocks for high accuracy. This study simulates the proposed circuits using a built-in Cadence 90 nm Complementary Metal Oxide Semiconductor library.\u0000\u0000\u0000Findings\u0000The results suggested that the response time of two bat-bootstrap wings and comp-lifier are 80 ns, 120 ns, and 90 ns, respectively. The supply voltage is 0.7 V, wherever the power consumption of bat-bootstrap, comp-lifier and SAR-ADC are 0.3561µW, 0.257µW and 35.76µW, respectively. Signal to Noise and Distortion Ratio is 65 dB with 5 MHz frequency and 25 KS/s sampling rate. The input referred noise of the amplifier and two comparators are 98µVrms, 224µVrms and 224µVrms, respectively.\u0000\u0000\u0000Originality/value\u0000Two basic circuit blocks for SAR-ADC are introduced, which fulfill the duality approach and delivered two outputs with highly synchronized clock pulses. The circuit sharing concept introduced for the high performance SAR-ADCs.\u0000","PeriodicalId":50693,"journal":{"name":"Circuit World","volume":" ","pages":""},"PeriodicalIF":0.9,"publicationDate":"2021-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43165439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Purpose The purpose of this paper is to design multiplexers (MUXs) based on ternary half subtractor and full subtractor using carbon nanotube field-effect transistors. Design/methodology/approach Conventionally, the binary logic functions are developed by using the binary decision diagram (BDD) systems. Each node in BDD is replaced by 2:1 MUX to implement the digital circuits. Similarly, in the ternary decision diagram, each node has to be replaced by 3:1 MUX. In this paper, ternary transformed BDD is used to design the ternary subtractors using 2:1 MUXs. Findings The performance of the proposed ternary half subtractor and full subtractor using the 2:1 MUX are compared with the 3:1 MUX-based ternary circuits. It has been observed that the delay, power and power delay product values are reduced, respectively, by 67.6%, 84.3%, 94.9% for half subtractor and 67.7%, 70.1%, 90.3% for full subtractor. From the Monte Carlo simulations, it is observed that the propagation delay and power dissipation of the proposed subtractors are increased by increasing the channel length due to process variations. The stability test is also performed and observed that the stability increases as the channel length and diameter are increased. Originality/value The proposed half subtractor and full subtractor show better performance over the existing subtractors.
{"title":"Design of ternary subtractor using multiplexers","authors":"Tulasi Naga Jyothi Kolanti, Vasundhara Patel K.S.","doi":"10.1108/cw-05-2020-0096","DOIUrl":"https://doi.org/10.1108/cw-05-2020-0096","url":null,"abstract":"\u0000Purpose\u0000The purpose of this paper is to design multiplexers (MUXs) based on ternary half subtractor and full subtractor using carbon nanotube field-effect transistors.\u0000\u0000\u0000Design/methodology/approach\u0000Conventionally, the binary logic functions are developed by using the binary decision diagram (BDD) systems. Each node in BDD is replaced by 2:1 MUX to implement the digital circuits. Similarly, in the ternary decision diagram, each node has to be replaced by 3:1 MUX. In this paper, ternary transformed BDD is used to design the ternary subtractors using 2:1 MUXs.\u0000\u0000\u0000Findings\u0000The performance of the proposed ternary half subtractor and full subtractor using the 2:1 MUX are compared with the 3:1 MUX-based ternary circuits. It has been observed that the delay, power and power delay product values are reduced, respectively, by 67.6%, 84.3%, 94.9% for half subtractor and 67.7%, 70.1%, 90.3% for full subtractor. From the Monte Carlo simulations, it is observed that the propagation delay and power dissipation of the proposed subtractors are increased by increasing the channel length due to process variations. The stability test is also performed and observed that the stability increases as the channel length and diameter are increased.\u0000\u0000\u0000Originality/value\u0000The proposed half subtractor and full subtractor show better performance over the existing subtractors.\u0000","PeriodicalId":50693,"journal":{"name":"Circuit World","volume":" ","pages":""},"PeriodicalIF":0.9,"publicationDate":"2021-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"48766692","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Purpose Control-signal-to-output-voltage transfer function of the conventional boost converter has at least one right-half plane zero (RHPZ) in the continuous conduction mode which can restrict the open-loop bandwidth of the converter. This problem can complicate the control design for the load voltage regulation and conversely, impact on the stability of the closed-loop system. To remove this positive zero and improve the dynamic performance, this paper aims to suggest a novel boost topology with a step-up voltage gain by developing the circuit diagram of a conventional boost converter. Design/methodology/approach Using a transformer, two different pathways are provided for a classical boost circuit. Hence, the effect of the RHPZ can be easily canceled and the voltage gain can be enhanced which provides conditions for achieving a smaller working duty cycle and reducing the voltage stress of the power switch. Using this technique makes it possible to achieve a good dynamic response compared to the classical boost converter. Findings The observations show that the phase margin of the proposed boost converter can be adequately improved, its bandwidth is largely increased, due to its minimum-phase structure through RHPZ cancellation. It is suitable for fast dynamic response applications such as micro-inverters and fuel cells. Originality/value The introduced method is analytically studied via determining the state-space model and necessary criteria are obtained to achieve a minimum-phase structure. Practical observations of a constructed prototype for the voltage conversion from 24 V to 100 V and various load conditions are shown.
{"title":"A new technique for right half plane zero elimination from dynamics of a boost converter using magnetic coupling concept","authors":"A. Goudarzian","doi":"10.1108/cw-01-2021-0013","DOIUrl":"https://doi.org/10.1108/cw-01-2021-0013","url":null,"abstract":"\u0000Purpose\u0000Control-signal-to-output-voltage transfer function of the conventional boost converter has at least one right-half plane zero (RHPZ) in the continuous conduction mode which can restrict the open-loop bandwidth of the converter. This problem can complicate the control design for the load voltage regulation and conversely, impact on the stability of the closed-loop system. To remove this positive zero and improve the dynamic performance, this paper aims to suggest a novel boost topology with a step-up voltage gain by developing the circuit diagram of a conventional boost converter.\u0000\u0000\u0000Design/methodology/approach\u0000Using a transformer, two different pathways are provided for a classical boost circuit. Hence, the effect of the RHPZ can be easily canceled and the voltage gain can be enhanced which provides conditions for achieving a smaller working duty cycle and reducing the voltage stress of the power switch. Using this technique makes it possible to achieve a good dynamic response compared to the classical boost converter.\u0000\u0000\u0000Findings\u0000The observations show that the phase margin of the proposed boost converter can be adequately improved, its bandwidth is largely increased, due to its minimum-phase structure through RHPZ cancellation. It is suitable for fast dynamic response applications such as micro-inverters and fuel cells.\u0000\u0000\u0000Originality/value\u0000The introduced method is analytically studied via determining the state-space model and necessary criteria are obtained to achieve a minimum-phase structure. Practical observations of a constructed prototype for the voltage conversion from 24 V to 100 V and various load conditions are shown.\u0000","PeriodicalId":50693,"journal":{"name":"Circuit World","volume":" ","pages":""},"PeriodicalIF":0.9,"publicationDate":"2021-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"46511705","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Purpose The purpose of this paper is to design a suitable guard trace to reduce the electromagentic interference between two closely spaced high frequency transmission lines. A novel cross-shaped resonator combined via fence is passed down to alleviate far-end and near-end crosstalk (NEXT) in tightly coupled high-speed transmission lines. The distance between the adjacent transmission lines is increased stepwise as a function of trace width. Design/methodology/approach A rectangular-shaped resonator via fence is connected by a guard trace has been proposed to overcome the coupling between the traces that is separated by 2 W. Similarly, by creating a cross-shaped resonator via fence connected by guard trace that reduces the spacing further by 1.5 W. Findings A tightly coupled transmission line structure that needs separation by a designed unit cell structure. Further research needs to be conducted to improve the NEXT, far-end crosstalk (FEXT) and spacing between the transmission lines. Originality/value This study portrays a novel method that combines the resonators via fence with a minimum spacing between the tightly coupled transmission lines which reduce the NEXT and FEXT; thereby reducing the size of the routing area. The resultant test structures are characterized at high frequencies using time domain and frequency domain analysis. The following scattering parameters such as insertion loss, NEXT and FEXT of the proposed method are measured as 1.504 dB, >30 dB and >20 dB, respectively.
{"title":"Crosstalk reduction using novel cross-shaped resonators with via fence in high-frequency transmission lines","authors":"Y. V., G. Mohammed, M. Kanagasabai","doi":"10.1108/cw-04-2021-0099","DOIUrl":"https://doi.org/10.1108/cw-04-2021-0099","url":null,"abstract":"\u0000Purpose\u0000The purpose of this paper is to design a suitable guard trace to reduce the electromagentic interference between two closely spaced high frequency transmission lines. A novel cross-shaped resonator combined via fence is passed down to alleviate far-end and near-end crosstalk (NEXT) in tightly coupled high-speed transmission lines. The distance between the adjacent transmission lines is increased stepwise as a function of trace width.\u0000\u0000\u0000Design/methodology/approach\u0000A rectangular-shaped resonator via fence is connected by a guard trace has been proposed to overcome the coupling between the traces that is separated by 2 W. Similarly, by creating a cross-shaped resonator via fence connected by guard trace that reduces the spacing further by 1.5 W.\u0000\u0000\u0000Findings\u0000A tightly coupled transmission line structure that needs separation by a designed unit cell structure. Further research needs to be conducted to improve the NEXT, far-end crosstalk (FEXT) and spacing between the transmission lines.\u0000\u0000\u0000Originality/value\u0000This study portrays a novel method that combines the resonators via fence with a minimum spacing between the tightly coupled transmission lines which reduce the NEXT and FEXT; thereby reducing the size of the routing area. The resultant test structures are characterized at high frequencies using time domain and frequency domain analysis. The following scattering parameters such as insertion loss, NEXT and FEXT of the proposed method are measured as 1.504 dB, >30 dB and >20 dB, respectively.\u0000","PeriodicalId":50693,"journal":{"name":"Circuit World","volume":" ","pages":""},"PeriodicalIF":0.9,"publicationDate":"2021-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"45598296","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Purpose Propagation characteristics of millimeter wave (mmW) frequencies that are being explored for implementing 5G network are quite different from sub 3GHz frequencies in which 4G network is operating, and hence antenna design for mmW 5G network is going to be significantly different. The purpose of this paper is to bring forth the unique challenges and opportunities of planar antenna design for mmW 5G network. Design/methodology/approach A lot of notable contemporary work has been investigated for this study and reported in this paper. A comparison of 4G and 5G technologies has been carried out to understand the difference between the air interface of two technologies that governs the antenna design. Important research gaps found after collating the work already done in the field have been bullet pointed for the use by many researchers working in this direction. Findings Several antenna design considerations have been laid out by the authors of this work, and it has been claimed that mmW 5G antenna design must satisfy these design considerations. In addition, prominent research gaps have been identified and thoroughly discussed. Originality/value As research in the field of mmW antenna design for 5G applications is still evolving, a lot of work is currently being done in this area. This study can prove to be important in understanding different challenges, opportunities and current state-of-art in the field of mmW planar antenna design for 5G cellular communication.
{"title":"Design considerations for implementation of planar antennas for millimeter wave (mmW) 5G network: a review","authors":"Sagar Juneja, R. Pratap, Rajnish Sharma","doi":"10.1108/cw-09-2020-0221","DOIUrl":"https://doi.org/10.1108/cw-09-2020-0221","url":null,"abstract":"\u0000Purpose\u0000Propagation characteristics of millimeter wave (mmW) frequencies that are being explored for implementing 5G network are quite different from sub 3GHz frequencies in which 4G network is operating, and hence antenna design for mmW 5G network is going to be significantly different. The purpose of this paper is to bring forth the unique challenges and opportunities of planar antenna design for mmW 5G network.\u0000\u0000\u0000Design/methodology/approach\u0000A lot of notable contemporary work has been investigated for this study and reported in this paper. A comparison of 4G and 5G technologies has been carried out to understand the difference between the air interface of two technologies that governs the antenna design. Important research gaps found after collating the work already done in the field have been bullet pointed for the use by many researchers working in this direction.\u0000\u0000\u0000Findings\u0000Several antenna design considerations have been laid out by the authors of this work, and it has been claimed that mmW 5G antenna design must satisfy these design considerations. In addition, prominent research gaps have been identified and thoroughly discussed.\u0000\u0000\u0000Originality/value\u0000As research in the field of mmW antenna design for 5G applications is still evolving, a lot of work is currently being done in this area. This study can prove to be important in understanding different challenges, opportunities and current state-of-art in the field of mmW planar antenna design for 5G cellular communication.\u0000","PeriodicalId":50693,"journal":{"name":"Circuit World","volume":" ","pages":""},"PeriodicalIF":0.9,"publicationDate":"2021-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"45652599","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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