ACM Journal on Emerging Technologies in Computing Systems最新文献

In this paper, a novel and highly efficient inexact Full Adder cell by exploiting two logic styles including conventional CMOS (C-COMS) and pass transistor logic (PTL) are presented. The so-called carbon nanotube field-effect transistor (CNFET) technology is used to implement circuits at the transistor level. To justify the efficiency of our design, extensive simulations are performed at the transistor level as well as application level. Transistor-level simulations which are carried out by the HSPICE 2008 tool, demonstrate at least 12% higher performance in terms of power-delay-area product (PDAP) of the proposed circuit compared to the latest designs. At the application level, by using the MATLAB tool, inexact Full Adders are employed in the structure of the ripple carry adder (RCA) that is applied in motion and edge detection algorithms. Computer simulation results confirm the appropriate quality of the output images in terms of the peak signal-to-noise ratio (PSNR) and structural similarity (SSIM) criteria. At last, to make a compromise between hardware and application level parameters, the power-delay-area-1/PSNR product (PDAPP) and power-delay-area-1/SSIM product (PDASP) are considered as figures of merit. The proposed circuit shows remarkable improvement from the PDAPP and PDASP points of view compared to its counterparts.

Spiking neural networks (SNNs) are brain-inspired event-driven models of computation with promising ultra-low energy dissipation. Rich network dynamics emergent in recurrent spiking neural networks (R-SNNs) can form temporally based memory, offering great potential in processing complex spatiotemporal data. However, recurrence in network connectivity produces tightly coupled data dependency in both space and time, rendering hardware acceleration of R-SNNs challenging. We present the first work to exploit spatiotemporal parallelisms to accelerate the R-SNN-based inference on systolic arrays using an architecture called SaARSP. We decouple the processing of feedforward synaptic connections from that of recurrent connections to allow for the exploitation of parallelisms across multiple time points. We propose a novel time window size optimization (TWSO) technique, to further explore the temporal granularity of the proposed decoupling in terms of optimal time window size and reconfiguration of the systolic array considering layer-dependent connectivity to boost performance. Stationary dataflow and time window size are jointly optimized to trade off between weight data reuse and movements of partial sums, the two bottlenecks in latency and energy dissipation of the accelerator. The proposed systolic-array architecture offers a unifying solution to an acceleration of both feedforward and recurrent SNNs, and delivers 4,000X EDP improvement on average for different R-SNN benchmarks over a conventional baseline.

No abstract available.

Faster and cheaper computers have been constantly demanding technological and architectural improvements. However, current technology is suffering from three technology walls: leakage wall, reliability wall, and cost wall. Meanwhile, existing architecture performance is also saturating due to three well-known architecture walls: memory wall, power wall, and instruction-level parallelism (ILP) wall. Hence, a lot of novel technologies and architectures have been introduced and developed intensively. Our previous work has presented a comprehensive classification and broad overview of memory-centric computer architectures. In this article, we aim to discuss the most important classes of memory-centric architectures thoroughly and evaluate their advantages and disadvantages. Moreover, for each class, the article provides a comprehensive survey on memory-centric architectures available in the literature.

Three-Dimensional Integrated Circuit (3D IC) based on Through-Silicon-Via (TSV) has brought a drastic change in IC technology. Since TSVs connect different layers of 3D stacks, their proper functioning is an essential prerequisite for system operation. Therefore, testing of TSV is essential for 3D IC. In this article, we propose a cost-effective Built-In Self-Test (BIST) method to test the TSVs of a 3D IC. The test method aims at identifying single and multiple defective TSVs using low test time with small hardware overhead. Further, we introduce a BIST partitioning scheme to reduce the test time and hardware overhead for many TSVs. We also present EBIST, an extended-BIST, to enhance BIST reliability with the least hardware cost. The time cycle needed for testing is calculated and compared with previously proposed methods. The simulation result shows that the proposed BIST reduces the test time by 87% compared to prior works. Moreover, the approach yields reduced area as compared to existing test architecture.

Recently, spin-transfer torque magnetic cell (STT-mCell) has emerged as a promising spintronic device to be used in Computing-in-Memory (CIM) systems. However, it is challenging to guarantee the hardware security of STT-mCell-based all-spin circuits. In this work, we propose a novel Physical Unclonable Function (PUF) design for the STT-mCell-based all-spin circuit (All-Spin PUF) exploiting the unique manufacturing process variation (PV) on STT-mCell write latency. A methodology is used to select appropriate logic gates in the all-spin chip to generate a unique identification key. A linear feedback shift register (LFSR) initiates the All-Spin PUF and simultaneously generates a 64-bit signature at each clock cycle. Signature generation is stabilized using an automatic write-back technique. In addition, a masking scheme is applied for signature improvement. The uniqueness of the improved signature is 49.61%. With ± 20% supply voltage and 5°C to 105°C temperature variations, the All-Spin PUF shows a strong resiliency. In comparison with state-of-the-art PUFs, our approach can reduce hardware overhead effectively. Finally, the robustness of the All-Spin PUF against emerging modeling attacks is verified as well.

Phase-based ranging has been widely deployed in proximity detection scenarios including security-critical applications due to their low implementation complexity on existing transceivers. In this work, the security of multi-carrier phase-based ranging systems in a multipath propagation environment is investigated. We present a threat model that can successfully target any decreasing distance in different multipath environmental conditions rendering the phase-based ranging method insecure. We assess the feasibility of attacks in various attack scenarios through simulations using a multipath channel and demonstrate a simplified version of the attacker model implemented in hardware. We show that the attacker can spoof the measured distance to less than one meter when the devices are separated by 30 meters. The evaluation of possible countermeasures and their limitations for different threat models is performed.

In Analog Computing-in-Memory (CIM) neural network accelerators, analog-to-digital converters (ADCs) are required to convert the analog partial sums generated from a CIM array to digital values. The overhead from ADCs substantially degrades the energy efficiency of CIM accelerators so that previous works attempted to lower the ADC resolution considering the distribution of the partial sums. Despite the efforts, the required ADC resolution still remains relatively high. In this article, we propose the data-driven partial sum quantization scheme, which exhaustively searches for the optimal quantization range with little computational burden. We also report that analyzing the characteristics of the partial sum distributions at each layer gives an additional information to further reduce the ADC resolution compared to previous works that mostly used the characteristics of the partial sum distributions of the entire network. Based on the finer-level data-driven approach combined with retraining, we present a methodology for extreme partial-sum quantization. Experimental results show that the proposed method can reduce the ADC resolution to 2 to 3 bits for CIFAR-10 dataset, which is the smaller ADC bit resolution than any previous CIM-based NN accelerators.

Novel transmission schemes, enabled by recent advances in the fields of metamaterial (MTM), leaky-wave antenna (LWA) and directional modulation (DM), are proposed for enhancing the physical layer (PHY) security. MTM-LWAs, which offer compact, integrated, and cost-effective alternatives to the classic phased-array architectures, are particularly of interest for emerging wireless communication systems including Internet-of-Things. The proposed secure schemes are devised to accomplish the functionalities of directional modulation (DM) transmitters for orthogonal frequency-division multiplexing (OFDM) and non-contiguous OFDM transmissions, while enjoying the implementation benefits of MTM-LWAs. Specifically, transmitter architectures based on the idea of time-modulated MTM-LWA have been put forth as a promising solution for PHY security for the first time. The PHY security for the proposed schemes are investigated from the point of view of both passive and active attacks where an adversary aims to decode secret information and feed spurious data to the legitimate receiver, respectively. Numerical simulations reveal that even when the adversary employs sophisticated state-of-the-art deep learning based attacks, the proposed transmission schemes are resistant to these attacks and reliably guarantee system security.