Pub Date : 2010-01-08DOI: 10.1109/TCAPT.2009.2035514
Y. Maydanik, S. Vershinin, V. Pastukhov, Stephen Fried
Loop heat pipes (LHPs) are exceptionally efficient heat-transfer devices that employ a closed loop evaporation-condensation cycle that can be used to cool densely packed electronic systems that reject large quantities of heat, including computers and their central processing units (CPUs). Tests were carried out on miniature ammonia LHPs with a CPU thermal simulator using different ways of condenser cooling. The possibility of maintaining the cooled object temperatures between 40°C and 70°C with heat load changing from 100 to 320 W was demonstrated. Subsequent tests of these devices in a 1U computer with dual core advanced micro devices Opteron CPUs, dissipating between 95 and 120 W, have confirmed the advantages and heat transfer efficiency of LHP-based cooling systems used to cool CPU in 1U chassis.
{"title":"Loop Heat Pipes for Cooling Systems of Servers","authors":"Y. Maydanik, S. Vershinin, V. Pastukhov, Stephen Fried","doi":"10.1109/TCAPT.2009.2035514","DOIUrl":"https://doi.org/10.1109/TCAPT.2009.2035514","url":null,"abstract":"Loop heat pipes (LHPs) are exceptionally efficient heat-transfer devices that employ a closed loop evaporation-condensation cycle that can be used to cool densely packed electronic systems that reject large quantities of heat, including computers and their central processing units (CPUs). Tests were carried out on miniature ammonia LHPs with a CPU thermal simulator using different ways of condenser cooling. The possibility of maintaining the cooled object temperatures between 40°C and 70°C with heat load changing from 100 to 320 W was demonstrated. Subsequent tests of these devices in a 1U computer with dual core advanced micro devices Opteron CPUs, dissipating between 95 and 120 W, have confirmed the advantages and heat transfer efficiency of LHP-based cooling systems used to cool CPU in 1U chassis.","PeriodicalId":55013,"journal":{"name":"IEEE Transactions on Components and Packaging Technologies","volume":"33 1","pages":"416-423"},"PeriodicalIF":0.0,"publicationDate":"2010-01-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TCAPT.2009.2035514","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62519793","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-01DOI: 10.1109/TCAPT.2009.2020696
J. Ong, A. Tay, X. Zhang, V. Kripesh, Y. K. Lim, D. Yeo, K.C. Chan, J.B. Tan, L. Hsia, D. Sohn
The trend toward finer pitch and higher performance integrated circuit devices has driven the semiconductor industry to incorporate copper and low-k dielectric materials. However, the low-k materials have lower modulus and poorer adhesion compared to the common dielectric materials. Thus, thermomechanical failure is one of the major bottlenecks in the development of Cu/low-k larger-die flip chip packages. This paper describes the optimization of the structural design of Chartered's C65 nm 21 mm times 21 mm die size flip-chip ball grid array package incorporated with fully active and functional ninemetal Cu/low-k layers and 150 mum interconnect pitch. The lowk material used in this paper is nonporous SiCOH with a k value of 2.9. A parametric study using 2-D plane strain finite element analysis was performed to study the effect of various parameters on the reliability of the large-die package in order to arrive at an optimized design. In order to have a simple criterion to predict the reliability of the yet-to-be-built largedie package, reliability tests were carried out on some existing 15 mm times 15 mm die CvJlow-k flip chip packages which were identical to the 21mm times 21mm die package except for the size. The packages were found to pass the reliability tests. 2-D plane strain finite element analyses were then performed on the 15 mm times 15 mm die. The computed delamination stresses at the low-k layer and the strain energy density dissipation per cycle in the critical solder (DeltaW) were then used as a benchmark for the design of a larger flip chip package. The efficacy of the polymer encapsulated dicing lane technology was established. In this paper, the effect of the number of fluorosilicate glass layers, die thickness, substrate thickness, Cu post height, and underfill type on the delamination stresses in the low-k layer and DeltaW were determined. Specimens of the optimized large-die package were then fabricated and subjected to reliability tests. They were all found to pass the reliability tests. From these reliability tests, new benchmark values of the delamination stresses at the low-k layer and DeltaW are obtained, which can be used to aid in the design of large-die Cu/low-k flip chip packages.
{"title":"Optimization of the Thermomechanical Reliability of a 65 nm Cu/Low-$k$ Large-Die Flip Chip Package","authors":"J. Ong, A. Tay, X. Zhang, V. Kripesh, Y. K. Lim, D. Yeo, K.C. Chan, J.B. Tan, L. Hsia, D. Sohn","doi":"10.1109/TCAPT.2009.2020696","DOIUrl":"https://doi.org/10.1109/TCAPT.2009.2020696","url":null,"abstract":"The trend toward finer pitch and higher performance integrated circuit devices has driven the semiconductor industry to incorporate copper and low-k dielectric materials. However, the low-k materials have lower modulus and poorer adhesion compared to the common dielectric materials. Thus, thermomechanical failure is one of the major bottlenecks in the development of Cu/low-k larger-die flip chip packages. This paper describes the optimization of the structural design of Chartered's C65 nm 21 mm times 21 mm die size flip-chip ball grid array package incorporated with fully active and functional ninemetal Cu/low-k layers and 150 mum interconnect pitch. The lowk material used in this paper is nonporous SiCOH with a k value of 2.9. A parametric study using 2-D plane strain finite element analysis was performed to study the effect of various parameters on the reliability of the large-die package in order to arrive at an optimized design. In order to have a simple criterion to predict the reliability of the yet-to-be-built largedie package, reliability tests were carried out on some existing 15 mm times 15 mm die CvJlow-k flip chip packages which were identical to the 21mm times 21mm die package except for the size. The packages were found to pass the reliability tests. 2-D plane strain finite element analyses were then performed on the 15 mm times 15 mm die. The computed delamination stresses at the low-k layer and the strain energy density dissipation per cycle in the critical solder (DeltaW) were then used as a benchmark for the design of a larger flip chip package. The efficacy of the polymer encapsulated dicing lane technology was established. In this paper, the effect of the number of fluorosilicate glass layers, die thickness, substrate thickness, Cu post height, and underfill type on the delamination stresses in the low-k layer and DeltaW were determined. Specimens of the optimized large-die package were then fabricated and subjected to reliability tests. They were all found to pass the reliability tests. From these reliability tests, new benchmark values of the delamination stresses at the low-k layer and DeltaW are obtained, which can be used to aid in the design of large-die Cu/low-k flip chip packages.","PeriodicalId":55013,"journal":{"name":"IEEE Transactions on Components and Packaging Technologies","volume":"32 1","pages":"838-848"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TCAPT.2009.2020696","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62519023","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-11-24DOI: 10.1109/TCAPT.2009.2032767
L. Martin, S. Ooi, D. Staiculescu, Michael D. Hill, C. Wong, M. Tentzeris
This paper is an investigation of the feasibility of applying a mechanically flexible magnetic composite material to radio frequency identification (RFID) planar antennas operating in the lower ultrahigh-frequency (UHF) spectrum (~300500 MHz). A key challenge is that the magnetic loss introduced by the magnetic composite must be sufficiently low for successful application at the targeted operating frequency. A flexible magnetic composite comprised of particles of Z-phase Co hexaferrite, also known as Co2Z, in a silicone matrix was developed. To the authors' knowledge, this is the first flexible magnetic composite demonstrated to work at these frequencies. The benchmarking structure was a quarter-wavelength microstrip patch antenna. Antennas on the developed magnetic composite and pure silicone substrates were electromagnetically modeled in Ansoft High-Frequency Sounder System full wave electromagnetic software. A prototype of the antenna on the magnetic composite was fabricated, and good agreement between the simulated and measured results was found. Comparison of the antennas on the magnetic composite versus the pure silicone substrate showed miniaturization capability of 2.4 times and performance differences of increased bandwidth and reduced gain, both of which were attributed in part to the increase in the dielectric and magnetic losses. A key finding of this paper is that a small amount of permeability (mur~2.5) can provide a substantial capability for miniaturization, while sufficiently low-magnetic loss can be introduced for successful application at the targeted operating frequency. This magnetic composite shows the capability to fulfill this balance and to be a feasible option for RFID, flexible wearable, and conformal applications in the lower UHF spectrum.
{"title":"Effect of Permittivity and Permeability of a Flexible Magnetic Composite Material on the Performance and Miniaturization Capability of Planar Antennas for RFID and Wearable Wireless Applications","authors":"L. Martin, S. Ooi, D. Staiculescu, Michael D. Hill, C. Wong, M. Tentzeris","doi":"10.1109/TCAPT.2009.2032767","DOIUrl":"https://doi.org/10.1109/TCAPT.2009.2032767","url":null,"abstract":"This paper is an investigation of the feasibility of applying a mechanically flexible magnetic composite material to radio frequency identification (RFID) planar antennas operating in the lower ultrahigh-frequency (UHF) spectrum (~300500 MHz). A key challenge is that the magnetic loss introduced by the magnetic composite must be sufficiently low for successful application at the targeted operating frequency. A flexible magnetic composite comprised of particles of Z-phase Co hexaferrite, also known as Co2Z, in a silicone matrix was developed. To the authors' knowledge, this is the first flexible magnetic composite demonstrated to work at these frequencies. The benchmarking structure was a quarter-wavelength microstrip patch antenna. Antennas on the developed magnetic composite and pure silicone substrates were electromagnetically modeled in Ansoft High-Frequency Sounder System full wave electromagnetic software. A prototype of the antenna on the magnetic composite was fabricated, and good agreement between the simulated and measured results was found. Comparison of the antennas on the magnetic composite versus the pure silicone substrate showed miniaturization capability of 2.4 times and performance differences of increased bandwidth and reduced gain, both of which were attributed in part to the increase in the dielectric and magnetic losses. A key finding of this paper is that a small amount of permeability (mur~2.5) can provide a substantial capability for miniaturization, while sufficiently low-magnetic loss can be introduced for successful application at the targeted operating frequency. This magnetic composite shows the capability to fulfill this balance and to be a feasible option for RFID, flexible wearable, and conformal applications in the lower UHF spectrum.","PeriodicalId":55013,"journal":{"name":"IEEE Transactions on Components and Packaging Technologies","volume":"32 1","pages":"849-858"},"PeriodicalIF":0.0,"publicationDate":"2009-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TCAPT.2009.2032767","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62519732","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-11-17DOI: 10.1109/TCAPT.2009.2025960
G. Sethi, R. Sahul, C. Min, P. Tewari, E. Furman, M. Horn, M. Lanagan
Deposition of high-k tantalum oxide thin films on thin polymer substrates was investigated, using low-temperature (-100degC) pulsed-dc reactive sputtering. Degradation of two different polymers, polyethylene terephthalate (PET) and polypropylene (PP), were studied as a function of sputtering conditions. Two different deposition configurations have been explored for polymer films with aluminum electrode on one side. In one configuration, tantalum oxide was deposited on the nonelectroded side of the polymer, while in the other the deposition was on the electroded side of the polymer. The two fabricated structures have been characterized for dielectric permittivity, loss, and ac conductivity as a function of frequency and temperature. Sputtering tantalum oxide on the nonelectroded side of PET substrates results in a 37% higher permittivity for PET than the series model prediction of permittivity. Higher dielectric loss and ac conductivity accompany the higher permittivity. The alpha bulk relaxation in PET moves to slightly higher temperatures, indicating that there is an increase in the crystallinity of the bulk polymer. This observation is supported by the broader glass transition and an additional endothermic peak around 200degC in PET/Ta2O5 compared to neat PET. In addition, modifications of the space charge activation energy in PET from 1.35 eV to 1.82 eV and of dc conductivity in PET from 6 times10-15 S/m to 4 times10-14 S/m is observed. Sputtering Ta2O5 on the electroded side of the PET, under the same sputtering conditions, results in the formation of high-k tantalum oxide with dielectric permittivity, loss, and ac conductivity of 30, <5%, and 10-7S/m at 1 kHz, respectively.
{"title":"Dielectric Response of Tantalum Oxide Deposited on Polyethylene Terephthalate (PET) Film by Low-Temperature Pulsed-DC Sputtering for Wound Capacitors","authors":"G. Sethi, R. Sahul, C. Min, P. Tewari, E. Furman, M. Horn, M. Lanagan","doi":"10.1109/TCAPT.2009.2025960","DOIUrl":"https://doi.org/10.1109/TCAPT.2009.2025960","url":null,"abstract":"Deposition of high-k tantalum oxide thin films on thin polymer substrates was investigated, using low-temperature (-100degC) pulsed-dc reactive sputtering. Degradation of two different polymers, polyethylene terephthalate (PET) and polypropylene (PP), were studied as a function of sputtering conditions. Two different deposition configurations have been explored for polymer films with aluminum electrode on one side. In one configuration, tantalum oxide was deposited on the nonelectroded side of the polymer, while in the other the deposition was on the electroded side of the polymer. The two fabricated structures have been characterized for dielectric permittivity, loss, and ac conductivity as a function of frequency and temperature. Sputtering tantalum oxide on the nonelectroded side of PET substrates results in a 37% higher permittivity for PET than the series model prediction of permittivity. Higher dielectric loss and ac conductivity accompany the higher permittivity. The alpha bulk relaxation in PET moves to slightly higher temperatures, indicating that there is an increase in the crystallinity of the bulk polymer. This observation is supported by the broader glass transition and an additional endothermic peak around 200degC in PET/Ta2O5 compared to neat PET. In addition, modifications of the space charge activation energy in PET from 1.35 eV to 1.82 eV and of dc conductivity in PET from 6 times10-15 S/m to 4 times10-14 S/m is observed. Sputtering Ta2O5 on the electroded side of the PET, under the same sputtering conditions, results in the formation of high-k tantalum oxide with dielectric permittivity, loss, and ac conductivity of 30, <5%, and 10-7S/m at 1 kHz, respectively.","PeriodicalId":55013,"journal":{"name":"IEEE Transactions on Components and Packaging Technologies","volume":"32 1","pages":"915-925"},"PeriodicalIF":0.0,"publicationDate":"2009-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TCAPT.2009.2025960","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62519581","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-11-06DOI: 10.1109/TCAPT.2009.2030418
M. Aziz, A. Safwat, F. Podevin, A. Vilcot
In this paper, coplanar waveguide filters with etched-ground stubs that have multiple behaviors are proposed. The response of a unit cell is a band reject with one or more transmission zeros according to the number and the lengths of the stubs. A library of transmission line models is being built for the basic cells and then used for the design of more elaborated structures. The potential of these new topologies is highlighted by providing different filtering structures with interesting features: a second-order narrow bandpass filter, and two configurations for a lowpass filter with a wide stopband. All theoretical predictions have been verified by electromagnetic simulation and measurements.
{"title":"Coplanar Waveguide Filters Based on Multibehavior Etched-Ground Stubs","authors":"M. Aziz, A. Safwat, F. Podevin, A. Vilcot","doi":"10.1109/TCAPT.2009.2030418","DOIUrl":"https://doi.org/10.1109/TCAPT.2009.2030418","url":null,"abstract":"In this paper, coplanar waveguide filters with etched-ground stubs that have multiple behaviors are proposed. The response of a unit cell is a band reject with one or more transmission zeros according to the number and the lengths of the stubs. A library of transmission line models is being built for the basic cells and then used for the design of more elaborated structures. The potential of these new topologies is highlighted by providing different filtering structures with interesting features: a second-order narrow bandpass filter, and two configurations for a lowpass filter with a wide stopband. All theoretical predictions have been verified by electromagnetic simulation and measurements.","PeriodicalId":55013,"journal":{"name":"IEEE Transactions on Components and Packaging Technologies","volume":"32 1","pages":"816-824"},"PeriodicalIF":0.0,"publicationDate":"2009-11-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TCAPT.2009.2030418","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62519463","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-11-03DOI: 10.1109/TCAPT.2009.2032830
M. Pecht, L. Zuga
By the end of 2008, companies based on the business model of offshore production were observed to be rethinking their business models, tending to consider the repatriation of production bases in order to lower costs and shorten delivery times. In this article, the authors of China's Electronics Industry (2009 Edition), M. Pecht and L. Zuga, (City University of Hong Kong Press, Hong Kong, China, 2009) argue that repatriation is not likely to occur in the electronics industry, where expensive and complex production facilities have been moved offshore over a period of several decades. In particular, China has taken advantage of the West's offshore production model and its associated technology transfer to develop a manufacturing capability that has resulted in the ldquoChina Pricerdquo in electronics. As a result, China now has the infrastructure and electronics supply chain necessary to produce a wide range of products, from simple components to embedded systems and systems integration. This gives China the capability to produce complex electronics applications domestically, including computers, automotive controls, medical instrumentation, avionics, and even sophisticated military command and control systems. The resultant gain in Chinese capabilities, commensurate with the loss in Western capabilities through use of the offshore production model, makes the repatriation of the electronics industry to its former bastions in the United States and Western Europe doubtful. This will have a strong impact on resource allocation, research planning, and innovation. The authors present their argument through a series of brief case studies.
{"title":"China as Hegemon of the Global Electronics Industry: How It Got That Way and Why It Won't Change","authors":"M. Pecht, L. Zuga","doi":"10.1109/TCAPT.2009.2032830","DOIUrl":"https://doi.org/10.1109/TCAPT.2009.2032830","url":null,"abstract":"By the end of 2008, companies based on the business model of offshore production were observed to be rethinking their business models, tending to consider the repatriation of production bases in order to lower costs and shorten delivery times. In this article, the authors of China's Electronics Industry (2009 Edition), M. Pecht and L. Zuga, (City University of Hong Kong Press, Hong Kong, China, 2009) argue that repatriation is not likely to occur in the electronics industry, where expensive and complex production facilities have been moved offshore over a period of several decades. In particular, China has taken advantage of the West's offshore production model and its associated technology transfer to develop a manufacturing capability that has resulted in the ldquoChina Pricerdquo in electronics. As a result, China now has the infrastructure and electronics supply chain necessary to produce a wide range of products, from simple components to embedded systems and systems integration. This gives China the capability to produce complex electronics applications domestically, including computers, automotive controls, medical instrumentation, avionics, and even sophisticated military command and control systems. The resultant gain in Chinese capabilities, commensurate with the loss in Western capabilities through use of the offshore production model, makes the repatriation of the electronics industry to its former bastions in the United States and Western Europe doubtful. This will have a strong impact on resource allocation, research planning, and innovation. The authors present their argument through a series of brief case studies.","PeriodicalId":55013,"journal":{"name":"IEEE Transactions on Components and Packaging Technologies","volume":"128 1","pages":"935-939"},"PeriodicalIF":0.0,"publicationDate":"2009-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TCAPT.2009.2032830","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62519743","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-10-30DOI: 10.1109/TCAPT.2009.2032923
Sang‐Woong Yoon, J. Laskar
This paper presents a folded inductor implemented with a multichip module, which involves a laminate organic packaging technology with an unfilled via process. The folded inductor had an increased inductor layer surface area because of the unfilled vias along the inductor layer. Thus, the quality (Q) factor of the inductor improved as the series resistance, resulting from the skin effect, decreased. The Q-factor for a folded inductor showed a maximum improvement of 32% by including contact resistances, in comparison with the Q -factors of a normal planar inductor.
{"title":"A Quality-Improved Folded Inductor Embedded in MCM-L Organic Packaging Substrate Using an Unfilled Via Process","authors":"Sang‐Woong Yoon, J. Laskar","doi":"10.1109/TCAPT.2009.2032923","DOIUrl":"https://doi.org/10.1109/TCAPT.2009.2032923","url":null,"abstract":"This paper presents a folded inductor implemented with a multichip module, which involves a laminate organic packaging technology with an unfilled via process. The folded inductor had an increased inductor layer surface area because of the unfilled vias along the inductor layer. Thus, the quality (Q) factor of the inductor improved as the series resistance, resulting from the skin effect, decreased. The Q-factor for a folded inductor showed a maximum improvement of 32% by including contact resistances, in comparison with the Q -factors of a normal planar inductor.","PeriodicalId":55013,"journal":{"name":"IEEE Transactions on Components and Packaging Technologies","volume":"32 1","pages":"741-745"},"PeriodicalIF":0.0,"publicationDate":"2009-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TCAPT.2009.2032923","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62519309","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-10-30DOI: 10.1109/TCAPT.2009.2020695
C.Y. Zhou, T. Yu, E. Suhir
A systematic study, both experimentally and analytically, is conducted to evaluate the feasibility of using appropriate shock table tests to mimic the drop impact environment for components and systems adopted in portable electronics. Firstly, experiments are carried out to observe the dynamic characteristics of typical portable electronic systems and components under drop impact. Then a series of shock table tests with different constraint conditions are designed to mimic the real-life impact state. By comparing the typical results from shock table tests and those from drop tests, the correlation of shock table test parameters and drop tests conditions is investigated. The results reveal that the conventional fully constrained shock table test cannot mimic the real-life drop impact conditions, while an appropriate shock table test method should allow the sample to rotate freely. Theoretical analysis is developed to explain the mechanics of the impact scenarios. It is found that due to Hertz contact spring effect and the rotational acceleration during the impact, the acceleration of the centroid sample is significantly different to that of the table. In addition, acceleration estimated by traditional force-divided-by-mass method may underestimate the real acceleration of components inside the products.
{"title":"Design of Shock Table Tests to Mimic Real-Life Drop Conditions","authors":"C.Y. Zhou, T. Yu, E. Suhir","doi":"10.1109/TCAPT.2009.2020695","DOIUrl":"https://doi.org/10.1109/TCAPT.2009.2020695","url":null,"abstract":"A systematic study, both experimentally and analytically, is conducted to evaluate the feasibility of using appropriate shock table tests to mimic the drop impact environment for components and systems adopted in portable electronics. Firstly, experiments are carried out to observe the dynamic characteristics of typical portable electronic systems and components under drop impact. Then a series of shock table tests with different constraint conditions are designed to mimic the real-life impact state. By comparing the typical results from shock table tests and those from drop tests, the correlation of shock table test parameters and drop tests conditions is investigated. The results reveal that the conventional fully constrained shock table test cannot mimic the real-life drop impact conditions, while an appropriate shock table test method should allow the sample to rotate freely. Theoretical analysis is developed to explain the mechanics of the impact scenarios. It is found that due to Hertz contact spring effect and the rotational acceleration during the impact, the acceleration of the centroid sample is significantly different to that of the table. In addition, acceleration estimated by traditional force-divided-by-mass method may underestimate the real acceleration of components inside the products.","PeriodicalId":55013,"journal":{"name":"IEEE Transactions on Components and Packaging Technologies","volume":"32 1","pages":"832-837"},"PeriodicalIF":0.0,"publicationDate":"2009-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TCAPT.2009.2020695","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62519013","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-10-30DOI: 10.1109/TCAPT.2009.2033414
Y. Yoon, Jin-Woo Park
We present a framework to calculate the thermal resistance of Au-Sn eutectic solder joint (Rth, Au-Sn joint) in high brightness light emitting diode (HB LED) packages whose heat extraction capability controls the optical efficiency and reliability of HB LEDs. Using the transient thermal measurement combined with the structure function based analytical method and the finite element method, we find that the thermal conductivity (k) of the thin solder joint becomes significantly smaller than the Au-Sn alloy after joining; hence, Rth, Au-Sn joint constitutes a large portion of the total Rth of the package (Rth PKG).
{"title":"The Thermal Resistance of Solder Joints in High Brightness Light Emitting Diode (HB LED) Packages","authors":"Y. Yoon, Jin-Woo Park","doi":"10.1109/TCAPT.2009.2033414","DOIUrl":"https://doi.org/10.1109/TCAPT.2009.2033414","url":null,"abstract":"We present a framework to calculate the thermal resistance of Au-Sn eutectic solder joint (Rth, Au-Sn joint) in high brightness light emitting diode (HB LED) packages whose heat extraction capability controls the optical efficiency and reliability of HB LEDs. Using the transient thermal measurement combined with the structure function based analytical method and the finite element method, we find that the thermal conductivity (k) of the thin solder joint becomes significantly smaller than the Au-Sn alloy after joining; hence, Rth, Au-Sn joint constitutes a large portion of the total Rth of the package (Rth PKG).","PeriodicalId":55013,"journal":{"name":"IEEE Transactions on Components and Packaging Technologies","volume":"32 1","pages":"825-831"},"PeriodicalIF":0.0,"publicationDate":"2009-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TCAPT.2009.2033414","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62520202","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-10-20DOI: 10.1109/TCAPT.2009.2024210
H. Johari, F. Ayazi
This paper reports on the design, implementation, and characterization of high-density trench-refilled capacitors in complementary metal-oxide-semiconductor (CMOS) grade silicon (1-10 Omegacm). High aspect ratio trench-refilled capacitors offer a capacitance density improvement of three orders of magnitude compared to thin-film capacitors with the same die area and dielectric thickness. Also, dielectric materials such as low-pressure chemical vapor deposition (LPCVD) silicon oxide and silicon nitride are utilized to enhance the breakdown voltage of these devices. The high aspect ratio polysilicon and single crystal silicon process was utilized to implement these capacitors, giving a gap aspect ratio of . This ultrahigh vertical capacitance area achieves an ultralarge capacitance density without requiring thin-or high-k dielectric material. High-value capacitors of values ranging from 40 nF to 4 muF with capacitance density of 58 (nF/mm 2) were implemented in silicon as arrays of 170 mum-deep trenches. LPCVD silicon dioxide and silicon nitride were employed as dielectric materials to provide robust deposition inside the high aspect ratio trenches. Trench-refilled capacitors show quality factors (Q) of 230 and 8, respectively, at 45 nF and 4 muF capacitances. The breakdown voltage in trench-refilled capacitors with 35 nm-thick Si3N4 is recorded to be as high as 17-V, which is ~4x to 10x larger than that of BaTiO3 and PbZrxTi1 - xO3 (PZT) thin-film capacitors with the same dielectric thickness. Furthermore, the capacitances were measured over a temperature range of 25 to 155degC, showing less than 1.8% variation in 45 nF devices. This implies that trench-refilled capacitors are free from the very strong temperature sensitivity exhibited by most high-k materials.
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