Pub Date : 2010-08-16DOI: 10.1109/TCAPT.2010.2047017
Gaowei Xu, Fei Geng, Qiuping Huang, L. Luo, Jian Zhou
In this paper, the warpage of 3-D multichip module (3D-MCM) on an embedded substrate with flip-chip and wirebonding interconnection method was studied by finite element (FE) simulation and moire fringes measurement. Simulation results showed that the warpage of 3D-MCM without underfill presents double-bow-shaped (W-shaped) mode, which is because of the cavity in substrate and the viscoplasticity behavior of solder balls. For the same reason, the warpage of substrate with temperature change has an inflexion around 75 °C, which indicated that the cavity in the substrate center may decrease the warpage of the substrate. The FE model and simulation results were validated through moire fringes measurement. Based on this model, the effect of underfill on warpage was discussed. It turned out that using suitable underfill could strengthen the interconnection between component and substrate, and then protect the solder balls and decrease the warpage of module. However, underfill with high coefficient of thermal expansion (CTE) may increase the stress, strain and plastic work density of solder ball, therefore result in the solder ball failure and lower the reliability of the module. The optimal CTE of the underfill, which is the mean magnitude of CTEs of the materials at both sides of unferfill layer, was determined with multiobjective method.
{"title":"Warpage and Reliability of a 3D-MCM on an Embedded Substrate With Multiple Interconnection Method","authors":"Gaowei Xu, Fei Geng, Qiuping Huang, L. Luo, Jian Zhou","doi":"10.1109/TCAPT.2010.2047017","DOIUrl":"https://doi.org/10.1109/TCAPT.2010.2047017","url":null,"abstract":"In this paper, the warpage of 3-D multichip module (3D-MCM) on an embedded substrate with flip-chip and wirebonding interconnection method was studied by finite element (FE) simulation and moire fringes measurement. Simulation results showed that the warpage of 3D-MCM without underfill presents double-bow-shaped (W-shaped) mode, which is because of the cavity in substrate and the viscoplasticity behavior of solder balls. For the same reason, the warpage of substrate with temperature change has an inflexion around 75 °C, which indicated that the cavity in the substrate center may decrease the warpage of the substrate. The FE model and simulation results were validated through moire fringes measurement. Based on this model, the effect of underfill on warpage was discussed. It turned out that using suitable underfill could strengthen the interconnection between component and substrate, and then protect the solder balls and decrease the warpage of module. However, underfill with high coefficient of thermal expansion (CTE) may increase the stress, strain and plastic work density of solder ball, therefore result in the solder ball failure and lower the reliability of the module. The optimal CTE of the underfill, which is the mean magnitude of CTEs of the materials at both sides of unferfill layer, was determined with multiobjective method.","PeriodicalId":55013,"journal":{"name":"IEEE Transactions on Components and Packaging Technologies","volume":"33 1","pages":"571-581"},"PeriodicalIF":0.0,"publicationDate":"2010-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TCAPT.2010.2047017","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62520589","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-08-12DOI: 10.1109/TCAPT.2009.2038169
S. Mikula, A. Kos
This paper presents an analysis of thermal dynamics in multicore systems, focusing on time response to heat generated in a single core and its connection with very large scale integration (VLSI) design principles. For the purpose of this paper, a point heating time (PHT) concept is introduced. PHT is a value that describes the time of temperature growth to its limited value. The PHT value is used for estimating the thermal capabilities of multicore systems. The physical properties of VLSI systems are taken into account for determining easy-to-apply rules of thermal dynamic response in common chip designs. The authors compare PHT in different physical conditions and its value versus displacement of the active thermal module away from the center position on the chip. An equation derived from analytical assumptions is the basis for asynchronous control of core activity toward minimizing its peak temperature. Final analysis leads to the conclusion that the paper can be used as a supplementary guide in VLSI chip development for better thermally optimized multicore chips.
{"title":"Thermal Dynamics of Multicore Integrated Systems","authors":"S. Mikula, A. Kos","doi":"10.1109/TCAPT.2009.2038169","DOIUrl":"https://doi.org/10.1109/TCAPT.2009.2038169","url":null,"abstract":"This paper presents an analysis of thermal dynamics in multicore systems, focusing on time response to heat generated in a single core and its connection with very large scale integration (VLSI) design principles. For the purpose of this paper, a point heating time (PHT) concept is introduced. PHT is a value that describes the time of temperature growth to its limited value. The PHT value is used for estimating the thermal capabilities of multicore systems. The physical properties of VLSI systems are taken into account for determining easy-to-apply rules of thermal dynamic response in common chip designs. The authors compare PHT in different physical conditions and its value versus displacement of the active thermal module away from the center position on the chip. An equation derived from analytical assumptions is the basis for asynchronous control of core activity toward minimizing its peak temperature. Final analysis leads to the conclusion that the paper can be used as a supplementary guide in VLSI chip development for better thermally optimized multicore chips.","PeriodicalId":55013,"journal":{"name":"IEEE Transactions on Components and Packaging Technologies","volume":"33 1","pages":"524-534"},"PeriodicalIF":0.0,"publicationDate":"2010-08-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TCAPT.2009.2038169","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62519859","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-08-12DOI: 10.1109/TCAPT.2010.2046901
H. Mustain, W. Brown, S. Ang
Recently, silicon carbide power devices have been receiving attention for applications above 300 °C. For high-temperature applications, the die attached for these devices has to withstand the maximum operating temperature. In this paper, a transient liquid phase (TLP) die attach technique was demonstrated for two binary alloy systems, Ag-In and Au-In, on Si3N4 substrates. A nearly void-free joint was developed using the Ag-In alloy. Two inter-metallic phases of Agln2 and Ag2ln, along with pure Ag were identified. After annealing at 400 °C, the silver appears to be more evenly spread to form a silver-rich Ag-In alloy with a Ag composition of 70-75 wt.%, even though a nearly pure silver phase is still found in the region where the silver was initially deposited on the Si3N4 substrate. For the Au-In system, there was no indication of bonding degradation at the interface after annealing at 400 °C for 100 h in air. Two inter-metallic phases, Auln and Auln2, along with pure gold, were identified in the Au-In TLP joint. After annealing, the bonding interface became a more Au-rich Au-In alloy. The die attach pull strength, after thermal annealing, increased to approximately twice the minimum strength. The uniformity of the bonds improves and they become more homogeneous because the formation of intermetallic phases continues during thermal annealing.
{"title":"Transient Liquid Phase Die Attach for High-Temperature Silicon Carbide Power Devices","authors":"H. Mustain, W. Brown, S. Ang","doi":"10.1109/TCAPT.2010.2046901","DOIUrl":"https://doi.org/10.1109/TCAPT.2010.2046901","url":null,"abstract":"Recently, silicon carbide power devices have been receiving attention for applications above 300 °C. For high-temperature applications, the die attached for these devices has to withstand the maximum operating temperature. In this paper, a transient liquid phase (TLP) die attach technique was demonstrated for two binary alloy systems, Ag-In and Au-In, on Si3N4 substrates. A nearly void-free joint was developed using the Ag-In alloy. Two inter-metallic phases of Agln2 and Ag2ln, along with pure Ag were identified. After annealing at 400 °C, the silver appears to be more evenly spread to form a silver-rich Ag-In alloy with a Ag composition of 70-75 wt.%, even though a nearly pure silver phase is still found in the region where the silver was initially deposited on the Si3N4 substrate. For the Au-In system, there was no indication of bonding degradation at the interface after annealing at 400 °C for 100 h in air. Two inter-metallic phases, Auln and Auln2, along with pure gold, were identified in the Au-In TLP joint. After annealing, the bonding interface became a more Au-rich Au-In alloy. The die attach pull strength, after thermal annealing, increased to approximately twice the minimum strength. The uniformity of the bonds improves and they become more homogeneous because the formation of intermetallic phases continues during thermal annealing.","PeriodicalId":55013,"journal":{"name":"IEEE Transactions on Components and Packaging Technologies","volume":"33 1","pages":"563-570"},"PeriodicalIF":0.0,"publicationDate":"2010-08-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TCAPT.2010.2046901","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62520548","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-08-12DOI: 10.1109/TCAPT.2010.2047019
A. Shibuya, A. Ouchi, K. Takemura
A silicon interposer with an integrated with SrTiO3 (STO) thin film capacitor that decreases switching noise in high-speed digital circuits has been developed, along with a process to fabricate it. The process for fabricating the capacitor was optimized to reduce the defect density. The identified optimal process conditions are sputter-depositing the STO at 400 °C and using Ru as a bottom electrode. An large-scale integration chip is stacked on the Si interposers using chip-to-wafer bonding, and through-silicon vias (TSVs) are then formed in the interposer. This stacking enables a 50 μm-thick Si interposer to be inserted between a chip and a printed wiring board (PWB). A maximum capacitance density of 2.5 F/cm2 was achieved for a 60-nm-thick STO capacitor in a 20 × 20 mm2 area with 9000 TSVs (50- diameter; 50- depth). The capacitance of slightly more than 1 F in interposer-chip stack samples with 1600 TSVs remained constant during a thermal testing on PWBs for up to 1000 cycles.
{"title":"A Silicon Interposer With an Integrated ${rm SrTiO}_{3}$ Thin Film Decoupling Capacitor and Through-Silicon Vias","authors":"A. Shibuya, A. Ouchi, K. Takemura","doi":"10.1109/TCAPT.2010.2047019","DOIUrl":"https://doi.org/10.1109/TCAPT.2010.2047019","url":null,"abstract":"A silicon interposer with an integrated with SrTiO3 (STO) thin film capacitor that decreases switching noise in high-speed digital circuits has been developed, along with a process to fabricate it. The process for fabricating the capacitor was optimized to reduce the defect density. The identified optimal process conditions are sputter-depositing the STO at 400 °C and using Ru as a bottom electrode. An large-scale integration chip is stacked on the Si interposers using chip-to-wafer bonding, and through-silicon vias (TSVs) are then formed in the interposer. This stacking enables a 50 μm-thick Si interposer to be inserted between a chip and a printed wiring board (PWB). A maximum capacitance density of 2.5 F/cm2 was achieved for a 60-nm-thick STO capacitor in a 20 × 20 mm2 area with 9000 TSVs (50- diameter; 50- depth). The capacitance of slightly more than 1 F in interposer-chip stack samples with 1600 TSVs remained constant during a thermal testing on PWBs for up to 1000 cycles.","PeriodicalId":55013,"journal":{"name":"IEEE Transactions on Components and Packaging Technologies","volume":"33 1","pages":"582-587"},"PeriodicalIF":0.0,"publicationDate":"2010-08-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TCAPT.2010.2047019","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62520639","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-07-01DOI: 10.1109/TCAPT.2010.2046488
Yeong-Her Lin, J. You, Yuan-Chang Lin, N. Tran, F. Shi
Silicone materials with a relatively high-refractive index have been introduced for the encapsulation of high-power light-emitting diodes (LEDs), and LEDs with relatively short wavelengths. However, most of those existing silicone encapsulants still suffer from thermal and radiation induced degradations and thus lead to reliability issues and a shorten lifetime. A new high-performance silicone has been developed and its performance is compared with other commercial silicone and optical grade epoxy in high-power white LEDs. The new materials had been found to suffer less loss in the lumen output during the aging test and high-temperature/high-humidity test, as well as the Joint Electron Devices Engineering Council (JEDEC) reliability test. It is concluded that this material is excellent for the packaging of high-power white LEDs and high-power colored LEDs, because of its ability in maintaining high-transparency and great radiation/thermal resistance.
{"title":"Development of High-Performance Optical Silicone for the Packaging of High-Power LEDs","authors":"Yeong-Her Lin, J. You, Yuan-Chang Lin, N. Tran, F. Shi","doi":"10.1109/TCAPT.2010.2046488","DOIUrl":"https://doi.org/10.1109/TCAPT.2010.2046488","url":null,"abstract":"Silicone materials with a relatively high-refractive index have been introduced for the encapsulation of high-power light-emitting diodes (LEDs), and LEDs with relatively short wavelengths. However, most of those existing silicone encapsulants still suffer from thermal and radiation induced degradations and thus lead to reliability issues and a shorten lifetime. A new high-performance silicone has been developed and its performance is compared with other commercial silicone and optical grade epoxy in high-power white LEDs. The new materials had been found to suffer less loss in the lumen output during the aging test and high-temperature/high-humidity test, as well as the Joint Electron Devices Engineering Council (JEDEC) reliability test. It is concluded that this material is excellent for the packaging of high-power white LEDs and high-power colored LEDs, because of its ability in maintaining high-transparency and great radiation/thermal resistance.","PeriodicalId":55013,"journal":{"name":"IEEE Transactions on Components and Packaging Technologies","volume":"33 1","pages":"761-766"},"PeriodicalIF":0.0,"publicationDate":"2010-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TCAPT.2010.2046488","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62520469","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-21DOI: 10.1109/TCAPT.2010.2041456
A. Espinosa, J. Riba, J. Cusidó, J. Ortega, L. Romeral
The undesirable phenomenon of the contact bounce causes severe erosion of the contacts and, as a consequence, their electrical life and reliability are greatly reduced. On the other hand, the bounce of the armature can provoke re-opening of the contacts, even when they have already been closed. This paper deals with the elimination of the bounce in both contacts and armature of a commercial dc core contactor. This is achieved by means of a current closed-loop controller, which only uses as input the current and voltage of the contactor's magnetizing coil. The logic control has been implemented in a low cost microcontroller. Moreover, the board control can be fed by either dc or ac, and either in 50 Hz or 60 Hz so as to extend its applicability. A set of data is obtained from the measurement of the position and velocity of the movable parts for different operating voltages, and the dynamic behavior of the contactor is discussed.
{"title":"Closed-Loop Controller for Eliminating the Contact Bounce in DC Core Contactors","authors":"A. Espinosa, J. Riba, J. Cusidó, J. Ortega, L. Romeral","doi":"10.1109/TCAPT.2010.2041456","DOIUrl":"https://doi.org/10.1109/TCAPT.2010.2041456","url":null,"abstract":"The undesirable phenomenon of the contact bounce causes severe erosion of the contacts and, as a consequence, their electrical life and reliability are greatly reduced. On the other hand, the bounce of the armature can provoke re-opening of the contacts, even when they have already been closed. This paper deals with the elimination of the bounce in both contacts and armature of a commercial dc core contactor. This is achieved by means of a current closed-loop controller, which only uses as input the current and voltage of the contactor's magnetizing coil. The logic control has been implemented in a low cost microcontroller. Moreover, the board control can be fed by either dc or ac, and either in 50 Hz or 60 Hz so as to extend its applicability. A set of data is obtained from the measurement of the position and velocity of the movable parts for different operating voltages, and the dynamic behavior of the contactor is discussed.","PeriodicalId":55013,"journal":{"name":"IEEE Transactions on Components and Packaging Technologies","volume":"06 1","pages":"535-543"},"PeriodicalIF":0.0,"publicationDate":"2010-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TCAPT.2010.2041456","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62520145","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-07DOI: 10.1109/TCAPT.2010.2045000
Qiang Wu, N. Lorenz, K. Cannon, D. Hand
In this paper, we investigate the feasibility of using a laser as the heat source to drive a hermetic joining process based on a glass frit intermediate layer. The laser allows the necessary heat energy to be provided in a localized manner; important either as part of a multistage process, or to allow thermally-sensitive materials to be used inside the package. Our study includes an investigation of the impact of rough and grooved surfaces on the hermeticity and strength of the join, demonstrating the robust nature of the process, and its ability to allow feed-throughs to the center of package. Hermetic sealing is demonstrated, with leak rates of 10-9 mbar 1s-1, satisfying the military standard MIL-STD-883G.
{"title":"Glass Frit as a Hermetic Joining Layer in Laser Based Joining of Miniature Devices","authors":"Qiang Wu, N. Lorenz, K. Cannon, D. Hand","doi":"10.1109/TCAPT.2010.2045000","DOIUrl":"https://doi.org/10.1109/TCAPT.2010.2045000","url":null,"abstract":"In this paper, we investigate the feasibility of using a laser as the heat source to drive a hermetic joining process based on a glass frit intermediate layer. The laser allows the necessary heat energy to be provided in a localized manner; important either as part of a multistage process, or to allow thermally-sensitive materials to be used inside the package. Our study includes an investigation of the impact of rough and grooved surfaces on the hermeticity and strength of the join, demonstrating the robust nature of the process, and its ability to allow feed-throughs to the center of package. Hermetic sealing is demonstrated, with leak rates of 10-9 mbar 1s-1, satisfying the military standard MIL-STD-883G.","PeriodicalId":55013,"journal":{"name":"IEEE Transactions on Components and Packaging Technologies","volume":"33 1","pages":"470-477"},"PeriodicalIF":0.0,"publicationDate":"2010-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TCAPT.2010.2045000","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62520098","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-07DOI: 10.1109/TCAPT.2010.2044575
Y. Yen, T. Fang, Yu-Cheng Lin
This paper investigates 2-D finite element analysis to determine the stress and strain distributions across the thickness of ink in single-lap joints. The results of simulations for 10 μm, 20 μm, 30 μm, and 40 μm thickness of ink are presented. Tensile peel and shear stress at the bond free edges change significantly across the thickness of ink, and the maximum shear and peel stresses occur near the overlap joint corner ends. Fourier transform infrared data indicated there was no water absorption in SN9000 ink after a pressure cooker test in which the parameters were 121°C, 100% relative humidity and 2 atm for 96 h. However, the thickness of tin varied when there were differences in the curing temperature. Looking at the experiment and predictions, the confidence level of the results is 91.4%. The findings of this paper help us to understand the relationship between the reliability and the operating temperature of SN9000 for curing temperature design.
{"title":"Reliability and Stress Analysis of Ink for Chip on Film Packaging","authors":"Y. Yen, T. Fang, Yu-Cheng Lin","doi":"10.1109/TCAPT.2010.2044575","DOIUrl":"https://doi.org/10.1109/TCAPT.2010.2044575","url":null,"abstract":"This paper investigates 2-D finite element analysis to determine the stress and strain distributions across the thickness of ink in single-lap joints. The results of simulations for 10 μm, 20 μm, 30 μm, and 40 μm thickness of ink are presented. Tensile peel and shear stress at the bond free edges change significantly across the thickness of ink, and the maximum shear and peel stresses occur near the overlap joint corner ends. Fourier transform infrared data indicated there was no water absorption in SN9000 ink after a pressure cooker test in which the parameters were 121°C, 100% relative humidity and 2 atm for 96 h. However, the thickness of tin varied when there were differences in the curing temperature. Looking at the experiment and predictions, the confidence level of the results is 91.4%. The findings of this paper help us to understand the relationship between the reliability and the operating temperature of SN9000 for curing temperature design.","PeriodicalId":55013,"journal":{"name":"IEEE Transactions on Components and Packaging Technologies","volume":"33 1","pages":"299-306"},"PeriodicalIF":0.0,"publicationDate":"2010-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TCAPT.2010.2044575","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62520041","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-07DOI: 10.1109/TCAPT.2010.2051598
Dan Deisz
This paper describes a recommended set of information that should be gathered and archived during the component design process to facilitate the component-level redesign process.The work presented is based on reverse engineering of many obsolete parts.
{"title":"Semiconductor Design Archiving for EDA Tool and Environment-Independent Product Reuse and Re-Creation","authors":"Dan Deisz","doi":"10.1109/TCAPT.2010.2051598","DOIUrl":"https://doi.org/10.1109/TCAPT.2010.2051598","url":null,"abstract":"This paper describes a recommended set of information that should be gathered and archived during the component design process to facilitate the component-level redesign process.The work presented is based on reverse engineering of many obsolete parts.","PeriodicalId":55013,"journal":{"name":"IEEE Transactions on Components and Packaging Technologies","volume":"33 1","pages":"510-514"},"PeriodicalIF":0.0,"publicationDate":"2010-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TCAPT.2010.2051598","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62520417","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-03DOI: 10.1109/TCAPT.2010.2050380
T. Vincent, Yan Itovich, I. Bar-on
This paper describes a method of forming different conductor edge cross-section angles by using thick-film screen printing on substrates of different surface roughness. The edge angle for each surface type is compared visually and measured using an interferometer microscope. The conductor edge angle is correlated to the respective transmission loss sample. The impact of different edge angles on conductor loss is observed.
{"title":"Quantitative Edge Cross-Section Angle Impact on Conductor Loss","authors":"T. Vincent, Yan Itovich, I. Bar-on","doi":"10.1109/TCAPT.2010.2050380","DOIUrl":"https://doi.org/10.1109/TCAPT.2010.2050380","url":null,"abstract":"This paper describes a method of forming different conductor edge cross-section angles by using thick-film screen printing on substrates of different surface roughness. The edge angle for each surface type is compared visually and measured using an interferometer microscope. The conductor edge angle is correlated to the respective transmission loss sample. The impact of different edge angles on conductor loss is observed.","PeriodicalId":55013,"journal":{"name":"IEEE Transactions on Components and Packaging Technologies","volume":"33 1","pages":"386-390"},"PeriodicalIF":0.0,"publicationDate":"2010-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TCAPT.2010.2050380","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62520260","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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