Pub Date : 2010-05-01DOI: 10.1109/TADVP.2009.2038615
D. Schulz, J. Hoey, D. Thompson, O. Swenson, S. Han, J. Lovaasen, X. Dai, C. Braun, K. Keller, I. Akhatov
Materials deposition based upon directed aerosol flow has the potential of finding application in the field of flexible electronics where a low-temperature route to printed transistors with high mobilities remains elusive. NDSU has been actively engaged in addressing this opportunity from the following two perspectives: 1) developing an appreciation of the basic physics that dominate aerosol beam deposition toward engineering a robust method that allows the realization of deposited features with sub-5 μm resolution; and, 2) developing an understanding of the mechanistic transformations of silane-based precursor inks toward the formation of electronic materials at atmospheric-pressure. In this paper, we will briefly discuss the genesis of a new materials deposition method termed collimated aerosol beam direct-write (CAB-DW) where precision linewidth control has been realized using a combined theoretical/experimental approach. Next, we will discuss progress using Si6H12 (cyclohexasilane-a liquid silane) as a precursor for solution-processed diodes and transistors. Finally, we demonstrate the ability to CAB-DW Si6H12-based precursor inks for printing Si-based semiconductors.
{"title":"Collimated Aerosol Beam Deposition: Sub-5-$mu$m Resolution of Printed Actives and Passives","authors":"D. Schulz, J. Hoey, D. Thompson, O. Swenson, S. Han, J. Lovaasen, X. Dai, C. Braun, K. Keller, I. Akhatov","doi":"10.1109/TADVP.2009.2038615","DOIUrl":"https://doi.org/10.1109/TADVP.2009.2038615","url":null,"abstract":"Materials deposition based upon directed aerosol flow has the potential of finding application in the field of flexible electronics where a low-temperature route to printed transistors with high mobilities remains elusive. NDSU has been actively engaged in addressing this opportunity from the following two perspectives: 1) developing an appreciation of the basic physics that dominate aerosol beam deposition toward engineering a robust method that allows the realization of deposited features with sub-5 μm resolution; and, 2) developing an understanding of the mechanistic transformations of silane-based precursor inks toward the formation of electronic materials at atmospheric-pressure. In this paper, we will briefly discuss the genesis of a new materials deposition method termed collimated aerosol beam direct-write (CAB-DW) where precision linewidth control has been realized using a combined theoretical/experimental approach. Next, we will discuss progress using Si6H12 (cyclohexasilane-a liquid silane) as a precursor for solution-processed diodes and transistors. Finally, we demonstrate the ability to CAB-DW Si6H12-based precursor inks for printing Si-based semiconductors.","PeriodicalId":55015,"journal":{"name":"IEEE Transactions on Advanced Packaging","volume":"33 1","pages":"421-427"},"PeriodicalIF":0.0,"publicationDate":"2010-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TADVP.2009.2038615","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62396357","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-05-01DOI: 10.1109/TADVP.2009.2034335
Wei Lin, Rongwei Zhang, K. Moon, C. Wong
Vertically aligned carbon nanotubes (VACNTs) grown on bulk copper substrate are of great importance for real-life commercial applications of carbon nanotubes (CNTs) as thermal interface materials in microelectronic packaging. However, their reproducible syntheses have been a great challenge so far. In this study, by introducing a well-controlled conformal Al2O3 support layer on the bulk copper substrate by atomic layer deposition, we reproducibly synthesized VACNTs of good alignment and high quality on the copper substrate. The alignment and the quality were characterized by scanning electron microscope, transmission electron microscope, and Raman spectroscopy. The key roles of the conformal Al2O3 support layer by atomic layer deposition are discussed. This progress may provide a real-life VACNT application for thermal management.
{"title":"Synthesis of High-Quality Vertically Aligned Carbon Nanotubes on Bulk Copper Substrate for Thermal Management","authors":"Wei Lin, Rongwei Zhang, K. Moon, C. Wong","doi":"10.1109/TADVP.2009.2034335","DOIUrl":"https://doi.org/10.1109/TADVP.2009.2034335","url":null,"abstract":"Vertically aligned carbon nanotubes (VACNTs) grown on bulk copper substrate are of great importance for real-life commercial applications of carbon nanotubes (CNTs) as thermal interface materials in microelectronic packaging. However, their reproducible syntheses have been a great challenge so far. In this study, by introducing a well-controlled conformal Al2O3 support layer on the bulk copper substrate by atomic layer deposition, we reproducibly synthesized VACNTs of good alignment and high quality on the copper substrate. The alignment and the quality were characterized by scanning electron microscope, transmission electron microscope, and Raman spectroscopy. The key roles of the conformal Al2O3 support layer by atomic layer deposition are discussed. This progress may provide a real-life VACNT application for thermal management.","PeriodicalId":55015,"journal":{"name":"IEEE Transactions on Advanced Packaging","volume":"33 1","pages":"370-376"},"PeriodicalIF":0.0,"publicationDate":"2010-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TADVP.2009.2034335","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62395117","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-05-01DOI: 10.1109/TADVP.2009.2029561
Feng Sheng, H. Gan, D. Jiao
Fast algorithms are developed in this work for solving the system matrix resulting from a frequency-domain layered finite element based analysis of integrated circuits. The frequency-domain layered finite element method represents a 3-D layered system by a 2-D layered system, and further by a single-layered one. The reduced system matrix is generally denser than the original sparse matrix. In this paper, we show that 1) the dense matrix-vector multiplication can be performed in linear complexity; in addition, the reduction cost can be bypassed, 2) an effective preconditioner can be developed to converge the iterative solution of the reduced system matrix in a small number of iterations, and 3) the preconditioner can be solved in linear complexity. As a result, the reduced system matrix can be solved efficiently. The algorithms are rigorous without making any approximation. They apply to any arbitrarily-shaped multilayer structure. Numerical results demonstrated the accuracy, effectiveness, and efficiency of the proposed algorithms in analyzing on-chip circuits.
{"title":"Fast Iterative Solution Algorithms in the Frequency-Domain Layered Finite Element Method for Analyzing Integrated Circuits","authors":"Feng Sheng, H. Gan, D. Jiao","doi":"10.1109/TADVP.2009.2029561","DOIUrl":"https://doi.org/10.1109/TADVP.2009.2029561","url":null,"abstract":"Fast algorithms are developed in this work for solving the system matrix resulting from a frequency-domain layered finite element based analysis of integrated circuits. The frequency-domain layered finite element method represents a 3-D layered system by a 2-D layered system, and further by a single-layered one. The reduced system matrix is generally denser than the original sparse matrix. In this paper, we show that 1) the dense matrix-vector multiplication can be performed in linear complexity; in addition, the reduction cost can be bypassed, 2) an effective preconditioner can be developed to converge the iterative solution of the reduced system matrix in a small number of iterations, and 3) the preconditioner can be solved in linear complexity. As a result, the reduced system matrix can be solved efficiently. The algorithms are rigorous without making any approximation. They apply to any arbitrarily-shaped multilayer structure. Numerical results demonstrated the accuracy, effectiveness, and efficiency of the proposed algorithms in analyzing on-chip circuits.","PeriodicalId":55015,"journal":{"name":"IEEE Transactions on Advanced Packaging","volume":"33 1","pages":"524-533"},"PeriodicalIF":0.0,"publicationDate":"2010-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TADVP.2009.2029561","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62394108","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-05-01DOI: 10.1109/TADVP.2009.2032157
N. Nakhla, M. Nakhla, R. Achar
With higher operating frequencies, signal integrity and interconnect analysis in high-speed designs is becoming increasingly important. Recently, a passive delay extraction-based macromodeling algorithm (DEPACT) has been presented for simulation of long lossy coupled lines. In this paper, a new macromodeling algorithm based on DEPACT is introduced to handle several practical cases of importance, resulting in a simple and compact implementation in SPICE-like circuit simulators. The accuracy and efficiency of the proposed algorithm are validated using several practical examples.
{"title":"Simplified Delay Extraction-Based Passive Transmission Line Macromodeling Algorithm","authors":"N. Nakhla, M. Nakhla, R. Achar","doi":"10.1109/TADVP.2009.2032157","DOIUrl":"https://doi.org/10.1109/TADVP.2009.2032157","url":null,"abstract":"With higher operating frequencies, signal integrity and interconnect analysis in high-speed designs is becoming increasingly important. Recently, a passive delay extraction-based macromodeling algorithm (DEPACT) has been presented for simulation of long lossy coupled lines. In this paper, a new macromodeling algorithm based on DEPACT is introduced to handle several practical cases of importance, resulting in a simple and compact implementation in SPICE-like circuit simulators. The accuracy and efficiency of the proposed algorithm are validated using several practical examples.","PeriodicalId":55015,"journal":{"name":"IEEE Transactions on Advanced Packaging","volume":"33 1","pages":"498-509"},"PeriodicalIF":0.0,"publicationDate":"2010-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TADVP.2009.2032157","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62394176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-05-01DOI: 10.1109/TADVP.2009.2033571
H. Yin
An approach previously developed by Suhir in 1986 for calculating the interfacial compliance of a long-narrow strip is a general, explicit method, but Basaran and Wen claimed that there had been an error in the derivation. Using an additional approximation, they obtained a different form of longitudinal interfacial compliance. However, that approximation is not appropriate. Disregarding it, we can see that their result is the same as Suhir's result. However, a minor inconsistence in Suhir's derivation is still found. The applicability and modification of Suhir's model are discussed.
{"title":"Comments on \"Influence of Interfacial Compliance on Thermomechanical Stresses in Multilayered Microelectronic Packaging","authors":"H. Yin","doi":"10.1109/TADVP.2009.2033571","DOIUrl":"https://doi.org/10.1109/TADVP.2009.2033571","url":null,"abstract":"An approach previously developed by Suhir in 1986 for calculating the interfacial compliance of a long-narrow strip is a general, explicit method, but Basaran and Wen claimed that there had been an error in the derivation. Using an additional approximation, they obtained a different form of longitudinal interfacial compliance. However, that approximation is not appropriate. Disregarding it, we can see that their result is the same as Suhir's result. However, a minor inconsistence in Suhir's derivation is still found. The applicability and modification of Suhir's model are discussed.","PeriodicalId":55015,"journal":{"name":"IEEE Transactions on Advanced Packaging","volume":"33 1","pages":"353-355"},"PeriodicalIF":0.0,"publicationDate":"2010-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TADVP.2009.2033571","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62394569","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-05-01DOI: 10.1109/TADVP.2009.2035439
L. Dou, J. Dou
This paper applies the Lax-Friedrichs technique, usually used in fluid dynamics, to transmission line sensitivity analysis. The Lax-Friedrichs difference scheme for sensitivity analysis of both uniform and nonuniform transmission lines is derived. Based on this scheme, a method for analyzing multiconductor transmission line sensitivity, which does not need to be decoupled, is presented by combining with matrix operations. Using numerical experiments, the proposed method is compared with the characteristic method and the fast Fourier transform approach. With the presented method, the sensitivity of a nonlinear circuit including nonuniform multiconductor transmission lines is analyzed and the results are verified by the HSPICE perturbation method. The proposed method can be applied to either linear or nonlinear circuits, which include lossy nonuniform multiconductor transmission lines, and is proved to be efficient.
{"title":"Sensitivity Analysis of Lossy Nonuniform Multiconductor Transmission Lines With Nonlinear Terminations","authors":"L. Dou, J. Dou","doi":"10.1109/TADVP.2009.2035439","DOIUrl":"https://doi.org/10.1109/TADVP.2009.2035439","url":null,"abstract":"This paper applies the Lax-Friedrichs technique, usually used in fluid dynamics, to transmission line sensitivity analysis. The Lax-Friedrichs difference scheme for sensitivity analysis of both uniform and nonuniform transmission lines is derived. Based on this scheme, a method for analyzing multiconductor transmission line sensitivity, which does not need to be decoupled, is presented by combining with matrix operations. Using numerical experiments, the proposed method is compared with the characteristic method and the fast Fourier transform approach. With the presented method, the sensitivity of a nonlinear circuit including nonuniform multiconductor transmission lines is analyzed and the results are verified by the HSPICE perturbation method. The proposed method can be applied to either linear or nonlinear circuits, which include lossy nonuniform multiconductor transmission lines, and is proved to be efficient.","PeriodicalId":55015,"journal":{"name":"IEEE Transactions on Advanced Packaging","volume":"33 1","pages":"492-497"},"PeriodicalIF":0.0,"publicationDate":"2010-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TADVP.2009.2035439","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62395945","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-05-01DOI: 10.1109/TADVP.2009.2022322
L. De Camillis, G. Antonini, V. Jandhyala
Design of modern printed circuit boards requires robust simulation techniques to model power-bus structures. A reliable method is the cavity model which assumes small spacing between power and ground planes. Designers often make the proper tradeoffs between conflicting design requirements using optimization techniques, to obtain the best possible performance. To this aim, sensitivity information with respect to power-bus parameters are required by optimizers which employ gradient-based techniques and need the knowledge of sensitivities of the output responses. In this paper, the sensitivity analysis of power-bus structures is presented. Relying on the cavity model, voltage sensitivity is computed in a rational function form or rational polynomial form leading to a time-domain macromodel which can be efficiently interfaced with linear and nonlinear terminations or Spice-like simulators. The simulation results show the accuracy of the proposed approach.
{"title":"Power-Bus Sensitivity Analysis","authors":"L. De Camillis, G. Antonini, V. Jandhyala","doi":"10.1109/TADVP.2009.2022322","DOIUrl":"https://doi.org/10.1109/TADVP.2009.2022322","url":null,"abstract":"Design of modern printed circuit boards requires robust simulation techniques to model power-bus structures. A reliable method is the cavity model which assumes small spacing between power and ground planes. Designers often make the proper tradeoffs between conflicting design requirements using optimization techniques, to obtain the best possible performance. To this aim, sensitivity information with respect to power-bus parameters are required by optimizers which employ gradient-based techniques and need the knowledge of sensitivities of the output responses. In this paper, the sensitivity analysis of power-bus structures is presented. Relying on the cavity model, voltage sensitivity is computed in a rational function form or rational polynomial form leading to a time-domain macromodel which can be efficiently interfaced with linear and nonlinear terminations or Spice-like simulators. The simulation results show the accuracy of the proposed approach.","PeriodicalId":55015,"journal":{"name":"IEEE Transactions on Advanced Packaging","volume":"33 1","pages":"447-456"},"PeriodicalIF":0.0,"publicationDate":"2010-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TADVP.2009.2022322","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62391402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-05-01DOI: 10.1109/TADVP.2009.2026482
B. Wu, L. Tsang
This paper successfully extends the Foldy-Lax multiple scattering approach to model massively-coupled multiple vias in substrate of layered dielectrics between two horizontal power/ ground plates. The dyadic Green's functions of layered dielectrics are expressed in vector cylindrical waves and modal representations. Formulations are derived for admittances and S-parameters of single via and multiple vias structures. The CPUs and results of S-parameters are illustrated for various sizes of via array. For the case of 16 × 16 via array through hybrid dielectrics in single interior layer, the CPU is about 0.8 s per frequency and is at least three orders of magnitude faster than Ansoft HFSS. The results are within 5% difference of accuracy up to 20 GHz. This full-wave method is able to include all the coupling effects among the multiple vias. It is also shown that the approach of using effective dielectric constant by assuming an effective homogeneous media does not give accurate results.
{"title":"Signal Integrity Analysis of Package and Printed Circuit Board With Multiple Vias in Substrate of Layered Dielectrics","authors":"B. Wu, L. Tsang","doi":"10.1109/TADVP.2009.2026482","DOIUrl":"https://doi.org/10.1109/TADVP.2009.2026482","url":null,"abstract":"This paper successfully extends the Foldy-Lax multiple scattering approach to model massively-coupled multiple vias in substrate of layered dielectrics between two horizontal power/ ground plates. The dyadic Green's functions of layered dielectrics are expressed in vector cylindrical waves and modal representations. Formulations are derived for admittances and S-parameters of single via and multiple vias structures. The CPUs and results of S-parameters are illustrated for various sizes of via array. For the case of 16 × 16 via array through hybrid dielectrics in single interior layer, the CPU is about 0.8 s per frequency and is at least three orders of magnitude faster than Ansoft HFSS. The results are within 5% difference of accuracy up to 20 GHz. This full-wave method is able to include all the coupling effects among the multiple vias. It is also shown that the approach of using effective dielectric constant by assuming an effective homogeneous media does not give accurate results.","PeriodicalId":55015,"journal":{"name":"IEEE Transactions on Advanced Packaging","volume":"33 1","pages":"510-516"},"PeriodicalIF":0.0,"publicationDate":"2010-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TADVP.2009.2026482","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62391782","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-04-22DOI: 10.1109/TADVP.2010.2043253
V. S. Rao, Xiaowu Zhang, H. Wee, R. Rajoo, C. Premachandran, V. Kripesh, S. Yoon, J. Lau
Copper (Cu)/low-dielectric constant (K) structures are desired choices for advanced integrated circuits (ICs) as the IC technology moving towards fine pitch, high speed, increased integration and high performance. Copper interconnects with low-k dielectric material improve the performance of ICs by reducing interconnect the RC delay, the cross talk between the adjacent metal lines and the power loss. However, the packaging of Cu/low-k IC device is a challenge for the packaging industry to integrate these devices without any failure during assembly and reliability. The current work presents, 1) the finite element model (FEM) based parametric study on Cu/low-K wafer level package (WLP) reliability and stresses on Cu/low-K layers, and 2) experimental validation of WLP reliability by fabricating the test chips. FEM modeling and simulation results have shown that high aspect ratio interconnects, thinner die, and thinner printed circuit board can reduce the stress in low-k layer and enhance the board level interconnect reliability. Test chip of 7 mm ? 7 mm size is designed with 128 input/output (I/O) off-chip interconnects at 300-?m pitch in two depopulated rows using redistribution layers (RDL). Test chips are fabricated on 200-mm-diameter wafer with blanket black diamond (BD) low-K layers structure. Two different Pb free solder interconnects, thick copper column of 100 ?m height with SnAg solder cap and SnAg solder bump of 150 ?m height with 5-?m-thick copper under bump metallurgy (UBM), are fabricated. The Cu/low-K test chips are assembled onto a two layer high glass transition temperature (Tg) FR-4 substrate using two different types of no-flow underfills (NFU) to build the test vehicles and assembled test vehicles are subjected to various JEDEC standard reliability tests, and related failure analysis is carried out. Cu/low-k WLP with copper column interconnects without no-flow underfill passed 1000 h high-temperature storage (HTS) test, and passed the JEDEC drop test with no-flow underfill. Thin die test vehicles of Cu column interconnects with no-flow underfill and extra solder shown better thermal cycling (TC) performance and the board level TC performance can be improved further using thicker RDL.
{"title":"Design and Development of Fine Pitch Copper/Low-K Wafer Level Package","authors":"V. S. Rao, Xiaowu Zhang, H. Wee, R. Rajoo, C. Premachandran, V. Kripesh, S. Yoon, J. Lau","doi":"10.1109/TADVP.2010.2043253","DOIUrl":"https://doi.org/10.1109/TADVP.2010.2043253","url":null,"abstract":"Copper (Cu)/low-dielectric constant (K) structures are desired choices for advanced integrated circuits (ICs) as the IC technology moving towards fine pitch, high speed, increased integration and high performance. Copper interconnects with low-k dielectric material improve the performance of ICs by reducing interconnect the RC delay, the cross talk between the adjacent metal lines and the power loss. However, the packaging of Cu/low-k IC device is a challenge for the packaging industry to integrate these devices without any failure during assembly and reliability. The current work presents, 1) the finite element model (FEM) based parametric study on Cu/low-K wafer level package (WLP) reliability and stresses on Cu/low-K layers, and 2) experimental validation of WLP reliability by fabricating the test chips. FEM modeling and simulation results have shown that high aspect ratio interconnects, thinner die, and thinner printed circuit board can reduce the stress in low-k layer and enhance the board level interconnect reliability. Test chip of 7 mm ? 7 mm size is designed with 128 input/output (I/O) off-chip interconnects at 300-?m pitch in two depopulated rows using redistribution layers (RDL). Test chips are fabricated on 200-mm-diameter wafer with blanket black diamond (BD) low-K layers structure. Two different Pb free solder interconnects, thick copper column of 100 ?m height with SnAg solder cap and SnAg solder bump of 150 ?m height with 5-?m-thick copper under bump metallurgy (UBM), are fabricated. The Cu/low-K test chips are assembled onto a two layer high glass transition temperature (Tg) FR-4 substrate using two different types of no-flow underfills (NFU) to build the test vehicles and assembled test vehicles are subjected to various JEDEC standard reliability tests, and related failure analysis is carried out. Cu/low-k WLP with copper column interconnects without no-flow underfill passed 1000 h high-temperature storage (HTS) test, and passed the JEDEC drop test with no-flow underfill. Thin die test vehicles of Cu column interconnects with no-flow underfill and extra solder shown better thermal cycling (TC) performance and the board level TC performance can be improved further using thicker RDL.","PeriodicalId":55015,"journal":{"name":"IEEE Transactions on Advanced Packaging","volume":"33 1","pages":"377-388"},"PeriodicalIF":0.0,"publicationDate":"2010-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TADVP.2010.2043253","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62396532","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-04-15DOI: 10.1109/TADVP.2009.2034013
M. K. Abdullah, M. Z. Abdullah, M. Mujeebu, Z. M. Ariff, K. A. Ahmad
Multistacked-chip scale package (S-CSP) is a new technology that provides high density electronic package. A fully 3-D numerical model is developed to simulate mould filling behavior in the epoxy moulding compound (EMC) encapsulation of multi-S-CSP. Four different shapes of chip arrangement namely uniform, rotated, z-staggered-Type A and z-staggered-Type B, have been tested. The EMC is treated as a generalized Newtonian fluid (GNF). The developed methodology combines the Kawamura and Kuwahara technique-based finite difference method (FDM) and the robustness of volume-tracking (VOF) method to solve the two-phase flow field around the complex arrangement of microchips in a cavity. The Castro-Macosko rheology model with Arrhenius temperature dependence is adopted in the viscosity model. Short-shot experiments are conducted to investigate the filling patterns at several time intervals. The results show that the rotated shape die-arrangement gives minimum filling time and better mould filling yield. The close agreement between the experimental and simulation results illustrates the applicability of the proposed numerical model.
{"title":"Three-Dimensional Modelling to Study the Effect of Die-Stacking Shape on Mould Filling During Encapsulation of Microelectronic Chips","authors":"M. K. Abdullah, M. Z. Abdullah, M. Mujeebu, Z. M. Ariff, K. A. Ahmad","doi":"10.1109/TADVP.2009.2034013","DOIUrl":"https://doi.org/10.1109/TADVP.2009.2034013","url":null,"abstract":"Multistacked-chip scale package (S-CSP) is a new technology that provides high density electronic package. A fully 3-D numerical model is developed to simulate mould filling behavior in the epoxy moulding compound (EMC) encapsulation of multi-S-CSP. Four different shapes of chip arrangement namely uniform, rotated, z-staggered-Type A and z-staggered-Type B, have been tested. The EMC is treated as a generalized Newtonian fluid (GNF). The developed methodology combines the Kawamura and Kuwahara technique-based finite difference method (FDM) and the robustness of volume-tracking (VOF) method to solve the two-phase flow field around the complex arrangement of microchips in a cavity. The Castro-Macosko rheology model with Arrhenius temperature dependence is adopted in the viscosity model. Short-shot experiments are conducted to investigate the filling patterns at several time intervals. The results show that the rotated shape die-arrangement gives minimum filling time and better mould filling yield. The close agreement between the experimental and simulation results illustrates the applicability of the proposed numerical model.","PeriodicalId":55015,"journal":{"name":"IEEE Transactions on Advanced Packaging","volume":"33 1","pages":"438-446"},"PeriodicalIF":0.0,"publicationDate":"2010-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TADVP.2009.2034013","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62395428","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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