Pub Date : 2010-04-08DOI: 10.1109/TADVP.2010.2046166
Y. Lamy, K. Jinesh, F. Roozeboom, D. Gravesteijn, W. Besling
High-aspect ratio (12.5) through silicon vias (TSV) made in a silicon interposer have been electrically characterized in the direct current (dc) and microwave regimes for 3D interconnect applications. The vias were micro-machined in silicon, insulated, and filled with copper employing a bottom-up copper electroplating technique in a “via-first” approach. DC via resistance measurements show good agreement with the theoretical expected value (~ 16 mΩ) . Radio-frequency (RF) measurements up to 50 GHz have been performed on coplanar waveguides located on the back-side of the wafers and connected to the front-side with TSVs. The S-parameters indicate clearly the beneficial impact of double sided ground planes of the RF signals. The via resistance extracted from impedance measurements is in good agreement with dc values, while the inductance (53 pH) and capacitance (2.4 pF) of the TSV are much lower than conventional wire bonding, which makes the use of TSV very promising for 3D integration. An advanced analytical model is proposed for the interconnect system with vias and lines and shows very good agreement with the experimental data with a limited number of fitting parameters. This work gives a proof of concept for high aspect ratio TSV manufacturing and new insights to improve 3D interconnect modeling for systems-in-package applications in the microwave regime.
{"title":"RF Characterization and Analytical Modelling of Through Silicon Vias and Coplanar Waveguides for 3D Integration","authors":"Y. Lamy, K. Jinesh, F. Roozeboom, D. Gravesteijn, W. Besling","doi":"10.1109/TADVP.2010.2046166","DOIUrl":"https://doi.org/10.1109/TADVP.2010.2046166","url":null,"abstract":"High-aspect ratio (12.5) through silicon vias (TSV) made in a silicon interposer have been electrically characterized in the direct current (dc) and microwave regimes for 3D interconnect applications. The vias were micro-machined in silicon, insulated, and filled with copper employing a bottom-up copper electroplating technique in a “via-first” approach. DC via resistance measurements show good agreement with the theoretical expected value (~ 16 mΩ) . Radio-frequency (RF) measurements up to 50 GHz have been performed on coplanar waveguides located on the back-side of the wafers and connected to the front-side with TSVs. The S-parameters indicate clearly the beneficial impact of double sided ground planes of the RF signals. The via resistance extracted from impedance measurements is in good agreement with dc values, while the inductance (53 pH) and capacitance (2.4 pF) of the TSV are much lower than conventional wire bonding, which makes the use of TSV very promising for 3D integration. An advanced analytical model is proposed for the interconnect system with vias and lines and shows very good agreement with the experimental data with a limited number of fitting parameters. This work gives a proof of concept for high aspect ratio TSV manufacturing and new insights to improve 3D interconnect modeling for systems-in-package applications in the microwave regime.","PeriodicalId":55015,"journal":{"name":"IEEE Transactions on Advanced Packaging","volume":"33 1","pages":"1072-1079"},"PeriodicalIF":0.0,"publicationDate":"2010-04-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TADVP.2010.2046166","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62397069","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-04-01DOI: 10.1109/TADVP.2010.2046167
F. de Paulis, L. Raimondo, S. Connor, B. Archambeault, A. Orlandi
In this paper, an embedded electromagnetic bandgap structure is proposed for harmonic filtering of differential signal's undesired common mode components. Rather than use lumped circuit components and likely causing some degradation to the intended high speed differential signal, the embedded planar common mode filter causes no degradation to the intended signal, and enhances the signal integrity and electromagnetic compatibility performance of the system. Single ended and differential traces are considered and the impact of the common mode filtering is measured in terms of mixed mode scattering parameters and eye diagram metrics. The systematic procedure to design such a structure is outlined, and its design robustness is also verified.
{"title":"Design of a Common Mode Filter by Using Planar Electromagnetic Bandgap Structures","authors":"F. de Paulis, L. Raimondo, S. Connor, B. Archambeault, A. Orlandi","doi":"10.1109/TADVP.2010.2046167","DOIUrl":"https://doi.org/10.1109/TADVP.2010.2046167","url":null,"abstract":"In this paper, an embedded electromagnetic bandgap structure is proposed for harmonic filtering of differential signal's undesired common mode components. Rather than use lumped circuit components and likely causing some degradation to the intended high speed differential signal, the embedded planar common mode filter causes no degradation to the intended signal, and enhances the signal integrity and electromagnetic compatibility performance of the system. Single ended and differential traces are considered and the impact of the common mode filtering is measured in terms of mixed mode scattering parameters and eye diagram metrics. The systematic procedure to design such a structure is outlined, and its design robustness is also verified.","PeriodicalId":55015,"journal":{"name":"IEEE Transactions on Advanced Packaging","volume":"33 1","pages":"994-1002"},"PeriodicalIF":0.0,"publicationDate":"2010-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TADVP.2010.2046167","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62397085","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-29DOI: 10.1109/TADVP.2010.2044660
C. Tseng
In this paper, compact low-temperature co-fired ceramic (LTCC) rat-race couplers are developed using multilayered phase-delay and phase-advance T-equivalent sections. By taking advantage of the multilayered LTCC layout capability, compact 3-D phase-delay and phase-advance T-equivalent sections are designed, and then treated as fundamental elements to construct two types of LTCC rat-race couplers. One type of coupler consists of three phase-delay and a phase-advance sections, whereas the other type coupler is integrated by a phase-delay and three phase-advance sections. At the design frequency 2 GHz, both two types of couplers occupy 3.8 × 3.8 mm2 circuit sizes, namely areas of 0.025 ¿0 × 0.025 ¿0 , where ¿0 is the free-space wavelength. The measured results of the developed couplers agree the simulated results very well. It demonstrates that using multilayered phase-delay and phase-advance T-equivalent sections is an effective approach to miniaturize the circuit size of the rat-race coupler.
{"title":"Compact LTCC Rat-Race Couplers Using Multilayered Phase-Delay and Phase-Advance T-Equivalent Sections","authors":"C. Tseng","doi":"10.1109/TADVP.2010.2044660","DOIUrl":"https://doi.org/10.1109/TADVP.2010.2044660","url":null,"abstract":"In this paper, compact low-temperature co-fired ceramic (LTCC) rat-race couplers are developed using multilayered phase-delay and phase-advance T-equivalent sections. By taking advantage of the multilayered LTCC layout capability, compact 3-D phase-delay and phase-advance T-equivalent sections are designed, and then treated as fundamental elements to construct two types of LTCC rat-race couplers. One type of coupler consists of three phase-delay and a phase-advance sections, whereas the other type coupler is integrated by a phase-delay and three phase-advance sections. At the design frequency 2 GHz, both two types of couplers occupy 3.8 × 3.8 mm2 circuit sizes, namely areas of 0.025 ¿0 × 0.025 ¿0 , where ¿0 is the free-space wavelength. The measured results of the developed couplers agree the simulated results very well. It demonstrates that using multilayered phase-delay and phase-advance T-equivalent sections is an effective approach to miniaturize the circuit size of the rat-race coupler.","PeriodicalId":55015,"journal":{"name":"IEEE Transactions on Advanced Packaging","volume":"33 1","pages":"543-551"},"PeriodicalIF":0.0,"publicationDate":"2010-03-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TADVP.2010.2044660","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62397399","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-18DOI: 10.1109/TADVP.2010.2044411
Rui Wang, Jianming Jin
This paper describes a flexible time-stepping scheme for a recently developed hybrid field-circuit solver based on the extended time-domain finite element method (TDFEM) to alleviate the limitation on the use of a system-wide global time-step size. The proposed time-stepping scheme generalizes the strict synchronous coupling mechanism between the FEM and circuit subsystems and allows the signals in the different subsystems to be tracked and sampled at different time-step sizes. The signals from a slow subsystem with a larger time-step size are extrapolated, when necessary, for updating the signals in a fast subsystem with a smaller time-step size. The capability of the hybrid field-circuit solver with the proposed time-stepping scheme is further enhanced by the application of a tree-cotree splitting technique to the FEM subsystem, which helps reduce the iteration count per time step for a preconditioned iterative solution when the time-step size of the FEM subsystem becomes relatively large. With the flexibility of choosing subsystem-specific time-step sizes, the proposed time-stepping scheme improves the computational efficiency of the existing TDFEM-based hybrid field-circuit solver especially when the computational cost associated with the slow subsystems is much higher than that associated with the fast subsystems.
{"title":"A Flexible Time-Stepping Scheme for Hybrid Field-Circuit Simulation Based on the Extended Time-Domain Finite Element Method","authors":"Rui Wang, Jianming Jin","doi":"10.1109/TADVP.2010.2044411","DOIUrl":"https://doi.org/10.1109/TADVP.2010.2044411","url":null,"abstract":"This paper describes a flexible time-stepping scheme for a recently developed hybrid field-circuit solver based on the extended time-domain finite element method (TDFEM) to alleviate the limitation on the use of a system-wide global time-step size. The proposed time-stepping scheme generalizes the strict synchronous coupling mechanism between the FEM and circuit subsystems and allows the signals in the different subsystems to be tracked and sampled at different time-step sizes. The signals from a slow subsystem with a larger time-step size are extrapolated, when necessary, for updating the signals in a fast subsystem with a smaller time-step size. The capability of the hybrid field-circuit solver with the proposed time-stepping scheme is further enhanced by the application of a tree-cotree splitting technique to the FEM subsystem, which helps reduce the iteration count per time step for a preconditioned iterative solution when the time-step size of the FEM subsystem becomes relatively large. With the flexibility of choosing subsystem-specific time-step sizes, the proposed time-stepping scheme improves the computational efficiency of the existing TDFEM-based hybrid field-circuit solver especially when the computational cost associated with the slow subsystems is much higher than that associated with the fast subsystems.","PeriodicalId":55015,"journal":{"name":"IEEE Transactions on Advanced Packaging","volume":"33 1","pages":"769-776"},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TADVP.2010.2044411","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62397215","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-11DOI: 10.1109/TADVP.2010.2043673
Jaemin Kim, Woojin Lee, Yujeong Shim, J. Shim, Kiyeong Kim, J. Pak, Joungho Kim
In this paper, a new modeling method for estimating the impedance properties in a chip-package hierarchical power distribution network (PDN) is proposed. The key ideas of the proposed modeling method are to decompose the chip-package hierarchical PDN into several structures, independently calculate the decomposed structures, and extract the whole structure's impedance by using a segmentation method. For the impedance calculations of the independently decomposed structures, a new method based on proposed analytic expressions is introduced for a chip level PDN, a resonant cavity model is used for a package level PDN, and equivalent circuit models are used for interconnections. The proposed method has been successfully verified by comparisons with measurements using a fabricated test vehicle in the frequency domain range up to 20 GHz, and it shows improved accuracy as well as computational superiority compared to EM simulations. Finally, the impedance properties in a chip-package hierarchical PDN are thoroughly investigated and analyzed.
{"title":"Chip-Package Hierarchical Power Distribution Network Modeling and Analysis Based on a Segmentation Method","authors":"Jaemin Kim, Woojin Lee, Yujeong Shim, J. Shim, Kiyeong Kim, J. Pak, Joungho Kim","doi":"10.1109/TADVP.2010.2043673","DOIUrl":"https://doi.org/10.1109/TADVP.2010.2043673","url":null,"abstract":"In this paper, a new modeling method for estimating the impedance properties in a chip-package hierarchical power distribution network (PDN) is proposed. The key ideas of the proposed modeling method are to decompose the chip-package hierarchical PDN into several structures, independently calculate the decomposed structures, and extract the whole structure's impedance by using a segmentation method. For the impedance calculations of the independently decomposed structures, a new method based on proposed analytic expressions is introduced for a chip level PDN, a resonant cavity model is used for a package level PDN, and equivalent circuit models are used for interconnections. The proposed method has been successfully verified by comparisons with measurements using a fabricated test vehicle in the frequency domain range up to 20 GHz, and it shows improved accuracy as well as computational superiority compared to EM simulations. Finally, the impedance properties in a chip-package hierarchical PDN are thoroughly investigated and analyzed.","PeriodicalId":55015,"journal":{"name":"IEEE Transactions on Advanced Packaging","volume":"33 1","pages":"647-659"},"PeriodicalIF":0.0,"publicationDate":"2010-03-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TADVP.2010.2043673","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62396754","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-11DOI: 10.1109/TADVP.2009.2036153
K. M. Chen
This paper evaluates the effect of the solder ball material and chip thickness on board-level reliability using low-K wafer-level chip-scale packaging (WLCSP). The composition of the three evaluated solder ball materials includes SnAg1.0Cu0.5, SnAg2.0Cu0.5, and SnAg2.6Cu0.6. The chip thickness is ranging from 200, 300, and 775 ¿m. Initially, the high temperature storage and ten-time multiple reflow tests were used as the wafer-level reliability test items. The work uses both the low speed (500 ¿m/s) and the high speed (200 mm/s and 1 m/s) solder ball shear test to compare the shear force, displacement, and fracture energy of the three solder compositions. The high speed shear test result shows the high silver content correlates to small displacement and the low fracture energy. Next, the finite element model was employed to compare the board level chip and solder ball stress for these three different chip thicknesses. The finite element method simulation results indicate the thinner chip implies the preferred thermal fatigue cycles. In addition, the drop test results show the chip thickness of 200 and 300 ¿m improve the drop test performance (81 drops and 88 drops) by 20.9%-31.34% than that of chip thickness of 775 ¿m. Moreover, the chip thickness of 200 and 300 ¿m substantially enhance the thermal fatigue life (665 cycles and 655 cycles) by 81.44%-84.21% than that of chip thickness of 775 ¿m using the SnAg1.0 Cu0.5. Notably, the experimental results correlate well with the simulation trend. This work provides a design guideline for selecting the favorable solder materials and the chip thickness to obtain the satisfactory board-level reliability of the low-K WLCSP packaging.
{"title":"Lead-Free Solder Material and Chip Thickness Impact on Board-Level Reliability for Low-K WLCSP","authors":"K. M. Chen","doi":"10.1109/TADVP.2009.2036153","DOIUrl":"https://doi.org/10.1109/TADVP.2009.2036153","url":null,"abstract":"This paper evaluates the effect of the solder ball material and chip thickness on board-level reliability using low-K wafer-level chip-scale packaging (WLCSP). The composition of the three evaluated solder ball materials includes SnAg1.0Cu0.5, SnAg2.0Cu0.5, and SnAg2.6Cu0.6. The chip thickness is ranging from 200, 300, and 775 ¿m. Initially, the high temperature storage and ten-time multiple reflow tests were used as the wafer-level reliability test items. The work uses both the low speed (500 ¿m/s) and the high speed (200 mm/s and 1 m/s) solder ball shear test to compare the shear force, displacement, and fracture energy of the three solder compositions. The high speed shear test result shows the high silver content correlates to small displacement and the low fracture energy. Next, the finite element model was employed to compare the board level chip and solder ball stress for these three different chip thicknesses. The finite element method simulation results indicate the thinner chip implies the preferred thermal fatigue cycles. In addition, the drop test results show the chip thickness of 200 and 300 ¿m improve the drop test performance (81 drops and 88 drops) by 20.9%-31.34% than that of chip thickness of 775 ¿m. Moreover, the chip thickness of 200 and 300 ¿m substantially enhance the thermal fatigue life (665 cycles and 655 cycles) by 81.44%-84.21% than that of chip thickness of 775 ¿m using the SnAg1.0 Cu0.5. Notably, the experimental results correlate well with the simulation trend. This work provides a design guideline for selecting the favorable solder materials and the chip thickness to obtain the satisfactory board-level reliability of the low-K WLCSP packaging.","PeriodicalId":55015,"journal":{"name":"IEEE Transactions on Advanced Packaging","volume":"33 1","pages":"340-347"},"PeriodicalIF":0.0,"publicationDate":"2010-03-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TADVP.2009.2036153","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62395669","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-01DOI: 10.1109/TADVP.2009.2035999
B. Dang, M. Bakir, D. Sekar, C. King, J. Meindl
Power dissipation in microprocessors is projected to reach a level that may necessitate chip-level liquid cooling in the near future. An on-chip microchannel heat sink can reduce the total thermal interfaces between an integrated circuit chip and the convective cooling medium and therefore yield smaller junction-to-ambient thermal resistance. This paper reports the fabrication, assembly, and testing of a silicon chip with complementary metal-oxide-semiconductor process compatible microchannel heat sink and thermofluidic chip input/output (I/O) interconnects fabricated using wafer-level batch processing. Ultra-small form factor, low-cost fabrication and assembly (system integration) are achieved for 2D and 3D chips, as the microchannel heat sink is fabricated directly on back-side of each chip. Through-wafer electrical and fluidic vias are used to interconnect the monolithically integrated microchannel heat sink to thermofluidic chip I/O interconnections. The feasibility of the novel fluidic I/O interconnect is demonstrated through preliminary thermal resistance measurements.
{"title":"Integrated Microfluidic Cooling and Interconnects for 2D and 3D Chips","authors":"B. Dang, M. Bakir, D. Sekar, C. King, J. Meindl","doi":"10.1109/TADVP.2009.2035999","DOIUrl":"https://doi.org/10.1109/TADVP.2009.2035999","url":null,"abstract":"Power dissipation in microprocessors is projected to reach a level that may necessitate chip-level liquid cooling in the near future. An on-chip microchannel heat sink can reduce the total thermal interfaces between an integrated circuit chip and the convective cooling medium and therefore yield smaller junction-to-ambient thermal resistance. This paper reports the fabrication, assembly, and testing of a silicon chip with complementary metal-oxide-semiconductor process compatible microchannel heat sink and thermofluidic chip input/output (I/O) interconnects fabricated using wafer-level batch processing. Ultra-small form factor, low-cost fabrication and assembly (system integration) are achieved for 2D and 3D chips, as the microchannel heat sink is fabricated directly on back-side of each chip. Through-wafer electrical and fluidic vias are used to interconnect the monolithically integrated microchannel heat sink to thermofluidic chip I/O interconnections. The feasibility of the novel fluidic I/O interconnect is demonstrated through preliminary thermal resistance measurements.","PeriodicalId":55015,"journal":{"name":"IEEE Transactions on Advanced Packaging","volume":"33 1","pages":"79-87"},"PeriodicalIF":0.0,"publicationDate":"2010-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TADVP.2009.2035999","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62395511","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-03-01DOI: 10.1109/TADVP.2009.2034384
F. Hung, T. Lui, Li-Hui Chen, Yi-Chang Lin
In the present study, the neck fracture properties of annealed wire with ¿ = 20 ¿m (0.8 mil) at 200°C ~ 300°C for 1 h and unannealed wire were compared. The microstructural characteristics, the mechanical properties and the texture transition using electron back scatter diffraction methods before and after an electric flame-off (EFO) process were also studied. Experimental results indicate that the annealing temperatures of more than 225°C, the 20 ¿m copper wires possessed a fully annealed structure, the tensile strength and the hardness decreased, and the elongation was raised. Through recrystallization, the matrix structure transferred from long, thin grains to equiaxed grains and a few annealed twins. The microstructure of the free air ball (FAB) after an EFO process consisted of column-like grains, and grew from the heat-affected zone (HAZ) to the Cu ball. For the 225°C annealed and unannealed wires, their preferred orientations on the wire and the neck were ¿100¿//AD. Under the thermal effect of EFO, the orientation of the Cu balls were mainly ¿101¿//AD and ¿111¿//AD for annealed wires. Additionally, the hardness of the Cu balls and the strength of the neck sites of the EFO wires were able to affect the reliability of the copper wire bonding.
{"title":"Recrystallization, Electric Flame-Off Characteristics, and Electron Backscatter Diffraction of Copper Bonding Wires","authors":"F. Hung, T. Lui, Li-Hui Chen, Yi-Chang Lin","doi":"10.1109/TADVP.2009.2034384","DOIUrl":"https://doi.org/10.1109/TADVP.2009.2034384","url":null,"abstract":"In the present study, the neck fracture properties of annealed wire with ¿ = 20 ¿m (0.8 mil) at 200°C ~ 300°C for 1 h and unannealed wire were compared. The microstructural characteristics, the mechanical properties and the texture transition using electron back scatter diffraction methods before and after an electric flame-off (EFO) process were also studied. Experimental results indicate that the annealing temperatures of more than 225°C, the 20 ¿m copper wires possessed a fully annealed structure, the tensile strength and the hardness decreased, and the elongation was raised. Through recrystallization, the matrix structure transferred from long, thin grains to equiaxed grains and a few annealed twins. The microstructure of the free air ball (FAB) after an EFO process consisted of column-like grains, and grew from the heat-affected zone (HAZ) to the Cu ball. For the 225°C annealed and unannealed wires, their preferred orientations on the wire and the neck were ¿100¿//AD. Under the thermal effect of EFO, the orientation of the Cu balls were mainly ¿101¿//AD and ¿111¿//AD for annealed wires. Additionally, the hardness of the Cu balls and the strength of the neck sites of the EFO wires were able to affect the reliability of the copper wire bonding.","PeriodicalId":55015,"journal":{"name":"IEEE Transactions on Advanced Packaging","volume":"33 1","pages":"58-63"},"PeriodicalIF":0.0,"publicationDate":"2010-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TADVP.2009.2034384","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62395282","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-02-25DOI: 10.1109/TADVP.2010.2042447
C. Chou, T. Hung, Chao-Jen Huang, K. Chiang
Accompanying the increasing popularity of portable and handheld products, high reliability for board level drop test becomes a great concern for semiconductor and electronic product manufacturers. Meanwhile, for design purpose, a reliable impact life prediction model is also a must in estimating the performance of packages subjected to drop impact. In this study, a stress-buffer-enhanced package is proposed to meet the high drop test performance requirement. Both the drop test experiment and numerical simulation were performed. The experimental drop test results showed that a different failure mode, the broken metal trace at package side, was observed in the stress-buffer-enhanced package. Several drop test simulations were conducted to elucidate the mechanical behavior of the test board and packages during the blink of impact. Based on the simulation results, a metal trace impact life prediction model is then developed for the novel stress-buffer-enhanced package to forecast the number of drops. Unlike the thermal cycle test, the dynamic response of the drop impact is irregular and not cyclic. As such, the concept of cumulative damage is considered in the life prediction model. Several characteristics of the metal trace dynamic response, the cumulative fatigue life, the cumulative plastic strain, and the cumulative effective plastic deformation, were studied during the development of the life prediction model. The results showed that the cumulative plastic strain of the metal trace could accurately predict impact life.
{"title":"Development of Empirical Equations for Metal Trace Failure Prediction of Wafer Level Package Under Board Level Drop Test","authors":"C. Chou, T. Hung, Chao-Jen Huang, K. Chiang","doi":"10.1109/TADVP.2010.2042447","DOIUrl":"https://doi.org/10.1109/TADVP.2010.2042447","url":null,"abstract":"Accompanying the increasing popularity of portable and handheld products, high reliability for board level drop test becomes a great concern for semiconductor and electronic product manufacturers. Meanwhile, for design purpose, a reliable impact life prediction model is also a must in estimating the performance of packages subjected to drop impact. In this study, a stress-buffer-enhanced package is proposed to meet the high drop test performance requirement. Both the drop test experiment and numerical simulation were performed. The experimental drop test results showed that a different failure mode, the broken metal trace at package side, was observed in the stress-buffer-enhanced package. Several drop test simulations were conducted to elucidate the mechanical behavior of the test board and packages during the blink of impact. Based on the simulation results, a metal trace impact life prediction model is then developed for the novel stress-buffer-enhanced package to forecast the number of drops. Unlike the thermal cycle test, the dynamic response of the drop impact is irregular and not cyclic. As such, the concept of cumulative damage is considered in the life prediction model. Several characteristics of the metal trace dynamic response, the cumulative fatigue life, the cumulative plastic strain, and the cumulative effective plastic deformation, were studied during the development of the life prediction model. The results showed that the cumulative plastic strain of the metal trace could accurately predict impact life.","PeriodicalId":55015,"journal":{"name":"IEEE Transactions on Advanced Packaging","volume":"33 1","pages":"681-689"},"PeriodicalIF":0.0,"publicationDate":"2010-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TADVP.2010.2042447","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62396672","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-02-25DOI: 10.1109/TADVP.2009.2037729
K. Zoschke, T. Fischer, M. Topper, K. Samulewicz, O. Wunsch, J. Roder, M. Lutz, O. Ehrmann, H. Reichl
Focus of this work was the development and optimization of process techniques for the application of Polyimide (PI) or Polybenzoxazole (PBO) to act as dielectric material together with semi-additive copper as conductive material in a thin film multilayer buildup, which is suitable for the integration of all three types of passive components. A thin film set up including seven layers was used to create integrated coils with values between 1 and 80 nH , integrated resistors with values between 100 ¿ and 100 k¿ as well as integrated radio-frequency (RF) filters for application between 2 and 5 GHz. As substrate material both low resistivity silicon and glass (Borofloat 33) was used, which influences the quality factor of the coils as well as the filter performance substantially. The fabricated structures performed well in thermal cycling tests, where no critical failure could be observed after 3000 thermal cycles for all examined components. The RF components have shown no critical deviations between initial measurements and measurements performed after thermal cycling. The resistor values have shown no deviations between the measurements, which have been taken before and after thermal cycling. Thus Polyimide/Polybenzoxazole/copper multilayer wiring represents a reliable and versatile base technology for the fabrication of passive components at wafer level.
{"title":"Wafer Level Processing of Integrated Passive Components Using Polyimide or Polybenzoxazole/Copper Multilayer Technology","authors":"K. Zoschke, T. Fischer, M. Topper, K. Samulewicz, O. Wunsch, J. Roder, M. Lutz, O. Ehrmann, H. Reichl","doi":"10.1109/TADVP.2009.2037729","DOIUrl":"https://doi.org/10.1109/TADVP.2009.2037729","url":null,"abstract":"Focus of this work was the development and optimization of process techniques for the application of Polyimide (PI) or Polybenzoxazole (PBO) to act as dielectric material together with semi-additive copper as conductive material in a thin film multilayer buildup, which is suitable for the integration of all three types of passive components. A thin film set up including seven layers was used to create integrated coils with values between 1 and 80 nH , integrated resistors with values between 100 ¿ and 100 k¿ as well as integrated radio-frequency (RF) filters for application between 2 and 5 GHz. As substrate material both low resistivity silicon and glass (Borofloat 33) was used, which influences the quality factor of the coils as well as the filter performance substantially. The fabricated structures performed well in thermal cycling tests, where no critical failure could be observed after 3000 thermal cycles for all examined components. The RF components have shown no critical deviations between initial measurements and measurements performed after thermal cycling. The resistor values have shown no deviations between the measurements, which have been taken before and after thermal cycling. Thus Polyimide/Polybenzoxazole/copper multilayer wiring represents a reliable and versatile base technology for the fabrication of passive components at wafer level.","PeriodicalId":55015,"journal":{"name":"IEEE Transactions on Advanced Packaging","volume":"33 1","pages":"398-407"},"PeriodicalIF":0.0,"publicationDate":"2010-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TADVP.2009.2037729","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62395639","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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