Pub Date : 2010-02-01DOI: 10.1109/TADVP.2009.2025263
D. Paul, N. Nakhla, R. Achar, M. Nakhla
In a system containing high-speed interconnects, the presence of a large number of coupled lines seriously limits the ability to perform fast simulations. In this paper, a parallel algorithm is presented that allows for simulations of massively coupled interconnects to be performed efficiently. New methods based on physical and time-domain partitioning are developed to create parallelism during transient simulations of large coupled interconnects. In addition, the proposed method exploits the recently developed waveform relaxation techniques to decouple and parallelize the large coupled simulation problem. In this approach, for a simulation of nL lines run on nP processors, the computational complexity is O(nLnP -1). This provides considerable savings as opposed to O(nL ß ), 3 ¿ ß ¿ 4 for full coupled-line simulations.
{"title":"Parallel Simulation of Massively Coupled Interconnect Networks","authors":"D. Paul, N. Nakhla, R. Achar, M. Nakhla","doi":"10.1109/TADVP.2009.2025263","DOIUrl":"https://doi.org/10.1109/TADVP.2009.2025263","url":null,"abstract":"In a system containing high-speed interconnects, the presence of a large number of coupled lines seriously limits the ability to perform fast simulations. In this paper, a parallel algorithm is presented that allows for simulations of massively coupled interconnects to be performed efficiently. New methods based on physical and time-domain partitioning are developed to create parallelism during transient simulations of large coupled interconnects. In addition, the proposed method exploits the recently developed waveform relaxation techniques to decouple and parallelize the large coupled simulation problem. In this approach, for a simulation of nL lines run on nP processors, the computational complexity is O(nLnP -1). This provides considerable savings as opposed to O(nL ß ), 3 ¿ ß ¿ 4 for full coupled-line simulations.","PeriodicalId":55015,"journal":{"name":"IEEE Transactions on Advanced Packaging","volume":"33 1","pages":"115-127"},"PeriodicalIF":0.0,"publicationDate":"2010-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TADVP.2009.2025263","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62391886","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-02-01DOI: 10.1109/TADVP.2009.2029560
A. Charest, M. Nakhla, R. Achar, D. Saraswat, N. Soveiko, I. Erdin
This paper introduces a new time-domain approach for compact macromodeling of multiport high-speed circuits with long delays, characterized by tabulated data. The algorithm is based on partitioning the data in the time-domain and subsequently, approximating each partition via delayed rational functions. This results in a compact low-order macromodel in the form of delayed differential equations, which can be efficiently analyzed in the time-domain using circuit simulators.
{"title":"Time Domain Delay Extraction-Based Macromodeling Algorithm for Long-Delay Networks","authors":"A. Charest, M. Nakhla, R. Achar, D. Saraswat, N. Soveiko, I. Erdin","doi":"10.1109/TADVP.2009.2029560","DOIUrl":"https://doi.org/10.1109/TADVP.2009.2029560","url":null,"abstract":"This paper introduces a new time-domain approach for compact macromodeling of multiport high-speed circuits with long delays, characterized by tabulated data. The algorithm is based on partitioning the data in the time-domain and subsequently, approximating each partition via delayed rational functions. This results in a compact low-order macromodel in the form of delayed differential equations, which can be efficiently analyzed in the time-domain using circuit simulators.","PeriodicalId":55015,"journal":{"name":"IEEE Transactions on Advanced Packaging","volume":"33 1","pages":"219-235"},"PeriodicalIF":0.0,"publicationDate":"2010-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TADVP.2009.2029560","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62394058","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-02-01DOI: 10.1109/TADVP.2009.2028636
Hsin-Chia Lu, T. Chan, C. Chen, Chia-Ming Liu, Heng-Jui Hsing, Po-Sheng Huang
In RF/microwave circuit design, inductor design is one of the most difficult and time-consuming tasks due to the tedious trial-and-error optimization process to achieve the target specifications such as inductance, quality factor and occupied space. This paper brings forward a fast spiral inductor synthesis method, which automatically generates physical layout of inductors according to electrical specifications. By fusion of substrate-aware partial element equivalent circuit (PEEC) model with nonlinear optimization engine, our modeling and synthesis strategies have been verified with industrial field solver and measurement results. Our calculation results got less than 7% error for inductance and less than 9% for quality factor as compared to the results from full-wave electromagnetic simulation software. This can provide a fast and good initial inductor design for designer.
{"title":"LTCC Spiral Inductor Synthesis and Optimization With Measurement Verification","authors":"Hsin-Chia Lu, T. Chan, C. Chen, Chia-Ming Liu, Heng-Jui Hsing, Po-Sheng Huang","doi":"10.1109/TADVP.2009.2028636","DOIUrl":"https://doi.org/10.1109/TADVP.2009.2028636","url":null,"abstract":"In RF/microwave circuit design, inductor design is one of the most difficult and time-consuming tasks due to the tedious trial-and-error optimization process to achieve the target specifications such as inductance, quality factor and occupied space. This paper brings forward a fast spiral inductor synthesis method, which automatically generates physical layout of inductors according to electrical specifications. By fusion of substrate-aware partial element equivalent circuit (PEEC) model with nonlinear optimization engine, our modeling and synthesis strategies have been verified with industrial field solver and measurement results. Our calculation results got less than 7% error for inductance and less than 9% for quality factor as compared to the results from full-wave electromagnetic simulation software. This can provide a fast and good initial inductor design for designer.","PeriodicalId":55015,"journal":{"name":"IEEE Transactions on Advanced Packaging","volume":"33 1","pages":"160-168"},"PeriodicalIF":0.0,"publicationDate":"2010-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TADVP.2009.2028636","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62394462","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-02-01DOI: 10.1109/TADVP.2009.2035304
B. Jaiswal, M. Roy, A. Titus
With the increasing complexity in the die and package designs and ever increasing cost pressure in today's microelectronic industry, the design for input/output (I/O) routing has assumed a vital role in the overall product design. This scenario is primarily driven by the increase in the I/O terminal counts in both die and package. Several authors have already described the possibility of using various escape routing models in order to maximize the number of I/Os in a given area. However, these models suffer from many drawbacks and fail to address the importance of processing factors and the actual manufacturing conditions. Therefore, a new design guideline for escape routing has been developed to achieve the maximum I/O density under the actual manufacturing, processing and cost related constraints. The correlation between the real world constraints and their impact on I/O routing has been explored and used as a foundation for developing design guidelines. This approach has been presented through a comprehensive case study that covers various design scenarios, provides the right set of real world trade-offs that need to be considered and simultaneously highlights the drawbacks in existing models.
{"title":"Escape Routing in Modern Area Array Packaging: An Analysis of Need, Trend, and Capability","authors":"B. Jaiswal, M. Roy, A. Titus","doi":"10.1109/TADVP.2009.2035304","DOIUrl":"https://doi.org/10.1109/TADVP.2009.2035304","url":null,"abstract":"With the increasing complexity in the die and package designs and ever increasing cost pressure in today's microelectronic industry, the design for input/output (I/O) routing has assumed a vital role in the overall product design. This scenario is primarily driven by the increase in the I/O terminal counts in both die and package. Several authors have already described the possibility of using various escape routing models in order to maximize the number of I/Os in a given area. However, these models suffer from many drawbacks and fail to address the importance of processing factors and the actual manufacturing conditions. Therefore, a new design guideline for escape routing has been developed to achieve the maximum I/O density under the actual manufacturing, processing and cost related constraints. The correlation between the real world constraints and their impact on I/O routing has been explored and used as a foundation for developing design guidelines. This approach has been presented through a comprehensive case study that covers various design scenarios, provides the right set of real world trade-offs that need to be considered and simultaneously highlights the drawbacks in existing models.","PeriodicalId":55015,"journal":{"name":"IEEE Transactions on Advanced Packaging","volume":"33 1","pages":"13-18"},"PeriodicalIF":0.0,"publicationDate":"2010-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TADVP.2009.2035304","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62395886","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-02-01DOI: 10.1109/TADVP.2009.2024212
K. Kang, J. Brinkhoff, Jinglin Shi, F. Lin
Transmission lines are fundamental elements in millimeter-wave circuits. In this paper, on-chip coupled transmission lines, fabricated in a commercial 0.18 ¿m complementary metal-oxide semiconductor process, have been modeled, based on measured 50 GHz four-port scattering-parameters. The two-port open-short deembedding technique and thru deembedding method were successfully extended and applied to the four-port structures presented here. The accuracy of the deembedding techniques was verified by full-wave electromagnetic simulation. Based on the deembedded S-parameters, a SPICE-compatible equivalent circuit model of on-chip coupled transmission lines was extracted. Simulation and measurement results agree well over the entire frequency band from 100 MHz up to 50 GHz.
{"title":"On-Chip Coupled Transmission Line Modeling for Millimeter-Wave Applications Using Four-Port Measurements","authors":"K. Kang, J. Brinkhoff, Jinglin Shi, F. Lin","doi":"10.1109/TADVP.2009.2024212","DOIUrl":"https://doi.org/10.1109/TADVP.2009.2024212","url":null,"abstract":"Transmission lines are fundamental elements in millimeter-wave circuits. In this paper, on-chip coupled transmission lines, fabricated in a commercial 0.18 ¿m complementary metal-oxide semiconductor process, have been modeled, based on measured 50 GHz four-port scattering-parameters. The two-port open-short deembedding technique and thru deembedding method were successfully extended and applied to the four-port structures presented here. The accuracy of the deembedding techniques was verified by full-wave electromagnetic simulation. Based on the deembedded S-parameters, a SPICE-compatible equivalent circuit model of on-chip coupled transmission lines was extracted. Simulation and measurement results agree well over the entire frequency band from 100 MHz up to 50 GHz.","PeriodicalId":55015,"journal":{"name":"IEEE Transactions on Advanced Packaging","volume":"33 1","pages":"153-159"},"PeriodicalIF":0.0,"publicationDate":"2010-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TADVP.2009.2024212","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62391302","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-02-01DOI: 10.1109/TADVP.2009.2033941
Chien-Chen Lee, Chang-Chun Lee, K. Chiang
Electromigration is a reliability concern of microelectronic interconnections, especially for flip chip solder bump with high current density applied. This study shows that with the line-to-bump geometry in a flip chip solder joint, the current density changes significantly between the Al trace and the bump, while the current crowding effect generates more heat between them. This large Joule heating under high current density can enhance the migration of Sn atoms at the current entrance of the solder bump, and cause the void formation at the entrance point. The present study finds two kinds of electromigration failure modes at the cathode/chip side of the solder bump: the pancake-type and the cotton-type void. The experimental finding shows that the effects of polarity and tilting are key factors to observe in the electromigration behavior of SnAg3.0Cu0.5 solder bumps. Consequently, this study has designed a 3-D numerical model and a corresponding test vehicle to verify the numerical finding. The maximum current density is simulated through the finite element method to provide a better understanding of local heat and current crowding. This study finds that the current crowding ratio is reduced linearly while the void formation is increased. Furthermore, it is concluded that there is a linear relationship between the growth of the intermetallic compound (IMC) layer and the applied current density at the anode/substrate side.
{"title":"Electromigration Characteristic of SnAg $_{3.0}$ Cu $_{0.5}$ Flip Chip Interconnection","authors":"Chien-Chen Lee, Chang-Chun Lee, K. Chiang","doi":"10.1109/TADVP.2009.2033941","DOIUrl":"https://doi.org/10.1109/TADVP.2009.2033941","url":null,"abstract":"Electromigration is a reliability concern of microelectronic interconnections, especially for flip chip solder bump with high current density applied. This study shows that with the line-to-bump geometry in a flip chip solder joint, the current density changes significantly between the Al trace and the bump, while the current crowding effect generates more heat between them. This large Joule heating under high current density can enhance the migration of Sn atoms at the current entrance of the solder bump, and cause the void formation at the entrance point. The present study finds two kinds of electromigration failure modes at the cathode/chip side of the solder bump: the pancake-type and the cotton-type void. The experimental finding shows that the effects of polarity and tilting are key factors to observe in the electromigration behavior of SnAg3.0Cu0.5 solder bumps. Consequently, this study has designed a 3-D numerical model and a corresponding test vehicle to verify the numerical finding. The maximum current density is simulated through the finite element method to provide a better understanding of local heat and current crowding. This study finds that the current crowding ratio is reduced linearly while the void formation is increased. Furthermore, it is concluded that there is a linear relationship between the growth of the intermetallic compound (IMC) layer and the applied current density at the anode/substrate side.","PeriodicalId":55015,"journal":{"name":"IEEE Transactions on Advanced Packaging","volume":"33 1","pages":"189-195"},"PeriodicalIF":0.0,"publicationDate":"2010-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TADVP.2009.2033941","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62394826","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-02-01DOI: 10.1109/TADVP.2009.2033809
Sungchul Joo, D. Baldwin
Nano-particle silver (NPS) conductors are increasingly being investigated for package level electronics applications. Unlike traditional thick film materials and conductive inks, nano-particle conductors often do not incorporate compounds to promote interfacial adhesion such as binders used in thick films and polymer adhesives used in conductive inks as these adhesion promoters can degrade the electrical performance. The NPS is concerned with low adhesion to most of processed polymer surface such as liquid crystal polymer (LCP), polyimide, and benzocyclobutene (BCB). Moreover, the adhesion mechanism of NPS has not been identified yet. Thus, as a first step to identify NPS adhesion mechanism and thus, to improve NPS adhesion, quantitative measurement of the adhesion strength of NPS is necessary. Since conventional adhesion test methods are not directly applicable to thin (~ 2 ¿m) NPS film adhesion test, a new adhesion test method is developed in this paper to estimate the adhesion strength of NPS films. The newly developed adhesion test method is called modified button shear test (MBST) because it modifies the conventional button shear test and integrates the generally known die shear test. The MBST is used for measuring not only interfacial bond strength, but also interfacial fracture energy. The interfacial bond strength in tension and the interfacial fracture energy of NPS with LCP substrate measured by MBST are 24.4 MPa and 17.2 J/m2, respectively. The MBST is generic in nature and can be extended to other thin films adhesion test for measuring interfacial bond strength and interfacial fracture energy.
{"title":"Analysis of Adhesion and Fracture Energy of Nano-Particle Silver in Electronics Packaging Applications","authors":"Sungchul Joo, D. Baldwin","doi":"10.1109/TADVP.2009.2033809","DOIUrl":"https://doi.org/10.1109/TADVP.2009.2033809","url":null,"abstract":"Nano-particle silver (NPS) conductors are increasingly being investigated for package level electronics applications. Unlike traditional thick film materials and conductive inks, nano-particle conductors often do not incorporate compounds to promote interfacial adhesion such as binders used in thick films and polymer adhesives used in conductive inks as these adhesion promoters can degrade the electrical performance. The NPS is concerned with low adhesion to most of processed polymer surface such as liquid crystal polymer (LCP), polyimide, and benzocyclobutene (BCB). Moreover, the adhesion mechanism of NPS has not been identified yet. Thus, as a first step to identify NPS adhesion mechanism and thus, to improve NPS adhesion, quantitative measurement of the adhesion strength of NPS is necessary. Since conventional adhesion test methods are not directly applicable to thin (~ 2 ¿m) NPS film adhesion test, a new adhesion test method is developed in this paper to estimate the adhesion strength of NPS films. The newly developed adhesion test method is called modified button shear test (MBST) because it modifies the conventional button shear test and integrates the generally known die shear test. The MBST is used for measuring not only interfacial bond strength, but also interfacial fracture energy. The interfacial bond strength in tension and the interfacial fracture energy of NPS with LCP substrate measured by MBST are 24.4 MPa and 17.2 J/m2, respectively. The MBST is generic in nature and can be extended to other thin films adhesion test for measuring interfacial bond strength and interfacial fracture energy.","PeriodicalId":55015,"journal":{"name":"IEEE Transactions on Advanced Packaging","volume":"33 1","pages":"48-57"},"PeriodicalIF":0.0,"publicationDate":"2010-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TADVP.2009.2033809","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62394969","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-02-01DOI: 10.1109/TADVP.2009.2034137
Li-Han Hsu, Wei-Cheng Wu, E. Chang, H. Zirath, Yun-Chi Wu, Chin-Te Wang, Ching-Ting Lee
This paper presents the parametric study of RF-via (0-level) and flip-chip bump (1-level) transitions for applications of packaging coplanar RF-MEMS devices. The key parameters were found to be the bumps' and vias' positions and the overlap of the metal pads, which should be carefully considered in the entire two levels of packages. The length of the backside transmission line, determining the MEMS substrate area, showed minor influence on the interconnect performance. With the experimental results, the design rules have been developed and established. The optimized interconnect structure for the two levels of packages demonstrates the return loss beyond 15 dB and the insertion loss within 0.6 dB from dc to 60 GHz.
{"title":"Design and Fabrication of 0/1-Level RF-Via Interconnect for RF-MEMS Packaging Applications","authors":"Li-Han Hsu, Wei-Cheng Wu, E. Chang, H. Zirath, Yun-Chi Wu, Chin-Te Wang, Ching-Ting Lee","doi":"10.1109/TADVP.2009.2034137","DOIUrl":"https://doi.org/10.1109/TADVP.2009.2034137","url":null,"abstract":"This paper presents the parametric study of RF-via (0-level) and flip-chip bump (1-level) transitions for applications of packaging coplanar RF-MEMS devices. The key parameters were found to be the bumps' and vias' positions and the overlap of the metal pads, which should be carefully considered in the entire two levels of packages. The length of the backside transmission line, determining the MEMS substrate area, showed minor influence on the interconnect performance. With the experimental results, the design rules have been developed and established. The optimized interconnect structure for the two levels of packages demonstrates the return loss beyond 15 dB and the insertion loss within 0.6 dB from dc to 60 GHz.","PeriodicalId":55015,"journal":{"name":"IEEE Transactions on Advanced Packaging","volume":"33 1","pages":"30-36"},"PeriodicalIF":0.0,"publicationDate":"2010-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TADVP.2009.2034137","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62395000","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-02-01DOI: 10.1109/TADVP.2009.2034334
Guanqun Wu, Yi-Che Chen, Tzong-Lin Wu
By embedding periodically high-K rods in the package substrate, a hybrid photonic crystal power/ground layers (PCPL) is proposed with stopband enhancement for power/ground noise suppression. The hybrid PCPL consists of two different lattice structures, which have the same pitch but different radii of the high-K rods. Using the gap map of the photonic crystal lattice, the enhanced stopband can be synthesized by designing these two different lattices with compensated stopband. An implementation approach, which is compatible to the standard fabrication process of package or printed circuit board (PCB), is also proposed in this paper. The high-K rods are considered as surface mount technology (SMT)-like components and ring-shaped soldering pads with through-hole-via connecting to power/ground planes are designed on the package substrate. A test sample of the hybrid PCPL is fabricated and measured. A wide stopband from 3.2 to 9.5 GHz is achieved with 30 dB of noise suppression in average. This enhanced stopband is consistent with the prediction both by gap map synthesis and full-wave simulation. The hybrid PCPL is applied in a package substrate with voltage-controlled oscillator (VCO) circuit and excellent noise suppression performance is demonstrated.
{"title":"Design and Implementation of a Novel Hybrid Photonic Crystal Power/Ground Layer for Broadband Power Noise Suppression","authors":"Guanqun Wu, Yi-Che Chen, Tzong-Lin Wu","doi":"10.1109/TADVP.2009.2034334","DOIUrl":"https://doi.org/10.1109/TADVP.2009.2034334","url":null,"abstract":"By embedding periodically high-K rods in the package substrate, a hybrid photonic crystal power/ground layers (PCPL) is proposed with stopband enhancement for power/ground noise suppression. The hybrid PCPL consists of two different lattice structures, which have the same pitch but different radii of the high-K rods. Using the gap map of the photonic crystal lattice, the enhanced stopband can be synthesized by designing these two different lattices with compensated stopband. An implementation approach, which is compatible to the standard fabrication process of package or printed circuit board (PCB), is also proposed in this paper. The high-K rods are considered as surface mount technology (SMT)-like components and ring-shaped soldering pads with through-hole-via connecting to power/ground planes are designed on the package substrate. A test sample of the hybrid PCPL is fabricated and measured. A wide stopband from 3.2 to 9.5 GHz is achieved with 30 dB of noise suppression in average. This enhanced stopband is consistent with the prediction both by gap map synthesis and full-wave simulation. The hybrid PCPL is applied in a package substrate with voltage-controlled oscillator (VCO) circuit and excellent noise suppression performance is demonstrated.","PeriodicalId":55015,"journal":{"name":"IEEE Transactions on Advanced Packaging","volume":"33 1","pages":"206-211"},"PeriodicalIF":0.0,"publicationDate":"2010-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TADVP.2009.2034334","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62395052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-02-01DOI: 10.1109/TADVP.2009.2014353
Feng Sheng, D. Jiao
In this paper, fast algorithms are proposed for an efficient reduction of a 3-D layered system matrix to a 2-D layered one in the framework of the frequency-domain layered finite element method. These algorithms include: 1) an effective preconditioner P that can converge the iterative solution of the volume-unknown-based matrix equation in a few iterations; 2) a fast direct computation of P -1 in linear complexity in both CPU run time and memory consumption; and 3) a fast evaluation of P -1 b in linear complexity, with b being an arbitrary vector. With these fast algorithms, the volume-unknown-based matrix equation is solved in linear complexity with a small constant in front of the number of unknowns, and hence significantly reducing the complexity of the 3-D to 2-D reduction. The algorithms are rigorous without making any approximation. They apply to any arbitrarily-shaped multilayer structure. Numerical and experimental results are shown to demonstrate the accuracy and efficiency of the proposed algorithms.
{"title":"Fast Reduction Algorithms in the Frequency-Domain Layered Finite Element Method for the Electromagnetic Analysis of Large-Scale High-Frequency Integrated Circuits","authors":"Feng Sheng, D. Jiao","doi":"10.1109/TADVP.2009.2014353","DOIUrl":"https://doi.org/10.1109/TADVP.2009.2014353","url":null,"abstract":"In this paper, fast algorithms are proposed for an efficient reduction of a 3-D layered system matrix to a 2-D layered one in the framework of the frequency-domain layered finite element method. These algorithms include: 1) an effective preconditioner P that can converge the iterative solution of the volume-unknown-based matrix equation in a few iterations; 2) a fast direct computation of P -1 in linear complexity in both CPU run time and memory consumption; and 3) a fast evaluation of P -1 b in linear complexity, with b being an arbitrary vector. With these fast algorithms, the volume-unknown-based matrix equation is solved in linear complexity with a small constant in front of the number of unknowns, and hence significantly reducing the complexity of the 3-D to 2-D reduction. The algorithms are rigorous without making any approximation. They apply to any arbitrarily-shaped multilayer structure. Numerical and experimental results are shown to demonstrate the accuracy and efficiency of the proposed algorithms.","PeriodicalId":55015,"journal":{"name":"IEEE Transactions on Advanced Packaging","volume":"33 1","pages":"266-275"},"PeriodicalIF":0.0,"publicationDate":"2010-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TADVP.2009.2014353","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"62388203","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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