Pub Date : 2025-03-06DOI: 10.1109/LES.2025.3567482
Xiqin Tang;Yang Li;Weijia Liu;Delong Shang
In this article, two approximate Radix-4 Booth encoders Approximate Radix-4 Booth Encoder1, 2 (AR4BE1 and AR4BE2) are. proposed to achieve great accuracy-cost tradeoff, and a series of signed approximation multipliers (SAMs) are designed based on a hybrid coding approach, where the most significant bits (MSBs) use exact radix-4 encoder, and the least significant bits (LSBs) use the proposed AR4BE1 and AR4BE2. And a simple error compensation circuit is used to reduce the accuracy loss in partial product array reduction. The proposed SAMs can be reconfigured for different applications with different accuracy-cost tradeoff requirement. We comprehensively evaluate the SAMs with respect to both hardware implementation and error analysis. Compared to the exact multiplier, the highest accuracy multiplier H10M6L0, has 22.8%, 32.1%, and 18.4% reduction in area, power consumption, and delay, respectively. The case study for image edge detection also proves the validity of the proposed SAMs in error-tolerant application.
{"title":"Two Novel Approximate Radix-4 Booth Encoders for Efficient Signed Approximate Booth Multipliers","authors":"Xiqin Tang;Yang Li;Weijia Liu;Delong Shang","doi":"10.1109/LES.2025.3567482","DOIUrl":"https://doi.org/10.1109/LES.2025.3567482","url":null,"abstract":"In this article, two approximate Radix-4 Booth encoders Approximate Radix-4 Booth Encoder1, 2 (AR4BE1 and AR4BE2) are. proposed to achieve great accuracy-cost tradeoff, and a series of signed approximation multipliers (SAMs) are designed based on a hybrid coding approach, where the most significant bits (MSBs) use exact radix-4 encoder, and the least significant bits (LSBs) use the proposed AR4BE1 and AR4BE2. And a simple error compensation circuit is used to reduce the accuracy loss in partial product array reduction. The proposed SAMs can be reconfigured for different applications with different accuracy-cost tradeoff requirement. We comprehensively evaluate the SAMs with respect to both hardware implementation and error analysis. Compared to the exact multiplier, the highest accuracy multiplier H10M6L0, has 22.8%, 32.1%, and 18.4% reduction in area, power consumption, and delay, respectively. The case study for image edge detection also proves the validity of the proposed SAMs in error-tolerant application.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"18 1","pages":"73-76"},"PeriodicalIF":2.0,"publicationDate":"2025-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146162237","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Low vision significantly impacts daily navigation, affecting an estimated 295 million people globally (Bourne et al., 2021). While Head-Mounted Displays (hereafter HMDs) have been used throughout the latest decades to mitigate these limitations, to our knowledge, no low-cost existing system utilizes real-time object detection within an HMD for navigation assistance specifically designed for the visually impaired. This letter presents the development and evaluation of a real-time navigation assistance device with automatic detection and highlighting of visual Points of Interest over the visual field, deployed on a resource-constrained embedded platform. We leverage state-of-the-art YOLO models (v8, v9, and v10), optimized for execution on a Raspberry Pi 5. Using optimized embedded systems inference engines, we investigate the tradeoffs between accuracy, speed, and power consumption. Using a custom-built dataset and publicly available benchmark files, our experimental results demonstrate the feasibility of achieving real-time performance with acceptable accuracy on a low-cost, portable device, enabling practical semantics-aware assistive technology for the visually impaired.
低视力严重影响日常导航，全球约有2.95亿人受到影响（Bourne et al., 2021）。虽然头戴式显示器（以下简称HMD）在过去的几十年里一直在使用，以减轻这些限制，但据我们所知，目前还没有低成本的现有系统在头戴式显示器中利用实时物体检测来帮助视力受损的人进行导航。这封信介绍了一种实时导航辅助设备的开发和评估，该设备具有自动检测和突出显示视野上的视觉兴趣点，部署在资源受限的嵌入式平台上。我们利用最先进的YOLO模型（v8、v9和v10），针对Raspberry Pi 5进行了优化。使用优化的嵌入式系统推理引擎，我们研究了精度、速度和功耗之间的权衡。使用定制的数据集和公开可用的基准文件，我们的实验结果证明了在低成本的便携式设备上以可接受的精度实现实时性能的可行性，从而为视障人士提供实用的语义感知辅助技术。
{"title":"Deep-Learning-Based Visual Aid for Low Vision","authors":"Rodolfo Bonnin;Claudio Delrieux;María Fabiana Piccoli","doi":"10.1109/LES.2025.3548959","DOIUrl":"https://doi.org/10.1109/LES.2025.3548959","url":null,"abstract":"Low vision significantly impacts daily navigation, affecting an estimated 295 million people globally (Bourne et al., 2021). While Head-Mounted Displays (hereafter HMDs) have been used throughout the latest decades to mitigate these limitations, to our knowledge, no low-cost existing system utilizes real-time object detection within an HMD for navigation assistance specifically designed for the visually impaired. This letter presents the development and evaluation of a real-time navigation assistance device with automatic detection and highlighting of visual Points of Interest over the visual field, deployed on a resource-constrained embedded platform. We leverage state-of-the-art YOLO models (v8, v9, and v10), optimized for execution on a Raspberry Pi 5. Using optimized embedded systems inference engines, we investigate the tradeoffs between accuracy, speed, and power consumption. Using a custom-built dataset and publicly available benchmark files, our experimental results demonstrate the feasibility of achieving real-time performance with acceptable accuracy on a low-cost, portable device, enabling practical semantics-aware assistive technology for the visually impaired.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"17 6","pages":"398-401"},"PeriodicalIF":2.0,"publicationDate":"2025-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145778297","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-06DOI: 10.1109/LES.2025.3548895
Abolfazl Rajaiyan;Seyed Mojtaba Atarodi
Key generation in cryptography is very important, as it helps secure digital communication. physically unclonable functions (PUFs) are among the circuits that ensure security at the hardware level by generating unique keys. However, PUFs are often affected by changes in temperature and voltage, which can impact their reliability. Additionally, PUFs are vulnerable to electromagnetic and modeling attacks, making it essential to use circuits that can resist such threats. In this letter, a temperature- and voltage-independent PUF (TVI PUF) is proposed. This circuit uses a novel two-step (pipeline) structure. This circuit incorporates pipelining and challenge obfuscation. This leads to enhanced reliability and improved resistance to modeling attacks. The proposed circuit is implemented on a Xilinx Zynq7 FPGA and tested under various conditions. The proposed circuit is resilient against both modeling and electromagnetic attacks and operates reliably across a temperature range of $- 40~^{circ }$ C to $150~^{circ }$ C. Measurement results show that the proposed circuit achieves a bit error rate (BER) of $1.21times 10{^{-}11 }$ , uniformity of 50.11%, and uniqueness of 49.89%. The proposed TVI PUF shows a vulnerability rate of 50.47% to modeling attacks. The high reliability (approximately zero BER) and low vulnerability to modeling attacks highlight the advantages of this circuit.
{"title":"TVI PUF: A Temperature- and Voltage-Independent PUF With High Resistance to Modeling Attacks","authors":"Abolfazl Rajaiyan;Seyed Mojtaba Atarodi","doi":"10.1109/LES.2025.3548895","DOIUrl":"https://doi.org/10.1109/LES.2025.3548895","url":null,"abstract":"Key generation in cryptography is very important, as it helps secure digital communication. physically unclonable functions (PUFs) are among the circuits that ensure security at the hardware level by generating unique keys. However, PUFs are often affected by changes in temperature and voltage, which can impact their reliability. Additionally, PUFs are vulnerable to electromagnetic and modeling attacks, making it essential to use circuits that can resist such threats. In this letter, a temperature- and voltage-independent PUF (TVI PUF) is proposed. This circuit uses a novel two-step (pipeline) structure. This circuit incorporates pipelining and challenge obfuscation. This leads to enhanced reliability and improved resistance to modeling attacks. The proposed circuit is implemented on a Xilinx Zynq7 FPGA and tested under various conditions. The proposed circuit is resilient against both modeling and electromagnetic attacks and operates reliably across a temperature range of <inline-formula> <tex-math>$- 40~^{circ }$ </tex-math></inline-formula>C to <inline-formula> <tex-math>$150~^{circ }$ </tex-math></inline-formula>C. Measurement results show that the proposed circuit achieves a bit error rate (BER) of <inline-formula> <tex-math>$1.21times 10{^{-}11 }$ </tex-math></inline-formula>, uniformity of 50.11%, and uniqueness of 49.89%. The proposed TVI PUF shows a vulnerability rate of 50.47% to modeling attacks. The high reliability (approximately zero BER) and low vulnerability to modeling attacks highlight the advantages of this circuit.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"17 6","pages":"443-446"},"PeriodicalIF":2.0,"publicationDate":"2025-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145778205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-05DOI: 10.1109/LES.2025.3566669
Hao Sun;Xiaoran Hao;Mande Xie
With the rapid proliferation of machine learning inference (MLI) tasks on Internet of Things (IoT) devices, the demand for enhanced memory system performance in these devices has become increasingly critical. This letter proposes a hybrid storage class memory (HSCM) optimization method to improve the efficiency of MLI on IoT devices. We conducted an in-depth analysis of memory access characteristics in MLI scenarios and found that the diversity and frequency of data access patterns significantly affect storage performance. Based on these characteristics, we propose a hybrid memory migration management strategy using the Markov model, which can dynamically adjust data migration between different storage levels to adapt to changing access patterns. We designed an acceleration method based on HSCM that improves inference speed and energy efficiency by optimizing data access paths and reducing latency. Experiments demonstrate that the proposed method outperforms existing memory systems, providing a new solution for efficient MLI on embedded IoT devices.
{"title":"Hybrid Storage Class Memory-Enhanced Machine Learning Inference in Embedded Edge Devices","authors":"Hao Sun;Xiaoran Hao;Mande Xie","doi":"10.1109/LES.2025.3566669","DOIUrl":"https://doi.org/10.1109/LES.2025.3566669","url":null,"abstract":"With the rapid proliferation of machine learning inference (MLI) tasks on Internet of Things (IoT) devices, the demand for enhanced memory system performance in these devices has become increasingly critical. This letter proposes a hybrid storage class memory (HSCM) optimization method to improve the efficiency of MLI on IoT devices. We conducted an in-depth analysis of memory access characteristics in MLI scenarios and found that the diversity and frequency of data access patterns significantly affect storage performance. Based on these characteristics, we propose a hybrid memory migration management strategy using the Markov model, which can dynamically adjust data migration between different storage levels to adapt to changing access patterns. We designed an acceleration method based on HSCM that improves inference speed and energy efficiency by optimizing data access paths and reducing latency. Experiments demonstrate that the proposed method outperforms existing memory systems, providing a new solution for efficient MLI on embedded IoT devices.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"18 1","pages":"15-18"},"PeriodicalIF":2.0,"publicationDate":"2025-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146162180","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-05DOI: 10.1109/LES.2025.3566674
Anirban Sengupta;Nabendu Bhui;Aditya Anshul
The threats of hardware intellectual property (IP) piracy and fraud IP ownership claim pose a grave concern for the hardware security community. This letter proposes a novel high-level synthesis (HLS) methodology that exploits IP vendor’s deoxyribonucleic acid (DNA) signature to form a forensic hardware watermark for covertly embedding into allocation phase of the design synthesis process. The forensic watermark signature is generated by extracting unique DNA components, such as microsatellites and fragments. The proposed approach, when compared with the existing HLS watermarking techniques, revealed enhancement in security in terms of probability of coincidence and tamper tolerance, at nominal design overhead.
{"title":"High-Level Synthesis-Based Forensic Watermarking of Hardware IPs Using IP Vendor’s DNA Signature","authors":"Anirban Sengupta;Nabendu Bhui;Aditya Anshul","doi":"10.1109/LES.2025.3566674","DOIUrl":"https://doi.org/10.1109/LES.2025.3566674","url":null,"abstract":"The threats of hardware intellectual property (IP) piracy and fraud IP ownership claim pose a grave concern for the hardware security community. This letter proposes a novel high-level synthesis (HLS) methodology that exploits IP vendor’s deoxyribonucleic acid (DNA) signature to form a forensic hardware watermark for covertly embedding into allocation phase of the design synthesis process. The forensic watermark signature is generated by extracting unique DNA components, such as microsatellites and fragments. The proposed approach, when compared with the existing HLS watermarking techniques, revealed enhancement in security in terms of probability of coincidence and tamper tolerance, at nominal design overhead.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"18 1","pages":"19-22"},"PeriodicalIF":2.0,"publicationDate":"2025-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146162238","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-05DOI: 10.1109/LES.2025.3566818
Manav Rathod;Anakhi Hazarika;Ayush Agrawal;Neeraj Kumar;Arunachaleashwer S.
Edge devices require low-power and efficient hardware to support data-intensive computations in real-time applications. Traditional multipliers are computationally demanding and consume considerable power, however, approximate circuits are used in applications requiring low-power consumption and high-performance. The approximate multiplier is the key arithmetic function in many error-tolerant applications, such as signal processing, image processing, etc. This letter presents a power-efficient approximate multiplier design tailored for error-resilient applications on edge devices. The proposed design employs an approximate 4:2 compressor based on input reordering. Input reordering is used to reduce the number of combinations which leads to low power consumption. The experimental analysis demonstrates the efficacy of the proposed approximate multiplier that achieves power and area savings. The results highlight the viability of DNN workloads in resource-constrained environments and the potential for extending edge device lifespans without compromising the accuracy required for real-time, error-tolerant tasks.
{"title":"Power Efficient Multiplier Design for Error Resilient Edge Applications","authors":"Manav Rathod;Anakhi Hazarika;Ayush Agrawal;Neeraj Kumar;Arunachaleashwer S.","doi":"10.1109/LES.2025.3566818","DOIUrl":"https://doi.org/10.1109/LES.2025.3566818","url":null,"abstract":"Edge devices require low-power and efficient hardware to support data-intensive computations in real-time applications. Traditional multipliers are computationally demanding and consume considerable power, however, approximate circuits are used in applications requiring low-power consumption and high-performance. The approximate multiplier is the key arithmetic function in many error-tolerant applications, such as signal processing, image processing, etc. This letter presents a power-efficient approximate multiplier design tailored for error-resilient applications on edge devices. The proposed design employs an approximate 4:2 compressor based on input reordering. Input reordering is used to reduce the number of combinations which leads to low power consumption. The experimental analysis demonstrates the efficacy of the proposed approximate multiplier that achieves power and area savings. The results highlight the viability of DNN workloads in resource-constrained environments and the potential for extending edge device lifespans without compromising the accuracy required for real-time, error-tolerant tasks.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"18 1","pages":"23-26"},"PeriodicalIF":2.0,"publicationDate":"2025-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146223562","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-05DOI: 10.1109/LES.2025.3567025
Marcelo V. C. Aragão;Tiago de M. Pereira;Felipe A. P. de Figueiredo;Samuel B. Mafra
The rapid growth of IoT devices demands scalable and efficient threat detection solutions. This article introduces a sample-based, multistage machine learning (ML) pipeline for IoT threat detection using the CICIoT2023 dataset, integrating feature selection, data balancing, and hyperparameter optimization to improve detection accuracy while reducing the computational overhead associated with training. We evaluate LightGBM, XGBoost, and XGBoostRF across binary, multiclass, and fine-grained tasks, showing that XGBoost with 10% sampling achieves the best tradeoff between accuracy and efficiency. Compared to prior methods, our approach eliminates GPU dependence, maintains low latency, and preserves state-of-the-art performance while enabling scalable training for high generalization capacity. Additionally, we provide model selection guidelines based on dataset complexity and computational constraints. The results show that training with a sample-based approach enables effective threat detection on large datasets, producing models that generalize well to diverse IoT attack scenarios, thus ensuring practical applicability in real-world deployments.
{"title":"A Sample-Based, Multistage Machine Learning Pipeline for Scalable IoT Threat Detection","authors":"Marcelo V. C. Aragão;Tiago de M. Pereira;Felipe A. P. de Figueiredo;Samuel B. Mafra","doi":"10.1109/LES.2025.3567025","DOIUrl":"https://doi.org/10.1109/LES.2025.3567025","url":null,"abstract":"The rapid growth of IoT devices demands scalable and efficient threat detection solutions. This article introduces a sample-based, multistage machine learning (ML) pipeline for IoT threat detection using the CICIoT2023 dataset, integrating feature selection, data balancing, and hyperparameter optimization to improve detection accuracy while reducing the computational overhead associated with training. We evaluate LightGBM, XGBoost, and XGBoostRF across binary, multiclass, and fine-grained tasks, showing that XGBoost with 10% sampling achieves the best tradeoff between accuracy and efficiency. Compared to prior methods, our approach eliminates GPU dependence, maintains low latency, and preserves state-of-the-art performance while enabling scalable training for high generalization capacity. Additionally, we provide model selection guidelines based on dataset complexity and computational constraints. The results show that training with a sample-based approach enables effective threat detection on large datasets, producing models that generalize well to diverse IoT attack scenarios, thus ensuring practical applicability in real-world deployments.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"18 1","pages":"36-39"},"PeriodicalIF":2.0,"publicationDate":"2025-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10985870","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146162231","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-04DOI: 10.1109/LES.2025.3547961
Nima Eslami;Mohammad Hossein Moaiyeri
Cardiovascular diseases (CVDs) necessitate continuous heart sound monitoring to distinguish normal from abnormal signals for early diagnosis. While wearable devices using phonocardiogram (PCG) technology show promise, energy constraints limit their effectiveness. This letter presents a binary PCG classification method utilizing a ternary neural network with nonvolatile ternary logic gates. Based on negative capacitance carbon nanotube field-effect transistor technology, the design incorporates ternary full adders and multipliers for efficient MAC operations, reducing transistor count and enhancing energy efficiency. Results demonstrate significant improvements in energy dissipation, extending device lifespan and enhancing long-term disease detection capabilities.
{"title":"Efficient Training and Energy Saving Using Ternary Hardware Acceleration for PCG Classification","authors":"Nima Eslami;Mohammad Hossein Moaiyeri","doi":"10.1109/LES.2025.3547961","DOIUrl":"https://doi.org/10.1109/LES.2025.3547961","url":null,"abstract":"Cardiovascular diseases (CVDs) necessitate continuous heart sound monitoring to distinguish normal from abnormal signals for early diagnosis. While wearable devices using phonocardiogram (PCG) technology show promise, energy constraints limit their effectiveness. This letter presents a binary PCG classification method utilizing a ternary neural network with nonvolatile ternary logic gates. Based on negative capacitance carbon nanotube field-effect transistor technology, the design incorporates ternary full adders and multipliers for efficient MAC operations, reducing transistor count and enhancing energy efficiency. Results demonstrate significant improvements in energy dissipation, extending device lifespan and enhancing long-term disease detection capabilities.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"17 6","pages":"447-450"},"PeriodicalIF":2.0,"publicationDate":"2025-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145778298","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Liquid Crystal on Silicon (LCoS) technology utilizing phase-only modulation offers a wide range of applications. Efficient management of high-speed data flow and complex logic control is crucial for driving LCoS chips. This work presents an FPGA-based control system based for a $2460times 1620$ , 120 Hz LCoS phase modulator. We propose a bandwidth efficient data mapping method by multiplexing the HDMI transmission protocol. The system supports full-resolution display and facilitates real-time projection. Compared to previous implementation schemes, the proposed system achieves a lower power consumption per pixel, as low as 5.70 nW. Additionally, the driven LCoS chip achieves an improved flipping rate of 1.22 kHz. This work demonstrates the effectiveness and feasibility of the proposed system for LCoS applications, providing a robust platform that can be adapted to various implementations.
{"title":"A Control System for Real-Time Driving of LCoS SLM Based on FPGA","authors":"Yuwei Jiang;Yingqi Feng;Tao Ren;Wenyu Yang;Li Tian;Hui Wang;Yongxin Zhu;Zunkai Huang","doi":"10.1109/LES.2025.3547021","DOIUrl":"https://doi.org/10.1109/LES.2025.3547021","url":null,"abstract":"Liquid Crystal on Silicon (LCoS) technology utilizing phase-only modulation offers a wide range of applications. Efficient management of high-speed data flow and complex logic control is crucial for driving LCoS chips. This work presents an FPGA-based control system based for a <inline-formula> <tex-math>$2460times 1620$ </tex-math></inline-formula>, 120 Hz LCoS phase modulator. We propose a bandwidth efficient data mapping method by multiplexing the HDMI transmission protocol. The system supports full-resolution display and facilitates real-time projection. Compared to previous implementation schemes, the proposed system achieves a lower power consumption per pixel, as low as 5.70 nW. Additionally, the driven LCoS chip achieves an improved flipping rate of 1.22 kHz. This work demonstrates the effectiveness and feasibility of the proposed system for LCoS applications, providing a robust platform that can be adapted to various implementations.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"17 6","pages":"431-434"},"PeriodicalIF":2.0,"publicationDate":"2025-03-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145778299","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this letter, a high-speed Reed-Solomon erasure code (RS-EC) decoder circuit is proposed for accelerating the data reconstruction in storage. By utilizing a check matrix instead of a regular Cauchy matrix for encoding the original data, the size of the matrix for decoding the damaged data can be reduced significantly. Moreover, in order to accelerate the matrix inversion related to the RS-EC decoder, the large matrix is partitioned into several small matrices and these small matrices execute the inversion operations individually. Subsequently, an equation method instead of the Gaussian elimination method is proposed for further speeding up the inversions of the small matrices. Eventually, a novel algorithm is proposed for reducing the overall data stream of the RS-EC decoder. The results show that the proposed RS (14, 10) decoder is able to achieve a 6800 MBps throughput, under the synthesis of TSMC 130 nm process design kits (PDK). The corresponding data stream of the decoder is reduced to 55% if only one data block is required to reconstruct.
{"title":"A High-Speed ASIC Design of Reed-Solomon Erasure Code (RS-EC) Decoders for Fast Data Recovery in Storage","authors":"Jiaqi Wang;Hongyang Zhao;Jiafeng Cheng;Wenrui Liu;Nengyuan Sun;Heng Sha;Zhiyuan Pan;Ming Jin;Jinghe Wang;Zhaoyi Niu;Jianghong Li;Kai Shi;Jiawei Zhang;Linhan Wang;Kangning Song;Ke Li;Selcuk Kose;Weize Yu","doi":"10.1109/LES.2025.3566686","DOIUrl":"https://doi.org/10.1109/LES.2025.3566686","url":null,"abstract":"In this letter, a high-speed Reed-Solomon erasure code (RS-EC) decoder circuit is proposed for accelerating the data reconstruction in storage. By utilizing a check matrix instead of a regular Cauchy matrix for encoding the original data, the size of the matrix for decoding the damaged data can be reduced significantly. Moreover, in order to accelerate the matrix inversion related to the RS-EC decoder, the large matrix is partitioned into several small matrices and these small matrices execute the inversion operations individually. Subsequently, an equation method instead of the Gaussian elimination method is proposed for further speeding up the inversions of the small matrices. Eventually, a novel algorithm is proposed for reducing the overall data stream of the RS-EC decoder. The results show that the proposed RS (14, 10) decoder is able to achieve a 6800 MBps throughput, under the synthesis of TSMC 130 nm process design kits (PDK). The corresponding data stream of the decoder is reduced to 55% if only one data block is required to reconstruct.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"18 1","pages":"11-14"},"PeriodicalIF":2.0,"publicationDate":"2025-03-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146162213","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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