Pub Date : 2024-06-19DOI: 10.1109/LES.2024.3416820
Ana Fernandes;Luís Crespo;Nuno Neves;Pedro Tomás;Nuno Roma;Gabriel Falcao
Data streaming and data-flow computing paradigms have been on the rise, aiming to improve the performance of general-purpose processors. However, providing support for data streaming typically requires the definition of new instruction set architecture (ISA) extensions, which must be thoroughly validated before being implemented in hardware. This step is usually carried out using instruction set simulators (ISSs), to which the necessary streaming support must be added. Accordingly, this work proposes a new validation simulator for the recently presented stream-based RISC-V ISA unlimited vector extension (UVE). The proposed tool is based on Spike, the golden reference instruction set simulator ISS for RISC-V extensions. It is capable of processing a wide range of memory access patterns and provides the necessary mechanisms to validate the target extension, as well as to evaluate the resulting instruction reduction gains.
{"title":"Functional Validation of the RISC-V Unlimited Vector Extension","authors":"Ana Fernandes;Luís Crespo;Nuno Neves;Pedro Tomás;Nuno Roma;Gabriel Falcao","doi":"10.1109/LES.2024.3416820","DOIUrl":"10.1109/LES.2024.3416820","url":null,"abstract":"Data streaming and data-flow computing paradigms have been on the rise, aiming to improve the performance of general-purpose processors. However, providing support for data streaming typically requires the definition of new instruction set architecture (ISA) extensions, which must be thoroughly validated before being implemented in hardware. This step is usually carried out using instruction set simulators (ISSs), to which the necessary streaming support must be added. Accordingly, this work proposes a new validation simulator for the recently presented stream-based RISC-V ISA unlimited vector extension (UVE). The proposed tool is based on Spike, the golden reference instruction set simulator ISS for RISC-V extensions. It is capable of processing a wide range of memory access patterns and provides the necessary mechanisms to validate the target extension, as well as to evaluate the resulting instruction reduction gains.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"17 1","pages":"2-5"},"PeriodicalIF":1.7,"publicationDate":"2024-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141937440","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Hardware Trojan insertion in high-level synthesis (HLS) generated intellectual property (IP) designs can pose strong security concern for the designers. Backdoor hardware Trojans can be inserted in the HLS design flow to compromise the produced register transfer level (RTL) IP design. This letter presents a novel malevolent HLS (M-HLS) framework introducing the possibility of two different hardware Trojan insertion [i.e., performance degradation hardware Trojan (PD-HT) and Denial of Service hardware Trojan (DoS-HT)] in multiplexer (mux)-based interconnect stage of HLS generated watermarked IP design. The proposed framework is validated on the watermarked MESA Horner Bezier’s IP, which indicates strong performance degradation and DoS achievable by an attacker at minimal area and power overhead.
{"title":"M-HLS: Malevolent High-Level Synthesis for Watermarked Hardware IPs","authors":"Anirban Sengupta;Aditya Anshul;Vishal Chourasia;Nitish Kumar","doi":"10.1109/LES.2024.3416422","DOIUrl":"10.1109/LES.2024.3416422","url":null,"abstract":"Hardware Trojan insertion in high-level synthesis (HLS) generated intellectual property (IP) designs can pose strong security concern for the designers. Backdoor hardware Trojans can be inserted in the HLS design flow to compromise the produced register transfer level (RTL) IP design. This letter presents a novel malevolent HLS (M-HLS) framework introducing the possibility of two different hardware Trojan insertion [i.e., performance degradation hardware Trojan (PD-HT) and Denial of Service hardware Trojan (DoS-HT)] in multiplexer (mux)-based interconnect stage of HLS generated watermarked IP design. The proposed framework is validated on the watermarked MESA Horner Bezier’s IP, which indicates strong performance degradation and DoS achievable by an attacker at minimal area and power overhead.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"16 4","pages":"497-500"},"PeriodicalIF":1.7,"publicationDate":"2024-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141937617","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-06-18DOI: 10.1109/LES.2024.3415651
Jose Alejandro Galaviz-Aguilar;Cesar Vargas-Rosales;Francisco Falcone
The lock-in amplifier (LIA) instruments are designed to provide signal conditioning for precision measurement systems to extract signals from extremely noisy environments. The digital LIAs design often requires a verification process to ensure hardware performance. Thus, hardware description language (HDL) with functional verification strategies offers a powerful tool to provide an field-programmable gate array (FPGA) integrated solution. In this letter, we propose a methodology of design and verification of all-digital LIA and an additive white Gaussian noise (AWGN) module able to measure extremely lower levels of signal-to-noise ratio (SNR) of $approx $ ${10}^{-{15}}$ or down to −37 dB while a wide reserve of spurious-free dynamic range (SFDR) up to 90 dB on FPGA is ensured. To this end, the designed and implemented FPGA framework for quick, accurate, and comprehensive characterization of a given digital LIA is used to leverage the capabilities of the design under controllable AWGN noise patterns stimulus.
锁相放大器（LIA）仪器的设计目的是为精密测量系统提供信号调节，以便从极度嘈杂的环境中提取信号。数字 LIA 设计通常需要验证过程，以确保硬件性能。因此，具有功能验证策略的硬件描述语言（HDL）为提供现场可编程门阵列（FPGA）集成解决方案提供了强有力的工具。在这封信中，我们提出了一种全数字 LIA 和加性白高斯噪声（AWGN）模块的设计和验证方法，该模块能够测量 ${10}^{-{15}}$ 或低至 -37 dB 的极低水平信噪比（SNR），同时确保 FPGA 具有高达 90 dB 的宽储备无杂散动态范围（SFDR）。为此，设计并实现了 FPGA 框架，用于快速、准确、全面地鉴定给定的数字 LIA，以充分利用设计在可控 AWGN 噪声模式刺激下的能力。
{"title":"Reliable Methodology to FPGA Design Verification and Noise Analysis for Digital Lock-In Amplifiers","authors":"Jose Alejandro Galaviz-Aguilar;Cesar Vargas-Rosales;Francisco Falcone","doi":"10.1109/LES.2024.3415651","DOIUrl":"10.1109/LES.2024.3415651","url":null,"abstract":"The lock-in amplifier (LIA) instruments are designed to provide signal conditioning for precision measurement systems to extract signals from extremely noisy environments. The digital LIAs design often requires a verification process to ensure hardware performance. Thus, hardware description language (HDL) with functional verification strategies offers a powerful tool to provide an field-programmable gate array (FPGA) integrated solution. In this letter, we propose a methodology of design and verification of all-digital LIA and an additive white Gaussian noise (AWGN) module able to measure extremely lower levels of signal-to-noise ratio (SNR) of \u0000<inline-formula> <tex-math>$approx $ </tex-math></inline-formula>\u0000 \u0000<inline-formula> <tex-math>${10}^{-{15}}$ </tex-math></inline-formula>\u0000 or down to −37 dB while a wide reserve of spurious-free dynamic range (SFDR) up to 90 dB on FPGA is ensured. To this end, the designed and implemented FPGA framework for quick, accurate, and comprehensive characterization of a given digital LIA is used to leverage the capabilities of the design under controllable AWGN noise patterns stimulus.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"16 3","pages":"307-310"},"PeriodicalIF":1.7,"publicationDate":"2024-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141937441","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In an era dominated by embedded systems, where efficient memory management is crucial, this study delves into the effectiveness of VCMalloc, a novel memory allocator that ensures virtual contiguity, on the Raspberry Pi 4 platform. Through a series of meticulously designed experiments, we compared the performance of VCMalloc with that of the conventional Malloc allocator. Our comprehensive findings reveal VCMalloc’s notable superiority across various performance metrics, positioning it as a highly promising solution for memory management in embedded systems, especially those leveraging virtual memory and memory management units (MMUs).
{"title":"Virtually Contiguous Memory Allocation in Embedded Systems: A Performance Analysis","authors":"Yacine Hadjadj;Chakib Mustapha Anouar Zouaoui;Nasreddine Taleb","doi":"10.1109/LES.2024.3416192","DOIUrl":"10.1109/LES.2024.3416192","url":null,"abstract":"In an era dominated by embedded systems, where efficient memory management is crucial, this study delves into the effectiveness of VCMalloc, a novel memory allocator that ensures virtual contiguity, on the Raspberry Pi 4 platform. Through a series of meticulously designed experiments, we compared the performance of VCMalloc with that of the conventional Malloc allocator. Our comprehensive findings reveal VCMalloc’s notable superiority across various performance metrics, positioning it as a highly promising solution for memory management in embedded systems, especially those leveraging virtual memory and memory management units (MMUs).","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"17 1","pages":"26-29"},"PeriodicalIF":1.7,"publicationDate":"2024-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141937442","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-06-18DOI: 10.1109/LES.2024.3416401
Zhanxian Liu;Chufan Liu;Haijun Zhang;Ling Zhao
This letter presents an optimized Viterbi decoder of convolutional codes on graphics processing unit (GPU) for software defined radio (SDR) platforms. Before the forward process, channel messages are interleaved with coalesced global memory access and the interleaved messages are represented with 4 bits to improve shared memory efficiency. Moreover, we optimize on-chip memory allocations of the forward process to accelerate instruction execution. Excluding the data transfer latency between host and device, the proposed Viterbi decoder achieves 22.2 and 76.5-Gb/s throughput on Tesla V100 and RTX4090, respectively. Compared with related works, the throughput speedups achieved by the proposed decoder are from $2.06times $ to $2.93times $ .
{"title":"76.5-Gb/s Viterbi Decoder for Convolutional Codes on GPU","authors":"Zhanxian Liu;Chufan Liu;Haijun Zhang;Ling Zhao","doi":"10.1109/LES.2024.3416401","DOIUrl":"10.1109/LES.2024.3416401","url":null,"abstract":"This letter presents an optimized Viterbi decoder of convolutional codes on graphics processing unit (GPU) for software defined radio (SDR) platforms. Before the forward process, channel messages are interleaved with coalesced global memory access and the interleaved messages are represented with 4 bits to improve shared memory efficiency. Moreover, we optimize on-chip memory allocations of the forward process to accelerate instruction execution. Excluding the data transfer latency between host and device, the proposed Viterbi decoder achieves 22.2 and 76.5-Gb/s throughput on Tesla V100 and RTX4090, respectively. Compared with related works, the throughput speedups achieved by the proposed decoder are from <inline-formula> <tex-math>$2.06times $ </tex-math></inline-formula> to <inline-formula> <tex-math>$2.93times $ </tex-math></inline-formula>.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"17 1","pages":"22-25"},"PeriodicalIF":1.7,"publicationDate":"2024-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141937443","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We have developed a low-cost, high-accuracy, and energy-efficient wearable tag sensor for apnea detection. The sensor can detect different types of breathing problems by monitoring the small movements of the chest wall compartments during each respiration cycle. This tag sensor sends also apnea events, digital respiration rate, and patient posture data using an ultra high radio frequency identification (UHF RFID) reader. The reader is based on the recent AS3993 chip connected to a Raspberry Pi 4 controller, which acts as a local server and is connected to the cloud to share acquired data with the treating doctor. A sleep disorder detection and classification with several positions using a long short-term memory (LSTM) network algorithm is implemented in real-time on the embedded arm microcontroller STM32F407. The proposed apnea detection method exhibits low error, enabling it to meet clinical requirements. The accuracy of apnea events and position detection were triggered in over 93% of cases. We have also evaluated six different classification techniques optimized by considering the proposed feature extraction and regularization of classifier parameters.
{"title":"Wireless Tag Sensor Network for Apnea Detection and Posture Recognition Using LSTM","authors":"Rafik Saddaoui;Massine Gana;Hamid Hamiche;Mourad Laghrouche","doi":"10.1109/LES.2024.3410024","DOIUrl":"10.1109/LES.2024.3410024","url":null,"abstract":"We have developed a low-cost, high-accuracy, and energy-efficient wearable tag sensor for apnea detection. The sensor can detect different types of breathing problems by monitoring the small movements of the chest wall compartments during each respiration cycle. This tag sensor sends also apnea events, digital respiration rate, and patient posture data using an ultra high radio frequency identification (UHF RFID) reader. The reader is based on the recent AS3993 chip connected to a Raspberry Pi 4 controller, which acts as a local server and is connected to the cloud to share acquired data with the treating doctor. A sleep disorder detection and classification with several positions using a long short-term memory (LSTM) network algorithm is implemented in real-time on the embedded arm microcontroller STM32F407. The proposed apnea detection method exhibits low error, enabling it to meet clinical requirements. The accuracy of apnea events and position detection were triggered in over 93% of cases. We have also evaluated six different classification techniques optimized by considering the proposed feature extraction and regularization of classifier parameters.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"16 4","pages":"469-472"},"PeriodicalIF":1.7,"publicationDate":"2024-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141937444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-06-06DOI: 10.1109/LES.2024.3410516
Malik Imran;Safiullah Khan;Ayesha Khalid;Ciara Rafferty;Yasir Ali Shah;Samuel Pagliarini;Muhammad Rashid;Máire O’Neill
Unifying the forward and inverse operations of the number theoretic transform (NTT) into a single hardware module is a common practice when designing polynomial coefficient multiplier accelerators as used in the post-quantum cryptographic algorithms. This letter experimentally evaluates that this design unification is not always advantageous. In this context, we present three NTT hardware architectures: 1) a forward NTT (FNTT) architecture; 2) an inverse NTT (INTT) architecture; and 3) a unified NTT (UNTT) architecture for computing the FNTT and INTT computations on a single design. We benchmark our throughput/area and energy/area evaluations on Xilinx Virtex-7 field-programmable gate array (FPGA) and 28-nm application-specific integrated circuit (ASIC) platforms. The standalone FNTT and INTT designs, on average on FPGA, exhibit $4.66times $ and $3.75times $ higher throughput/area and energy/area values, respectively, than the UNTT design. Similarly, the individual FNTT and INTT designs, on average on ASIC, achieve $1.25times $ and $1.09times $ higher throughput/area and energy/area values, respectively, compared to the UNTT design.
{"title":"Evaluating NTT/INTT Implementation Styles for Post-Quantum Cryptography","authors":"Malik Imran;Safiullah Khan;Ayesha Khalid;Ciara Rafferty;Yasir Ali Shah;Samuel Pagliarini;Muhammad Rashid;Máire O’Neill","doi":"10.1109/LES.2024.3410516","DOIUrl":"10.1109/LES.2024.3410516","url":null,"abstract":"Unifying the forward and inverse operations of the number theoretic transform (NTT) into a single hardware module is a common practice when designing polynomial coefficient multiplier accelerators as used in the post-quantum cryptographic algorithms. This letter experimentally evaluates that this design unification is not always advantageous. In this context, we present three NTT hardware architectures: 1) a forward NTT (FNTT) architecture; 2) an inverse NTT (INTT) architecture; and 3) a unified NTT (UNTT) architecture for computing the FNTT and INTT computations on a single design. We benchmark our throughput/area and energy/area evaluations on Xilinx Virtex-7 field-programmable gate array (FPGA) and 28-nm application-specific integrated circuit (ASIC) platforms. The standalone FNTT and INTT designs, on average on FPGA, exhibit \u0000<inline-formula> <tex-math>$4.66times $ </tex-math></inline-formula>\u0000 and \u0000<inline-formula> <tex-math>$3.75times $ </tex-math></inline-formula>\u0000 higher throughput/area and energy/area values, respectively, than the UNTT design. Similarly, the individual FNTT and INTT designs, on average on ASIC, achieve \u0000<inline-formula> <tex-math>$1.25times $ </tex-math></inline-formula>\u0000 and \u0000<inline-formula> <tex-math>$1.09times $ </tex-math></inline-formula>\u0000 higher throughput/area and energy/area values, respectively, compared to the UNTT design.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"16 4","pages":"485-488"},"PeriodicalIF":1.7,"publicationDate":"2024-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141937516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-06-06DOI: 10.1109/LES.2024.3410892
Christos Sad;Dimosthenis Masouros;Kostas Siozios
The rise of edge computing, characterized by swarms of edge devices, marks a significant shift in cloud-edge computing landscapes, moving data processing closer to the source of data generation. However, this paradigm introduces complexities in orchestration, as traditional centralized methods become inadequate for effectively managing distributed, dynamic edge environments. In this letter, we introduce FEARLESS, a distributed orchestration framework tailored for swarms of edge devices. FEARLESS employs a vertical federated reinforcement learning approach to efficiently orchestrate function invocation requests in serverless swarms. Experimental results demonstrate that FEARLESS significantly reduces the quality-of-service violations of the scheduled tasks by up to 57%, compared to a centralized “least-CPU-utilization” and a “local-execution” approach, while it also achieves approximately up to 20% average total energy reduction.
{"title":"FEARLESS: A Federated Reinforcement Learning Orchestrator for Serverless Edge Swarms","authors":"Christos Sad;Dimosthenis Masouros;Kostas Siozios","doi":"10.1109/LES.2024.3410892","DOIUrl":"10.1109/LES.2024.3410892","url":null,"abstract":"The rise of edge computing, characterized by swarms of edge devices, marks a significant shift in cloud-edge computing landscapes, moving data processing closer to the source of data generation. However, this paradigm introduces complexities in orchestration, as traditional centralized methods become inadequate for effectively managing distributed, dynamic edge environments. In this letter, we introduce FEARLESS, a distributed orchestration framework tailored for swarms of edge devices. FEARLESS employs a vertical federated reinforcement learning approach to efficiently orchestrate function invocation requests in serverless swarms. Experimental results demonstrate that FEARLESS significantly reduces the quality-of-service violations of the scheduled tasks by up to 57%, compared to a centralized “least-CPU-utilization” and a “local-execution” approach, while it also achieves approximately up to 20% average total energy reduction.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"17 1","pages":"34-37"},"PeriodicalIF":1.7,"publicationDate":"2024-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141937517","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The advanced encryption standard (AES) has been widely used to protect digital data in various applications, such as secure IoT communication, files encryption, and pseudorandom number generation. The efficient implementation of AES on parallel architecture, such as graphics processing unit (GPU), has attracted considerable interest over the past decade. These prior studies mainly implemented the AES electronics code book (ECB) and counter (CTR) mode using the table-based approach. In this brief, we set a new speed record of AES-ECB and AES-CTR on GPU based on the proposed bit-sliced implementation techniques. Our implementation achieved 2.6% (ECB) and 9% (CTR) faster than the state-of-the-art table-based implementation on a RTX3080 GPU. Our work evaluated on an embedded GPU (Jetson Orin Nano) can also achieve high throughput at 60 Gb/s, which is 1.9% (ECB) and 7% (CTR) faster than state-of-the-art.
{"title":"Speed Record of AES-CTR and AES-ECB Bit-Sliced Implementation on GPUs","authors":"Wai-Kong Lee;Seog Chung Seo;Hwajeong Seo;Dong Cheon Kim;Seong Oun Hwang","doi":"10.1109/LES.2024.3409725","DOIUrl":"10.1109/LES.2024.3409725","url":null,"abstract":"The advanced encryption standard (AES) has been widely used to protect digital data in various applications, such as secure IoT communication, files encryption, and pseudorandom number generation. The efficient implementation of AES on parallel architecture, such as graphics processing unit (GPU), has attracted considerable interest over the past decade. These prior studies mainly implemented the AES electronics code book (ECB) and counter (CTR) mode using the table-based approach. In this brief, we set a new speed record of AES-ECB and AES-CTR on GPU based on the proposed bit-sliced implementation techniques. Our implementation achieved 2.6% (ECB) and 9% (CTR) faster than the state-of-the-art table-based implementation on a RTX3080 GPU. Our work evaluated on an embedded GPU (Jetson Orin Nano) can also achieve high throughput at 60 Gb/s, which is 1.9% (ECB) and 7% (CTR) faster than state-of-the-art.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"16 4","pages":"481-484"},"PeriodicalIF":1.7,"publicationDate":"2024-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141937518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-04-29DOI: 10.1109/LES.2024.3394446
Juan Pablo Becoña;Marcel Grané;Matías Miguez;Alfredo Arnaud
In this letter, three battery-powered, custom Internet of Things (IoT) sensor nodes for the agribusiness, are presented: first, a Sigfox-based temperature-humidity index (THI) sensor to monitor the impact of heat stress in livestock, then a LoRaWAN version of an estrus detection collar for dairy farms, and finally a NB-IoT low-power A-GPS geolocation device for animals. Detailed power consumption measurements are presented and compared to highlight the benefits of each low-power wide-area network technology for the industry. The measured energy to transmit a single 10Byte payload packet was 90, 20, and 90 mJ for Sigfox, LoRa, and NB-IoT, respectively. With an adequate power management strategy, the nodes could operate up to 10 years in the case of the THI and estrus detector, and >1 yr in the case of the GPS tracker, powered by a single 1900 mA $cdot mathrm {h}~mathrm {LiSOCl}_{2}$ battery.
{"title":"LoRa, Sigfox, and NB-IoT: An Empirical Comparison for IoT LPWAN Technologies in the Agribusiness","authors":"Juan Pablo Becoña;Marcel Grané;Matías Miguez;Alfredo Arnaud","doi":"10.1109/LES.2024.3394446","DOIUrl":"10.1109/LES.2024.3394446","url":null,"abstract":"In this letter, three battery-powered, custom Internet of Things (IoT) sensor nodes for the agribusiness, are presented: first, a Sigfox-based temperature-humidity index (THI) sensor to monitor the impact of heat stress in livestock, then a LoRaWAN version of an estrus detection collar for dairy farms, and finally a NB-IoT low-power A-GPS geolocation device for animals. Detailed power consumption measurements are presented and compared to highlight the benefits of each low-power wide-area network technology for the industry. The measured energy to transmit a single 10Byte payload packet was 90, 20, and 90 mJ for Sigfox, LoRa, and NB-IoT, respectively. With an adequate power management strategy, the nodes could operate up to 10 years in the case of the THI and estrus detector, and >1 yr in the case of the GPS tracker, powered by a single 1900 mA\u0000<inline-formula> <tex-math>$cdot mathrm {h}~mathrm {LiSOCl}_{2}$ </tex-math></inline-formula>\u0000 battery.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"16 3","pages":"283-286"},"PeriodicalIF":1.7,"publicationDate":"2024-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140829762","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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