Pub Date : 2025-01-16DOI: 10.1109/LES.2024.3507646
Wei-Jie Wang;Paul D. Rosero-Montalvo
Analog gauges are still used in industry and manufacturing sectors to gather analog values of one parameter to show the state of the machine or pipe. However, these devices are prone to human error readings and inaccurate samples. Therefore, this work aims to present an edge device with a small camera to digitalize analog samples from the analog gauge by using a novel pointer angle detector approach with an object-detection-vision technique. Yolo V5 nano was the target model and was quantized to be exported to the edge device to make inferences on it. As a main result, the system was tested in two analog gauges, one to present the atmospheric pressure (bar) and the other to show pressure measurement (psi). The system developed has an average ±0.261 bar deviation and a maximum error range of ±0.584 bar on one meter. In the case of another meter, it has an average ±1.438 psi deviation and a maximum error range of ±3.091 psi. The model developed weighs 2 MB.
{"title":"A Gauge Meter Reader Edge Device Based on Computer Vision and Deep Learning","authors":"Wei-Jie Wang;Paul D. Rosero-Montalvo","doi":"10.1109/LES.2024.3507646","DOIUrl":"https://doi.org/10.1109/LES.2024.3507646","url":null,"abstract":"Analog gauges are still used in industry and manufacturing sectors to gather analog values of one parameter to show the state of the machine or pipe. However, these devices are prone to human error readings and inaccurate samples. Therefore, this work aims to present an edge device with a small camera to digitalize analog samples from the analog gauge by using a novel pointer angle detector approach with an object-detection-vision technique. Yolo V5 nano was the target model and was quantized to be exported to the edge device to make inferences on it. As a main result, the system was tested in two analog gauges, one to present the atmospheric pressure (bar) and the other to show pressure measurement (psi). The system developed has an average ±0.261 bar deviation and a maximum error range of ±0.584 bar on one meter. In the case of another meter, it has an average ±1.438 psi deviation and a maximum error range of ±3.091 psi. The model developed weighs 2 MB.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"17 4","pages":"218-221"},"PeriodicalIF":2.0,"publicationDate":"2025-01-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144843063","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-14DOI: 10.1109/LES.2025.3529731
Saeid Gorgin;Ghassem Jaberipur;Jeong-A Lee;Seokjoo Shin;Jungrae Kim
Performance in modern embedded systems, particularly those executing computation-intensive signal/image processing and machine learning algorithms, is critically dependent on the efficiency of multiplication operations. Serial multiplication offers key advantages in these resource-constrained environments, including low-memory usage and minimal interconnect complexity. The most significant digit first (MSDF) serial multiplication scheme further enhances efficiency by enabling early termination and supporting variable precision. It is ideal for embedded applications where power and performance are critical. This letter proposes an auto-selection scheme for MSDF multiplication, where product digits are generated as a byproduct of residual maintenance, leading to speed, cost, and power efficiency improvements. We demonstrate the implementation of serial-serial and serial-parallel multipliers, where the multiplier operand in the latter is fully available throughout the computation. Simulation and synthesis results, compared to the most relevant previous works, show reductions in delay (16% and 20%), area consumption (11% and 23%), and power dissipation (7% and 20%), making our approach well-suited for embedded systems requiring efficient, low-power multiplication hardware.
{"title":"Auto Digit Selection for Most Significant Digit First Multiplication","authors":"Saeid Gorgin;Ghassem Jaberipur;Jeong-A Lee;Seokjoo Shin;Jungrae Kim","doi":"10.1109/LES.2025.3529731","DOIUrl":"https://doi.org/10.1109/LES.2025.3529731","url":null,"abstract":"Performance in modern embedded systems, particularly those executing computation-intensive signal/image processing and machine learning algorithms, is critically dependent on the efficiency of multiplication operations. Serial multiplication offers key advantages in these resource-constrained environments, including low-memory usage and minimal interconnect complexity. The most significant digit first (MSDF) serial multiplication scheme further enhances efficiency by enabling early termination and supporting variable precision. It is ideal for embedded applications where power and performance are critical. This letter proposes an auto-selection scheme for MSDF multiplication, where product digits are generated as a byproduct of residual maintenance, leading to speed, cost, and power efficiency improvements. We demonstrate the implementation of serial-serial and serial-parallel multipliers, where the multiplier operand in the latter is fully available throughout the computation. Simulation and synthesis results, compared to the most relevant previous works, show reductions in delay (16% and 20%), area consumption (11% and 23%), and power dissipation (7% and 20%), making our approach well-suited for embedded systems requiring efficient, low-power multiplication hardware.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"17 4","pages":"272-275"},"PeriodicalIF":2.0,"publicationDate":"2025-01-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144843068","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-13DOI: 10.1109/LES.2025.3528415
Amit Bhongade;A. P. Prathosh;Tapan Kumar Gandhi
Photoplethysmography (PPG) signals are extensively used for nonintrusive health monitoring, including deriving cardiorespiratory parameters. However, current approaches often face challenges with complexity and noise susceptibility. This study proposes a novel variational mode decomposition with principal component analysis (VMD-PCA) method to estimate respiratory parameters from a single PPG signal. The method was tested on ten healthy volunteers breathing at normal, fast, and slow rates, showing robust performance with an average RMSE of $3.23{pm }0.69$ , $21.69{pm }10.31$ , and $3.14{pm }1.35$ for each respiration rate (RR), respectively. Results indicate that VMD-PCA offers reliable real-time performance with enhanced resilience to motion artifacts, demonstrating its potential for practical health monitoring applications.
{"title":"A Robust VMD-PCA Integrated Approach for Accurate Respiration Parameter Estimation From PPG Signals","authors":"Amit Bhongade;A. P. Prathosh;Tapan Kumar Gandhi","doi":"10.1109/LES.2025.3528415","DOIUrl":"https://doi.org/10.1109/LES.2025.3528415","url":null,"abstract":"Photoplethysmography (PPG) signals are extensively used for nonintrusive health monitoring, including deriving cardiorespiratory parameters. However, current approaches often face challenges with complexity and noise susceptibility. This study proposes a novel variational mode decomposition with principal component analysis (VMD-PCA) method to estimate respiratory parameters from a single PPG signal. The method was tested on ten healthy volunteers breathing at normal, fast, and slow rates, showing robust performance with an average RMSE of <inline-formula> <tex-math>$3.23{pm }0.69$ </tex-math></inline-formula>, <inline-formula> <tex-math>$21.69{pm }10.31$ </tex-math></inline-formula>, and <inline-formula> <tex-math>$3.14{pm }1.35$ </tex-math></inline-formula> for each respiration rate (RR), respectively. Results indicate that VMD-PCA offers reliable real-time performance with enhanced resilience to motion artifacts, demonstrating its potential for practical health monitoring applications.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"17 4","pages":"230-233"},"PeriodicalIF":2.0,"publicationDate":"2025-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144843060","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A 256-bit high-performance hardware accelerator for elliptic curve cryptography (ECC) in GF$(p)$ over generic Weierstrass curves is presented in this letter. First, to improve the utilization of the multiplier, a new radix-128 Montgomery modular multiplication (MMM) without final reduction is proposed. Second, a combined-addition (CA) is proposed to recover the final reduction of MMM. The CA could reduce the clock cycles of continuous MMM. Finally, a high-parallelism Montgomery ladder hardware accelerator is presented to improve the performance of the elliptic curve point-multiplication (ECPM). The proposed accelerator consumes 766k gates and compute the 256-bit ECPM in 0.014 ms on ASIC with a 90 nm standard cell library. This is a higher performance design compared to the previous research in GF$(p)$ over generic Weierstrass curves.
{"title":"A High-Performance Hardware Accelerator for ECC in GF(p) Over Generic Weierstrass Curves","authors":"Yujun Xie;Riheng Yan;Yuan Liu;Xin Zheng;Shuting Cai;Xiaoming Xiong","doi":"10.1109/LES.2024.3514127","DOIUrl":"https://doi.org/10.1109/LES.2024.3514127","url":null,"abstract":"A 256-bit high-performance hardware accelerator for elliptic curve cryptography (ECC) in GF<inline-formula> <tex-math>$(p)$ </tex-math></inline-formula> over generic Weierstrass curves is presented in this letter. First, to improve the utilization of the multiplier, a new radix-128 Montgomery modular multiplication (MMM) without final reduction is proposed. Second, a combined-addition (CA) is proposed to recover the final reduction of MMM. The CA could reduce the clock cycles of continuous MMM. Finally, a high-parallelism Montgomery ladder hardware accelerator is presented to improve the performance of the elliptic curve point-multiplication (ECPM). The proposed accelerator consumes 766k gates and compute the 256-bit ECPM in 0.014 ms on ASIC with a 90 nm standard cell library. This is a higher performance design compared to the previous research in GF<inline-formula> <tex-math>$(p)$ </tex-math></inline-formula> over generic Weierstrass curves.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"17 4","pages":"214-217"},"PeriodicalIF":2.0,"publicationDate":"2024-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144843067","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-13DOI: 10.1109/LES.2024.3516853
Nicolas Belleville
Side-channel attacks are very efficient against AES implementations. In consequence, countermeasures are needed. Many works studied how to efficiently mask the AES, and in particular its SBox. In this letter, we revisit Genelle et al. approach based on secure conversion between Boolean and multiplicative masking, and show that with bitslicing along with other optimizations it enables computing a whole round with only four secure ANDs (SecAnd), making it very competitive in terms of performance. In particular, our second-order implementation is $1.18times $ faster than a fixsliced implementation, for similar binary size and security.
{"title":"Genelle et al. Revisited: Masking an AES Round With Only Four Secure ANDs","authors":"Nicolas Belleville","doi":"10.1109/LES.2024.3516853","DOIUrl":"https://doi.org/10.1109/LES.2024.3516853","url":null,"abstract":"Side-channel attacks are very efficient against AES implementations. In consequence, countermeasures are needed. Many works studied how to efficiently mask the AES, and in particular its SBox. In this letter, we revisit Genelle et al. approach based on secure conversion between Boolean and multiplicative masking, and show that with bitslicing along with other optimizations it enables computing a whole round with only four secure ANDs (<monospace>SecAnd</monospace>), making it very competitive in terms of performance. In particular, our second-order implementation is <inline-formula> <tex-math>$1.18times $ </tex-math></inline-formula> faster than a fixsliced implementation, for similar binary size and security.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"17 4","pages":"210-213"},"PeriodicalIF":2.0,"publicationDate":"2024-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144843058","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-11DOI: 10.1109/LES.2024.3516532
Christopher Bencini;Jason Mendola;Wei He;Sunwoong Kim
Edge-cloud computing architectures are exposed to significant security challenges. Although general encryption methods can mitigate some of these concerns, they require decryption to perform operations on data, exposing the data and secret keys to potential attacks. Homomorphic encryption (HE), which allows operations on encrypted data without decryption, provides an effective solution to this issue. Applying HE schemes to root-finding algorithms can expand the use of HE to a wider range of real-world applications that involve solving equations. This letter presents an adaptation of the well-known Newton’s method for use in the HE domain. Specifically, it employs a division-free approach to remove the division operation, which is not a basic HE operation. In addition, the proposed method is extended to handle a polynomial multiplicity greater than one for faster convergence. Compared to an alternative implementation that uses a numerical method for division, the proposed HE-based root-finding algorithm (HERFA) significantly reduces the number of sequential multiplications, which is a key factor limiting the feasibility of applications in the HE domain. This reduction allows HERFA to achieve faster execution speeds or higher accuracy.
{"title":"HERFA: A Homomorphic Encryption-Based Root-Finding Algorithm","authors":"Christopher Bencini;Jason Mendola;Wei He;Sunwoong Kim","doi":"10.1109/LES.2024.3516532","DOIUrl":"https://doi.org/10.1109/LES.2024.3516532","url":null,"abstract":"Edge-cloud computing architectures are exposed to significant security challenges. Although general encryption methods can mitigate some of these concerns, they require decryption to perform operations on data, exposing the data and secret keys to potential attacks. Homomorphic encryption (HE), which allows operations on encrypted data without decryption, provides an effective solution to this issue. Applying HE schemes to root-finding algorithms can expand the use of HE to a wider range of real-world applications that involve solving equations. This letter presents an adaptation of the well-known Newton’s method for use in the HE domain. Specifically, it employs a division-free approach to remove the division operation, which is not a basic HE operation. In addition, the proposed method is extended to handle a polynomial multiplicity greater than one for faster convergence. Compared to an alternative implementation that uses a numerical method for division, the proposed HE-based root-finding algorithm (HERFA) significantly reduces the number of sequential multiplications, which is a key factor limiting the feasibility of applications in the HE domain. This reduction allows HERFA to achieve faster execution speeds or higher accuracy.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"17 3","pages":"143-146"},"PeriodicalIF":1.7,"publicationDate":"2024-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144272962","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-11DOI: 10.1109/LES.2024.3513638
Paul Flammarion;Sajjad Parvin;Frank Sill Torres;Rolf Drechsler
In this letter, for the first time, we propose a security evaluation framework, namely, Auto-OPS, that automates performing the optical probing (OP) attack in simulation on a full GDS-II design file. Auto-OPS empowers designers by automatically extracting the active regions geometry model of each logic cell in the standard cell library or custom-designed logic cells to evaluate the security robustness of a design. Auto-OPS enables scaling up of the current OP evaluation environments which rely on manual extraction of active regions which is an error-prone and cumbersome procedure. Additionally, we evaluated and demonstrated the performance of our framework on several benchmark circuits GDS-II files designed using an open-source 45-nm standard cell library.
{"title":"Auto-OPS: A Framework for Automated Optical Probing Simulation on GDS-II","authors":"Paul Flammarion;Sajjad Parvin;Frank Sill Torres;Rolf Drechsler","doi":"10.1109/LES.2024.3513638","DOIUrl":"https://doi.org/10.1109/LES.2024.3513638","url":null,"abstract":"In this letter, for the first time, we propose a security evaluation framework, namely, Auto-OPS, that automates performing the optical probing (OP) attack in simulation on a full GDS-II design file. Auto-OPS empowers designers by automatically extracting the active regions geometry model of each logic cell in the standard cell library or custom-designed logic cells to evaluate the security robustness of a design. Auto-OPS enables scaling up of the current OP evaluation environments which rely on manual extraction of active regions which is an error-prone and cumbersome procedure. Additionally, we evaluated and demonstrated the performance of our framework on several benchmark circuits GDS-II files designed using an open-source 45-nm standard cell library.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"17 3","pages":"147-150"},"PeriodicalIF":1.7,"publicationDate":"2024-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144272961","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-09DOI: 10.1109/LES.2024.3510365
Mohamed El-Hadedy;Andrea Abelian;Kenny Lee;Benny N. Cheng;Wen-Mei Hwu
Field-programmable gate arrays (FPGAs) and field-programmable analog arrays (FPAAs) are reconfigurable circuits that enable flexible digital and analog implementations post-manufacturing. FPGAs are widely used in telecommunications, mixed-signal, and embedded systems due to their parallel processing and reconfigurability. Meanwhile, FPAAs provide flexibility for analog systems, which is crucial for modern mixed-signal processing. This letter introduces ANUBIS, a hybrid system combining FPGA and FPAA technologies to generate true random number generators (TRNGs) for secure UAV communication. Due to its reliability and cost efficiency, ANUBIS leverages a thermistor circuit as an entropy source. The FPAA amplifies the analog noise generated by the thermistor, while the FPGA digitizes and processes the signal using Von Neumann whitening (VNW) to remove bias. The ASCON hash function is applied to the whitened bitstream to generate cryptographically secure keys. These keys are utilized in a DHKE to enable secure communication via Bluetooth low energy (BLE), an ideal protocol for energy-constrained UAV applications. ANUBIS demonstrates reconfigurability, power efficiency, and ease of implementation, showcasing its potential for secure communication applications. It achieves robust randomization, setting a new standard for UAV communication security and addressing applications requiring reliable TRNG solutions. The system consumes 1.615 W in total, with 1.54 W consumed by the FPGA and 75 mW by the FPAA. Resource utilization on the PYNQ-Z1 board includes 5186 LUTs (9.75%), 549 units of memory (3.15%), and 5.5 units of BRAM (3.93%), indicating moderate resource usage with room for future enhancements. By integrating reliable analog noise harvesting with efficient digital post-processing, ANUBIS offers a novel approach to TRNG design, demonstrating the potential for broader cryptographic applications in resource-constrained environments.
{"title":"ANUBIS: Hybrid FPAA-FPGA Architecture for Entropy-Based True Random Number Generation in Secure UAV Communication","authors":"Mohamed El-Hadedy;Andrea Abelian;Kenny Lee;Benny N. Cheng;Wen-Mei Hwu","doi":"10.1109/LES.2024.3510365","DOIUrl":"https://doi.org/10.1109/LES.2024.3510365","url":null,"abstract":"Field-programmable gate arrays (FPGAs) and field-programmable analog arrays (FPAAs) are reconfigurable circuits that enable flexible digital and analog implementations post-manufacturing. FPGAs are widely used in telecommunications, mixed-signal, and embedded systems due to their parallel processing and reconfigurability. Meanwhile, FPAAs provide flexibility for analog systems, which is crucial for modern mixed-signal processing. This letter introduces ANUBIS, a hybrid system combining FPGA and FPAA technologies to generate true random number generators (TRNGs) for secure UAV communication. Due to its reliability and cost efficiency, ANUBIS leverages a thermistor circuit as an entropy source. The FPAA amplifies the analog noise generated by the thermistor, while the FPGA digitizes and processes the signal using Von Neumann whitening (VNW) to remove bias. The ASCON hash function is applied to the whitened bitstream to generate cryptographically secure keys. These keys are utilized in a DHKE to enable secure communication via Bluetooth low energy (BLE), an ideal protocol for energy-constrained UAV applications. ANUBIS demonstrates reconfigurability, power efficiency, and ease of implementation, showcasing its potential for secure communication applications. It achieves robust randomization, setting a new standard for UAV communication security and addressing applications requiring reliable TRNG solutions. The system consumes 1.615 W in total, with 1.54 W consumed by the FPGA and 75 mW by the FPAA. Resource utilization on the PYNQ-Z1 board includes 5186 LUTs (9.75%), 549 units of memory (3.15%), and 5.5 units of BRAM (3.93%), indicating moderate resource usage with room for future enhancements. By integrating reliable analog noise harvesting with efficient digital post-processing, ANUBIS offers a novel approach to TRNG design, demonstrating the potential for broader cryptographic applications in resource-constrained environments.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"17 3","pages":"164-167"},"PeriodicalIF":1.7,"publicationDate":"2024-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144272959","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Recently, conditional computation has been applied to on-device object detection to solve the conflict between huge computation requirements of deep neural network (DNN) and limited computation resources of edge devices. There is a need for an optimized inference scheme that can efficiently perform conditional computation in on-device object detection. This letter proposes a predictor which can predict router decisions of conditional computation. Based on the predictor, this letter also presents an inference scheme which hides router latency through concurrently executing router and the predicted branch. The proposed predictor shows higher accuracy than profiling-based method, and experiment shows that our inference scheme can get latency decrease over traditional scheme.
{"title":"Optimized Inference Scheme for Conditional Computation in On-Device Object Detection","authors":"Kairong Zhao;Yinghui Chang;Weikang Wu;Zirun Li;Hongyin Luo;Shan He;Donghui Guo","doi":"10.1109/LES.2024.3514920","DOIUrl":"https://doi.org/10.1109/LES.2024.3514920","url":null,"abstract":"Recently, conditional computation has been applied to on-device object detection to solve the conflict between huge computation requirements of deep neural network (DNN) and limited computation resources of edge devices. There is a need for an optimized inference scheme that can efficiently perform conditional computation in on-device object detection. This letter proposes a predictor which can predict router decisions of conditional computation. Based on the predictor, this letter also presents an inference scheme which hides router latency through concurrently executing router and the predicted branch. The proposed predictor shows higher accuracy than profiling-based method, and experiment shows that our inference scheme can get latency decrease over traditional scheme.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"17 3","pages":"135-138"},"PeriodicalIF":1.7,"publicationDate":"2024-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144272956","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-09DOI: 10.1109/LES.2024.3513852
Ping-Xiang Chen;Dongjoo Seo;Nikil Dutt
In the above article [1], there is a correction to introduction section in line 6, write application factor (WAF) should be write amplification factor.Also, please include the following link to the acknowledgment: https://github.com/pingxiang-chen/fuse-fdpfs.
{"title":"Corrections to “FDPFS: Leveraging File System Abstraction for FDP SSD Data Placement”","authors":"Ping-Xiang Chen;Dongjoo Seo;Nikil Dutt","doi":"10.1109/LES.2024.3513852","DOIUrl":"https://doi.org/10.1109/LES.2024.3513852","url":null,"abstract":"In the above article <xref>[1]</xref>, there is a correction to introduction section in line 6, write application factor (WAF) should be write amplification factor.Also, please include the following link to the acknowledgment: <uri>https://github.com/pingxiang-chen/fuse-fdpfs</uri>.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"17 1","pages":"66-66"},"PeriodicalIF":1.7,"publicationDate":"2024-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10787027","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143403918","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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