Pub Date : 2024-04-10DOI: 10.1109/LES.2024.3387310
A. Hernández-Benítez;J. Vázquez-Castillo;Johan J. Estrada-López;G. Becerra-Nunez;N. Cólin-García;A. Castillo-Atoche
Hydroponic farming is a promising alternative to soil-based farming. However, it requires a precise control of the growth environment, which is hard to achieve with energy-constrained embedded systems. This letter presents an energy optimization technique for the continuous operation of energy harvesting-based hydroponics sensor nodes. The proposed technique is based on the self-tuning model, that dynamically adjust the duty cycle of the node, ensuring the autonomous operation of the Internet of Things system. The model can be programmed in a low-power microcontroller, allowing the decision-making process to reside entirely on the sensor node. Experimental results show that in the same time period, the self-tuning model allows $3.5times $ more data transmissions than a uniform 5-min duty cycle, while ensuring a minimum voltage level in the storage device. This balance allows the stored energy to be enough for continuous monitoring, providing a clean and cost-effective alternative to perpetually power the hydroponic system.
{"title":"Self-Tuning Model for Energy-Context Optimization in Perpetual Sensor Nodes Within IoT-Integrated Hydroponic Systems","authors":"A. Hernández-Benítez;J. Vázquez-Castillo;Johan J. Estrada-López;G. Becerra-Nunez;N. Cólin-García;A. Castillo-Atoche","doi":"10.1109/LES.2024.3387310","DOIUrl":"10.1109/LES.2024.3387310","url":null,"abstract":"Hydroponic farming is a promising alternative to soil-based farming. However, it requires a precise control of the growth environment, which is hard to achieve with energy-constrained embedded systems. This letter presents an energy optimization technique for the continuous operation of energy harvesting-based hydroponics sensor nodes. The proposed technique is based on the self-tuning model, that dynamically adjust the duty cycle of the node, ensuring the autonomous operation of the Internet of Things system. The model can be programmed in a low-power microcontroller, allowing the decision-making process to reside entirely on the sensor node. Experimental results show that in the same time period, the self-tuning model allows \u0000<inline-formula> <tex-math>$3.5times $ </tex-math></inline-formula>\u0000 more data transmissions than a uniform 5-min duty cycle, while ensuring a minimum voltage level in the storage device. This balance allows the stored energy to be enough for continuous monitoring, providing a clean and cost-effective alternative to perpetually power the hydroponic system.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"16 3","pages":"267-270"},"PeriodicalIF":1.7,"publicationDate":"2024-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140569027","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Digitalization and automation in the agricultural sector enable the enhancement of production processes, leading to increased yields. Specifically, the medications administration or complementary treatments in animals often prove to be a demanding task for human operators. This letter introduces an embedded system prototype that facilitates monitoring the level of capsules coverage in troughs through image processing. The suggested system enables an innovative antiparasitic treatment using biological control agents. The prototype utilizes a Raspberry Pi 3B as the platform to execute the developed image processing algorithm. The obtained results successfully demonstrate the algorithm’s accurate functionality estimating capsules coverage within the troughs.
农业领域的数字化和自动化能够改进生产流程，提高产量。具体来说，动物的用药或辅助治疗往往是一项对人类操作员要求很高的任务。这封信介绍了一种嵌入式系统原型，它可通过图像处理来监控食槽中胶囊的覆盖水平。所建议的系统能够利用生物控制剂进行创新的抗寄生虫治疗。原型利用 Raspberry Pi 3B 作为平台，执行开发的图像处理算法。所获得的结果成功地证明了该算法在估算食槽中胶囊覆盖率方面的准确功能。
{"title":"Automated Parasite Control System Prototype Through Capsule Dosage Based on Image Processing","authors":"Ezequiel Carbajo;Lucas Leiva;Juan Toloza;Martín Vázquez;Silvina Fernández;Federica Sagües;Milagros Junco;Inés Guerrero;Sara Zegbi;Carlos Saumell","doi":"10.1109/LES.2024.3386336","DOIUrl":"10.1109/LES.2024.3386336","url":null,"abstract":"Digitalization and automation in the agricultural sector enable the enhancement of production processes, leading to increased yields. Specifically, the medications administration or complementary treatments in animals often prove to be a demanding task for human operators. This letter introduces an embedded system prototype that facilitates monitoring the level of capsules coverage in troughs through image processing. The suggested system enables an innovative antiparasitic treatment using biological control agents. The prototype utilizes a Raspberry Pi 3B as the platform to execute the developed image processing algorithm. The obtained results successfully demonstrate the algorithm’s accurate functionality estimating capsules coverage within the troughs.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"16 3","pages":"303-306"},"PeriodicalIF":1.7,"publicationDate":"2024-04-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140569348","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-04-03DOI: 10.1109/LES.2024.3384843
Gerardo Avalos-Almazan;Sarahi Aguayo-Tapia;Jose De Jesus Rangel-Magdaleno;Victor Aviña-Corral
This research centers on the application of the discrete-time Taylor–Fourier transform (DTTFT) algorithmic implementation for phasor estimation on a field-programmable gate array board. The system employs a finite impulse response structure of a digital Taylor–Fourier filter to extract amplitude and phase information. The hardware description utilizes a multiply accumulator architecture with only forty embedded 9-bit multiplier elements, achieving an 18-bit input–output resolution. Performance assessment involves signal analysis through FPGA-in-the-loop simulation in MATLAB/Simulink. Findings demonstrate that the DTTFT-based phasor estimator can be effectively characterized using VHDL code and implemented on an Intel D2-115 board.
{"title":"FPGA-Based Digital Taylor–Fourier Transform","authors":"Gerardo Avalos-Almazan;Sarahi Aguayo-Tapia;Jose De Jesus Rangel-Magdaleno;Victor Aviña-Corral","doi":"10.1109/LES.2024.3384843","DOIUrl":"10.1109/LES.2024.3384843","url":null,"abstract":"This research centers on the application of the discrete-time Taylor–Fourier transform (DTTFT) algorithmic implementation for phasor estimation on a field-programmable gate array board. The system employs a finite impulse response structure of a digital Taylor–Fourier filter to extract amplitude and phase information. The hardware description utilizes a multiply accumulator architecture with only forty embedded 9-bit multiplier elements, achieving an 18-bit input–output resolution. Performance assessment involves signal analysis through FPGA-in-the-loop simulation in MATLAB/Simulink. Findings demonstrate that the DTTFT-based phasor estimator can be effectively characterized using VHDL code and implemented on an Intel D2-115 board.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"16 3","pages":"299-302"},"PeriodicalIF":1.7,"publicationDate":"2024-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140569651","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-03-27DOI: 10.1109/LES.2024.3382615
Lucas A. Rabioglio;M. C. Cebedio;L. Arnone;L. De Micco;J. Castiñeira Moreira
This letter introduces the design of an estimator for parameters of Middleton Class A noise using its canonical formula and classical numerical methods. The main focus is to acquire parameters to characterize communication channels in intelligent systems or those based on cognitive paradigms. A comprehensive analysis of the first-order characteristics of the Middleton Class A noise model is conducted to establish the foundational understanding necessary for developing the presented estimator model, named impulsive noise estimator with minimization methods (INEMM). Subsequently, the method is introduced, substantiated, and compared to various established estimators concerning precision and complexity. Results show a distinct advantage in terms of overall performance.
这封信介绍了如何利用米德尔顿 A 类噪声的经典公式和经典数值方法设计一种米德尔顿 A 类噪声参数估计器。主要重点是获取参数，以描述智能系统或基于认知范式的通信信道的特征。我们对 Middleton A 类噪声模型的一阶特征进行了全面分析，以建立必要的基础认识，从而开发出所提出的估计模型，并将其命名为脉冲噪声最小化方法估计模型（INEMM）。随后，对该方法进行了介绍、论证，并就精度和复杂性与各种成熟的估计方法进行了比较。结果表明，该方法在整体性能方面具有明显优势。
{"title":"Impulsive Noise Estimator With Minimization Methods (INEMM) on Software","authors":"Lucas A. Rabioglio;M. C. Cebedio;L. Arnone;L. De Micco;J. Castiñeira Moreira","doi":"10.1109/LES.2024.3382615","DOIUrl":"10.1109/LES.2024.3382615","url":null,"abstract":"This letter introduces the design of an estimator for parameters of Middleton Class A noise using its canonical formula and classical numerical methods. The main focus is to acquire parameters to characterize communication channels in intelligent systems or those based on cognitive paradigms. A comprehensive analysis of the first-order characteristics of the Middleton Class A noise model is conducted to establish the foundational understanding necessary for developing the presented estimator model, named impulsive noise estimator with minimization methods (INEMM). Subsequently, the method is introduced, substantiated, and compared to various established estimators concerning precision and complexity. Results show a distinct advantage in terms of overall performance.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"16 3","pages":"291-294"},"PeriodicalIF":1.7,"publicationDate":"2024-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140314293","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Parsing value change dump (VCD) files through signal turnover behavior is important for power analysis and estimation. In practical applications, the size of VCD files can reach hundreds of GB. Thus, designing an efficient VCD parser for parsing large VCD files is of great significance. Different from the traditional hash search functions applied in many VCD parsers, this letter proposes a specific search algorithm based on the rules of identifiers in VCD files. Then, a high-performance VCD parser is constructed. The parser supports single-core and multicore modes. Based on the regression test, the function of the VCD parser is verified. Experimental results show that the proposed VCD parser is faster and more functional than the vcd2saif. In multicore mode, our VCD parser only takes about 8.139 s to parse 1-GB VCD files, and the time consumption of the search algorithm only accounts for 2% of the total CPU time.
{"title":"An Efficient VCD Parser for Dynamic Power Estimation of Digital Integrated Circuits","authors":"Xin Zheng;Shaofen Zeng;Yongfeng Zhong;Chenyu Huang;Xianghong Hu;Xiaoming Xiong","doi":"10.1109/LES.2024.3380048","DOIUrl":"10.1109/LES.2024.3380048","url":null,"abstract":"Parsing value change dump (VCD) files through signal turnover behavior is important for power analysis and estimation. In practical applications, the size of VCD files can reach hundreds of GB. Thus, designing an efficient VCD parser for parsing large VCD files is of great significance. Different from the traditional hash search functions applied in many VCD parsers, this letter proposes a specific search algorithm based on the rules of identifiers in VCD files. Then, a high-performance VCD parser is constructed. The parser supports single-core and multicore modes. Based on the regression test, the function of the VCD parser is verified. Experimental results show that the proposed VCD parser is faster and more functional than the vcd2saif. In multicore mode, our VCD parser only takes about 8.139 s to parse 1-GB VCD files, and the time consumption of the search algorithm only accounts for 2% of the total CPU time.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"16 4","pages":"461-464"},"PeriodicalIF":1.7,"publicationDate":"2024-03-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140298588","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-03-20DOI: 10.1109/LES.2024.3403090
Andreas Karatzas;Iraklis Anagnostopoulos
Modern deep learning agents usually operate in low-dimensional environments. They process pixel input, do not offer insights into their thought process, and require significant power and computational resources. These characteristics make them inapplicable for embedded devices. In this letter, we present Pythia, an edge-first framework that uses latent imagination to handle complex environments efficiently and envision future agent states. It utilizes a vector quantized variational autoencoder to reduce the high-dimensional features into a low-dimensional space, making it ideal for modern embedded devices. Moreover, Pythia offers human interpretable feedback and scales well with respect to the design space. Pythia surpassed the other state-of-the-art models in prediction accuracy on both intrinsic and extrinsic metrics.
{"title":"Pythia: An Edge-First Agent for State Prediction in High-Dimensional Environments","authors":"Andreas Karatzas;Iraklis Anagnostopoulos","doi":"10.1109/LES.2024.3403090","DOIUrl":"10.1109/LES.2024.3403090","url":null,"abstract":"Modern deep learning agents usually operate in low-dimensional environments. They process pixel input, do not offer insights into their thought process, and require significant power and computational resources. These characteristics make them inapplicable for embedded devices. In this letter, we present Pythia, an edge-first framework that uses latent imagination to handle complex environments efficiently and envision future agent states. It utilizes a vector quantized variational autoencoder to reduce the high-dimensional features into a low-dimensional space, making it ideal for modern embedded devices. Moreover, Pythia offers human interpretable feedback and scales well with respect to the design space. Pythia surpassed the other state-of-the-art models in prediction accuracy on both intrinsic and extrinsic metrics.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"16 4","pages":"473-476"},"PeriodicalIF":1.7,"publicationDate":"2024-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141150412","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-03-13DOI: 10.1109/LES.2024.3377180
José L. I. Rangel;Moises I. Arroyo;Eduardo Vázquez;Juan G. Avalos;Giovanny Sanchez
Finite-field arithmetic operations are vital for the computation of complex cryptography algorithms used in several cutting-edge applications, such as side-channel attacks, authentication, and digital signatures, among others. Currently, the simulation of these algorithms exceeds the computational capabilities of conventional computing systems. This aspect becomes critical, especially when these algorithms are implemented in resource-constrained electronic appliances. In particular, the improvement of execution time in these devices generally require more area. To overcome this issue, a large number of works have been focused on the development of compact conventional binary finite-field arithmetic circuits over GF(p) since these demand a large area consumption. Inspired by neural phenomena, a new emerging branch of computer science has made intensive efforts to improve area consumption of conventional arithmetic circuits. However, the development of compact finite-field arithmetic circuits over GF(p) is a still a challenging task. In this letter, we present for the first time, the design of four new finite-field arithmetic circuits over GF(p) based on spiking neural P (SN P) systems with communication on request. In addition, we propose a neural processor to perform four new finite-field arithmetic operations over GF(p) by using the same processing core, which is not feasible with the use of conventional binary circuits since each finite-field arithmetic-binary circuit over GF(p) is implemented separately, to significantly improve the area consumption. This has mainly been achieved since the neural processor dynamically change its configuration, which is defined in terms of the connectivity and firing rules of each neuron.
{"title":"New Compact Finite-Field Arithmetic Circuits Over GF(p) Based on Spiking Neural P Systems With Communication on Request Implemented in a Low-Cost FPGA","authors":"José L. I. Rangel;Moises I. Arroyo;Eduardo Vázquez;Juan G. Avalos;Giovanny Sanchez","doi":"10.1109/LES.2024.3377180","DOIUrl":"10.1109/LES.2024.3377180","url":null,"abstract":"Finite-field arithmetic operations are vital for the computation of complex cryptography algorithms used in several cutting-edge applications, such as side-channel attacks, authentication, and digital signatures, among others. Currently, the simulation of these algorithms exceeds the computational capabilities of conventional computing systems. This aspect becomes critical, especially when these algorithms are implemented in resource-constrained electronic appliances. In particular, the improvement of execution time in these devices generally require more area. To overcome this issue, a large number of works have been focused on the development of compact conventional binary finite-field arithmetic circuits over GF(p) since these demand a large area consumption. Inspired by neural phenomena, a new emerging branch of computer science has made intensive efforts to improve area consumption of conventional arithmetic circuits. However, the development of compact finite-field arithmetic circuits over GF(p) is a still a challenging task. In this letter, we present for the first time, the design of four new finite-field arithmetic circuits over GF(p) based on spiking neural P (SN P) systems with communication on request. In addition, we propose a neural processor to perform four new finite-field arithmetic operations over GF(p) by using the same processing core, which is not feasible with the use of conventional binary circuits since each finite-field arithmetic-binary circuit over GF(p) is implemented separately, to significantly improve the area consumption. This has mainly been achieved since the neural processor dynamically change its configuration, which is defined in terms of the connectivity and firing rules of each neuron.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"16 3","pages":"295-298"},"PeriodicalIF":1.7,"publicationDate":"2024-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140128992","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-03-13DOI: 10.1109/LES.2024.3376801
Seunghoon Lee;Jinkyu Lee
Machine learning methods have been used to solve real-time scheduling problems but none has yet made an architecture that utilizes influences between real-time tasks as input features. This letter proposes a novel approach to partitioned scheduling in real-time systems using graph machine learning. We present a graph representation of real-time task sets that enable graph machine-learning schemes to capture the influence between real-time tasks. By using a graph attention network (GAT) with this method, our model successfully partitioned-schedule task sets that were previously deemed unschedulable by state-of-the-art partitioned scheduling algorithms. The GAT is used to establish relationships between nodes in the graph, which represent real-time tasks, and to learn how these relationships affect the schedulability of the system.
{"title":"A Graph Attention Network Approach to Partitioned Scheduling in Real-Time Systems","authors":"Seunghoon Lee;Jinkyu Lee","doi":"10.1109/LES.2024.3376801","DOIUrl":"10.1109/LES.2024.3376801","url":null,"abstract":"Machine learning methods have been used to solve real-time scheduling problems but none has yet made an architecture that utilizes influences between real-time tasks as input features. This letter proposes a novel approach to partitioned scheduling in real-time systems using graph machine learning. We present a graph representation of real-time task sets that enable graph machine-learning schemes to capture the influence between real-time tasks. By using a graph attention network (GAT) with this method, our model successfully partitioned-schedule task sets that were previously deemed unschedulable by state-of-the-art partitioned scheduling algorithms. The GAT is used to establish relationships between nodes in the graph, which represent real-time tasks, and to learn how these relationships affect the schedulability of the system.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"16 4","pages":"457-460"},"PeriodicalIF":1.7,"publicationDate":"2024-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140128742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-03-09DOI: 10.1109/LES.2024.3399071
Khalid Javeed;David Gregg
This letter presents a novel and efficient hardware architecture to accelerate the computation of point multiplication (PM) primitive over arbitrary Montgomery curves (MCs). It is based on a new novel double field multiplier (DFM) that computes two field multiplications simultaneously. The DFM uses the interleaved multiplication technique, and it shortens the critical path of the circuit by computing two results at once. It is generic to work for any prime structure and curve parameters over the MCs. At the system level, a fast scheduling methodology is also presented to execute the field-level operations with the Montgomery ladder (ML) approach. Our ML and DFM designs perform the same operations regardless of the input values, which provides resistance to timing and simple power analysis side-channel attacks. It is synthesized and implemented over different FPGA platforms. The implementation results confirm that it outperforms the state-of-the-art in terms of area-time product and throughput/slice. To the best of the authors’ knowledge, it is the first fully LUT-based architecture for the arbitrary MCs.
{"title":"Point Multiplication Accelerator for Arbitrary Montgomery Curves","authors":"Khalid Javeed;David Gregg","doi":"10.1109/LES.2024.3399071","DOIUrl":"10.1109/LES.2024.3399071","url":null,"abstract":"This letter presents a novel and efficient hardware architecture to accelerate the computation of point multiplication (PM) primitive over arbitrary Montgomery curves (MCs). It is based on a new novel double field multiplier (DFM) that computes two field multiplications simultaneously. The DFM uses the interleaved multiplication technique, and it shortens the critical path of the circuit by computing two results at once. It is generic to work for any prime structure and curve parameters over the MCs. At the system level, a fast scheduling methodology is also presented to execute the field-level operations with the Montgomery ladder (ML) approach. Our ML and DFM designs perform the same operations regardless of the input values, which provides resistance to timing and simple power analysis side-channel attacks. It is synthesized and implemented over different FPGA platforms. The implementation results confirm that it outperforms the state-of-the-art in terms of area-time product and throughput/slice. To the best of the authors’ knowledge, it is the first fully LUT-based architecture for the arbitrary MCs.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"16 4","pages":"465-468"},"PeriodicalIF":1.7,"publicationDate":"2024-03-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140930446","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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