Pub Date : 2025-02-27DOI: 10.1109/LES.2025.3546543
A. Sharma;G. Purohit;A. R. Asati
This letter presents a novel architecture for a high-throughput encoder for quasi-cyclic low-density parity-check codes. This low-complexity encoder is specifically tailored for the 5th generation (5G) new radio (NR) standard. To achieve high throughput, we employ an automated approach to design customized encoders for individual base graphs using a Verilog Code Generator (VeCoGen) that we developed in MATLAB. Our proposed architecture improves efficiency by rearranging the wire indices during the hardware design language code generation stage itself, instead of performing shifting operations on the data carried by those wires on the fly. This eliminates the need for RAM (for storing base graph coefficients) and dedicated barrel shifters. The parity bits are computed in parallel, while maintaining optimal performance and gate count through effective exploitation of the base graph’s sparsity. Consequently, the encoder can be designed as a fully combinational circuit between the input and output registers, enabling the generation of the complete codeword within a single clock cycle. This results in exceptionally high throughput, optimal hardware utilization, and minimal number of xor operations, making our approach highly effective for 5G NR applications.
{"title":"FPGA-Based Implementation of Single-Cycle High-Throughput LDPC Encoder for 5G New Radio","authors":"A. Sharma;G. Purohit;A. R. Asati","doi":"10.1109/LES.2025.3546543","DOIUrl":"https://doi.org/10.1109/LES.2025.3546543","url":null,"abstract":"This letter presents a novel architecture for a high-throughput encoder for quasi-cyclic low-density parity-check codes. This low-complexity encoder is specifically tailored for the 5th generation (5G) new radio (NR) standard. To achieve high throughput, we employ an automated approach to design customized encoders for individual base graphs using a Verilog Code Generator (VeCoGen) that we developed in MATLAB. Our proposed architecture improves efficiency by rearranging the wire indices during the hardware design language code generation stage itself, instead of performing shifting operations on the data carried by those wires on the fly. This eliminates the need for RAM (for storing base graph coefficients) and dedicated barrel shifters. The parity bits are computed in parallel, while maintaining optimal performance and gate count through effective exploitation of the base graph’s sparsity. Consequently, the encoder can be designed as a fully combinational circuit between the input and output registers, enabling the generation of the complete codeword within a single clock cycle. This results in exceptionally high throughput, optimal hardware utilization, and minimal number of <sc>xor</small> operations, making our approach highly effective for 5G NR applications.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"17 6","pages":"439-442"},"PeriodicalIF":2.0,"publicationDate":"2025-02-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145778304","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-02-25DOI: 10.1109/LES.2025.3545798
Luis R. Islas-Estrada;Diego A. Flores-Hernández
In recent years, the use of solar technology as an alternative to conventional methods of electricity generation has increased. However, they have a low conversion efficiency; one way to increase energy production is by using solar tracking systems (STS), which cause energy expenditure. Monitoring systems are required to calculate the energy balance between produced and consumed. In this research, the design and implementation from a concurrent approach of an embedded system for energy monitoring in solar applications is presented, obtaining a low energy consumption, high connectivity, scalable, modular, and open architecture system. Experimental tests were carried out considering five proposed energy-saving strategies. These tests recorded the energy consumption of actuators, electronic hardware, and generated power, resulting in a 16.47% increase in the energy budget and a reduction in the global power consumption of 7.27%. Notably, the developed embedded system exhibited a low energy consumption of 0.326 Wh.
{"title":"Embedded Energy Monitoring System for Solar Applications","authors":"Luis R. Islas-Estrada;Diego A. Flores-Hernández","doi":"10.1109/LES.2025.3545798","DOIUrl":"https://doi.org/10.1109/LES.2025.3545798","url":null,"abstract":"In recent years, the use of solar technology as an alternative to conventional methods of electricity generation has increased. However, they have a low conversion efficiency; one way to increase energy production is by using solar tracking systems (STS), which cause energy expenditure. Monitoring systems are required to calculate the energy balance between produced and consumed. In this research, the design and implementation from a concurrent approach of an embedded system for energy monitoring in solar applications is presented, obtaining a low energy consumption, high connectivity, scalable, modular, and open architecture system. Experimental tests were carried out considering five proposed energy-saving strategies. These tests recorded the energy consumption of actuators, electronic hardware, and generated power, resulting in a 16.47% increase in the energy budget and a reduction in the global power consumption of 7.27%. Notably, the developed embedded system exhibited a low energy consumption of 0.326 Wh.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"17 6","pages":"386-389"},"PeriodicalIF":2.0,"publicationDate":"2025-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145778176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-02-21DOI: 10.1109/LES.2025.3544623
Cheng-Kai Lu;Jun-Yu Shen;Cheng-Hung Lin;Chung-Yueh Lien;Ding Su Yen
Floating debris in aquatic environments poses ecological risks, necessitating prompt detection to prevent its spread into oceans, where recovery is challenging. This letter introduces an optimized YOLOv4-based detection framework tailored for small-scale floating debris on embedded systems, specifically for the Raspberry Pi 4 with integrated camera modules. Key innovations include a modified REGP pooling layer, enhanced spatial pyramid pooling (SPP), and reduced detection heads, boosting mean Average Precision (mAP) by 7.91% on the FloW dataset while reducing parameters by 26.35% compared to the baseline model. These improvements enhance computational efficiency, achieving real-time performance at 15 fps with 2.8 W power consumption, making it ideal for large-scale environmental monitoring.
{"title":"Efficient Embedded System for Small Object Detection: A Case Study on Floating Debris in Environmental Monitoring","authors":"Cheng-Kai Lu;Jun-Yu Shen;Cheng-Hung Lin;Chung-Yueh Lien;Ding Su Yen","doi":"10.1109/LES.2025.3544623","DOIUrl":"https://doi.org/10.1109/LES.2025.3544623","url":null,"abstract":"Floating debris in aquatic environments poses ecological risks, necessitating prompt detection to prevent its spread into oceans, where recovery is challenging. This letter introduces an optimized YOLOv4-based detection framework tailored for small-scale floating debris on embedded systems, specifically for the Raspberry Pi 4 with integrated camera modules. Key innovations include a modified REGP pooling layer, enhanced spatial pyramid pooling (SPP), and reduced detection heads, boosting mean Average Precision (mAP) by 7.91% on the FloW dataset while reducing parameters by 26.35% compared to the baseline model. These improvements enhance computational efficiency, achieving real-time performance at 15 fps with 2.8 W power consumption, making it ideal for large-scale environmental monitoring.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"17 4","pages":"264-267"},"PeriodicalIF":2.0,"publicationDate":"2025-02-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144843059","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-02-20DOI: 10.1109/LES.2025.3544121
Soheil Mahdizadeh;Elyas Oustad;Mohsen Ansari
Reducing latency in the Internet of Things (IoT) remains a critical challenge. While cloud computing supports data processing, it often fails to meet real-time demands due to its distance from end users. Edge and fog computing address this issue by positioning processing resources closer to devices, reducing latency, and enhancing performance. In this letter, we propose a node placement strategy using a fictitious play game theory approach, where each node iteratively adjusts its placement based on interactions with neighboring nodes to minimize latency and cost. Our method assigns tasks by selecting the nearest available node with adequate processing resources, allowing for dynamic task handling across the network. Simulation results demonstrate that the proposed fictitious play approach effectively reduces latency and cost, achieving an average improvement of 32.5% in a combined penalty that considers both average latency and total cost, compared to state-of-the-art methods.
{"title":"Fictitious Play Game Theory for Server Deployment Optimization in Edge–Fog Environments","authors":"Soheil Mahdizadeh;Elyas Oustad;Mohsen Ansari","doi":"10.1109/LES.2025.3544121","DOIUrl":"https://doi.org/10.1109/LES.2025.3544121","url":null,"abstract":"Reducing latency in the Internet of Things (IoT) remains a critical challenge. While cloud computing supports data processing, it often fails to meet real-time demands due to its distance from end users. Edge and fog computing address this issue by positioning processing resources closer to devices, reducing latency, and enhancing performance. In this letter, we propose a node placement strategy using a fictitious play game theory approach, where each node iteratively adjusts its placement based on interactions with neighboring nodes to minimize latency and cost. Our method assigns tasks by selecting the nearest available node with adequate processing resources, allowing for dynamic task handling across the network. Simulation results demonstrate that the proposed fictitious play approach effectively reduces latency and cost, achieving an average improvement of 32.5% in a combined penalty that considers both average latency and total cost, compared to state-of-the-art methods.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"17 4","pages":"260-263"},"PeriodicalIF":2.0,"publicationDate":"2025-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144842983","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-02-18DOI: 10.1109/LES.2025.3539308
Sungyoun Hwang;Kon-Woo Kwon;Yongtae Kim
This letter presents a novel hardware-efficient approximate 4-2 compressor design that significantly enhances accuracy through a systematic analysis of input patterns obtained from practical applications. We incorporate a majority operation and a compound gate in the compressor design to effectively boost hardware efficiency in multiplications. Our design approach results in substantial error reductions, with normalized mean error distance (NMED) and mean relative error distance (MRED) decreasing by up to 74.84% and 82.04%, respectively, compared to existing approximate multipliers discussed in this letter. When implemented in a 32-nm CMOS technology, the approximate multiplier adopting the proposed 4-2 compressor achieves excellent hardware efficiency, reducing area, power, and energy consumption by up to 8.95%, 13.02%, and 13.02%, respectively, compared to the other alternatives. Moreover, our design delivers enhanced performance in image processing tasks, achieving up to a $4.84times $ increase in peak signal-to-noise ratio (PSNR) compared to other designs, all while optimizing hardware efficiency.
{"title":"Design of a Hardware-Efficient Approximate 4-2 Compressor for Multiplications in Image Processing","authors":"Sungyoun Hwang;Kon-Woo Kwon;Yongtae Kim","doi":"10.1109/LES.2025.3539308","DOIUrl":"https://doi.org/10.1109/LES.2025.3539308","url":null,"abstract":"This letter presents a novel hardware-efficient approximate 4-2 compressor design that significantly enhances accuracy through a systematic analysis of input patterns obtained from practical applications. We incorporate a majority operation and a compound gate in the compressor design to effectively boost hardware efficiency in multiplications. Our design approach results in substantial error reductions, with normalized mean error distance (NMED) and mean relative error distance (MRED) decreasing by up to 74.84% and 82.04%, respectively, compared to existing approximate multipliers discussed in this letter. When implemented in a 32-nm CMOS technology, the approximate multiplier adopting the proposed 4-2 compressor achieves excellent hardware efficiency, reducing area, power, and energy consumption by up to 8.95%, 13.02%, and 13.02%, respectively, compared to the other alternatives. Moreover, our design delivers enhanced performance in image processing tasks, achieving up to a <inline-formula> <tex-math>$4.84times $ </tex-math></inline-formula> increase in peak signal-to-noise ratio (PSNR) compared to other designs, all while optimizing hardware efficiency.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"17 4","pages":"226-229"},"PeriodicalIF":2.0,"publicationDate":"2025-02-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144842960","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-02-13DOI: 10.1109/LES.2025.3541818
A. J. Bhuvaneshwari;P. Kaythry;K. J. Jegadish Kumar;D. Sachin
Ascon is an intended lightweight algorithm designed to deliver efficiency and security for resource-constrained Internet of Things (IoT) devices. This letter presents a field-programmable gate array (FPGA) implementation of the pipelined architecture of Ascon for rapid execution. The objective is to optimize the datapath to achieve high throughput while maintaining a minimal hardware footprint. The proposed 7-stage pipelined Ascon (7S-PASCON) algorithm enhances data processing, security, and performance. 7S-PASCON’s power efficiency is 2.5 times higher, throughput is 7 times higher, and latency is reduced to 31% for 100-MHz frequency than the standard Ascon. The proposed S-Box implementation uses a unified equation structure and reduces area usage by minimizing gate count and hardware resources. It has efficient resource utilization with a lookup table (LUT) efficiency of 14.39% and a flip-flop (FF) efficiency of 5.53% significantly better than existing works. The results demonstrate a tradeoff between resource utilization and potential performance enhancements compared to the nonpipelined version. The 7S-PASCON is beneficial for secure communication in IoT networks, wireless sensor networks, and defense systems.
{"title":"7-Stage Pipelined Architecture of ASCON for Resource Constraint Devices","authors":"A. J. Bhuvaneshwari;P. Kaythry;K. J. Jegadish Kumar;D. Sachin","doi":"10.1109/LES.2025.3541818","DOIUrl":"https://doi.org/10.1109/LES.2025.3541818","url":null,"abstract":"Ascon is an intended lightweight algorithm designed to deliver efficiency and security for resource-constrained Internet of Things (IoT) devices. This letter presents a field-programmable gate array (FPGA) implementation of the pipelined architecture of Ascon for rapid execution. The objective is to optimize the datapath to achieve high throughput while maintaining a minimal hardware footprint. The proposed 7-stage pipelined Ascon (7S-PASCON) algorithm enhances data processing, security, and performance. 7S-PASCON’s power efficiency is 2.5 times higher, throughput is 7 times higher, and latency is reduced to 31% for 100-MHz frequency than the standard Ascon. The proposed S-Box implementation uses a unified equation structure and reduces area usage by minimizing gate count and hardware resources. It has efficient resource utilization with a lookup table (LUT) efficiency of 14.39% and a flip-flop (FF) efficiency of 5.53% significantly better than existing works. The results demonstrate a tradeoff between resource utilization and potential performance enhancements compared to the nonpipelined version. The 7S-PASCON is beneficial for secure communication in IoT networks, wireless sensor networks, and defense systems.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"17 4","pages":"252-255"},"PeriodicalIF":2.0,"publicationDate":"2025-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144843064","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-02-11DOI: 10.1109/LES.2025.3541130
Cruz F. López Olvera;Diego A. Flores-Hernández
The legged robots have a better performance than the wheeled and tracked mobile robots for some applications. The development of quadruped robots (QRs) has increased in the last years mainly with the mammalian configuration due to the velocity of displacement and for the implementation of new control strategies that improve its stability. However, it is necessary to integrate embedded systems into the QR design to increase the overall performance. The proposed research presents the development of an integrated system composed of a QR in mammalian configuration and an embedded system with a concurrent methodology that ensures harmonic integration. The system was tested under real environments, on flat, sandy, and rocky terrains. The experimental results were analyzed with Kinovea software, obtaining a maximum velocity in the flat terrain with 0.43 and 0.2 m/s in sandy terrain, and 0.345 m/s in rocky. Finally, an embedded system is a factor key to improving the QR’s performance because it allows for modification of the behavior through the implementation of unconventional control strategies, to make the robot smaller, and it is possible to integrate tools of IoT that are necessary for the new applications.
{"title":"Embedded System for Quadruped Robot in Mammalian Configuration","authors":"Cruz F. López Olvera;Diego A. Flores-Hernández","doi":"10.1109/LES.2025.3541130","DOIUrl":"https://doi.org/10.1109/LES.2025.3541130","url":null,"abstract":"The legged robots have a better performance than the wheeled and tracked mobile robots for some applications. The development of quadruped robots (QRs) has increased in the last years mainly with the mammalian configuration due to the velocity of displacement and for the implementation of new control strategies that improve its stability. However, it is necessary to integrate embedded systems into the QR design to increase the overall performance. The proposed research presents the development of an integrated system composed of a QR in mammalian configuration and an embedded system with a concurrent methodology that ensures harmonic integration. The system was tested under real environments, on flat, sandy, and rocky terrains. The experimental results were analyzed with Kinovea software, obtaining a maximum velocity in the flat terrain with 0.43 and 0.2 m/s in sandy terrain, and 0.345 m/s in rocky. Finally, an embedded system is a factor key to improving the QR’s performance because it allows for modification of the behavior through the implementation of unconventional control strategies, to make the robot smaller, and it is possible to integrate tools of IoT that are necessary for the new applications.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"17 6","pages":"378-381"},"PeriodicalIF":2.0,"publicationDate":"2025-02-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145760887","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-02-11DOI: 10.1109/LES.2025.3540704
Brandon Pineda;Juan G. Avalos;Giovanny Sánchez;Eduardo Vázquez;Juan C. Sánchez;Ángel A. Vázquez
Recently, various active noise control (ANC) systems have been developed to attenuate unwanted signals within airplane cabins. Most of these works use the filtered-x least mean squares (FxLMS) algorithm due to its low computational cost, however its convergence speed is slow. To overcome this, several variations of the LMS algorithm have been developed to offer better convergence properties, such as affine projection algorithms and recent cutting-edge methods based on the q-gradient concept. Here, we present for the first time, a new affine projection algorithm based on the q-gradient, and the design of an ANC system applied to headrests of airplane seats. To evaluate the effectiveness of the proposal, we perform tests inside a Boeing 727-200 airplane cabin. The results demonstrate that the proposed algorithm achieves faster convergence speed than the conventional version, and its practical implementation shows good performance in attenuating noise signals within an airplane.
近年来，各种主动噪声控制（ANC）系统被开发出来，以衰减飞机机舱内的有害信号。这些研究大多采用滤波-x最小均方（filter -x least mean squares, FxLMS）算法，由于其计算成本较低，但收敛速度较慢。为了克服这个问题，LMS算法的几种变体已经被开发出来，以提供更好的收敛特性，例如仿射投影算法和基于q梯度概念的最新前沿方法。本文首次提出了一种新的基于q梯度的仿射投影算法，并设计了一种应用于飞机座椅头枕的ANC系统。为了评估该建议的有效性，我们在波音727-200飞机机舱内进行了测试。结果表明，该算法的收敛速度比传统算法快，并且在实际应用中对飞机内的噪声信号有较好的衰减效果。
{"title":"A New Fast Convergence Speed q-APL Algorithm for Active Noise Control Applied to Airplane Seats","authors":"Brandon Pineda;Juan G. Avalos;Giovanny Sánchez;Eduardo Vázquez;Juan C. Sánchez;Ángel A. Vázquez","doi":"10.1109/LES.2025.3540704","DOIUrl":"https://doi.org/10.1109/LES.2025.3540704","url":null,"abstract":"Recently, various active noise control (ANC) systems have been developed to attenuate unwanted signals within airplane cabins. Most of these works use the filtered-x least mean squares (FxLMS) algorithm due to its low computational cost, however its convergence speed is slow. To overcome this, several variations of the LMS algorithm have been developed to offer better convergence properties, such as affine projection algorithms and recent cutting-edge methods based on the q-gradient concept. Here, we present for the first time, a new affine projection algorithm based on the q-gradient, and the design of an ANC system applied to headrests of airplane seats. To evaluate the effectiveness of the proposal, we perform tests inside a Boeing 727-200 airplane cabin. The results demonstrate that the proposed algorithm achieves faster convergence speed than the conventional version, and its practical implementation shows good performance in attenuating noise signals within an airplane.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"17 6","pages":"382-385"},"PeriodicalIF":2.0,"publicationDate":"2025-02-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145778463","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Achieving peak performance is a primary goal for athletes, and understanding progress is essential for this pursuit. Jump tests are a reliable method for evaluating athletic performance. This study presents an embedded system that leverages the cutting-edge technology present in the SensorTile STEVAL-STLCS01V1 sensor to provide accurate measurements of key performance indicators, such as jump height, power, and reaction time. We propose a wearable technology solution that seamlessly tracks and analyzes these metrics, offering evaluators valuable insights into an athlete’s development. A data collection protocol was implemented involving 22 participants, and the results show that the system’s measurements exhibit a consistent bias relative to the gold standard. A minor bias correction would allow the system to achieve both higher accuracy and precision, demonstrating its potential for practical use in athletic training.
{"title":"Embedded System for Athletes’ Jump Performance Analysis","authors":"Jeremías Gaia;Eugenio Orosco;Lucas Trigo;Marcos Toibero","doi":"10.1109/LES.2025.3539009","DOIUrl":"https://doi.org/10.1109/LES.2025.3539009","url":null,"abstract":"Achieving peak performance is a primary goal for athletes, and understanding progress is essential for this pursuit. Jump tests are a reliable method for evaluating athletic performance. This study presents an embedded system that leverages the cutting-edge technology present in the SensorTile STEVAL-STLCS01V1 sensor to provide accurate measurements of key performance indicators, such as jump height, power, and reaction time. We propose a wearable technology solution that seamlessly tracks and analyzes these metrics, offering evaluators valuable insights into an athlete’s development. A data collection protocol was implemented involving 22 participants, and the results show that the system’s measurements exhibit a consistent bias relative to the gold standard. A minor bias correction would allow the system to achieve both higher accuracy and precision, demonstrating its potential for practical use in athletic training.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"17 6","pages":"374-377"},"PeriodicalIF":2.0,"publicationDate":"2025-02-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145778169","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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