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Hardware-Aware Bayesian Neural Architecture Search of Quantized CNNs 量化 CNN 的硬件感知贝叶斯神经架构搜索
IF 1.6 4区 计算机科学 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE Pub Date : 2024-07-26 DOI: 10.1109/les.2024.3434379
Mathieu Perrin, William Guicquero, Bruno Paille, Gilles Sicard
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引用次数: 0
An Endogenous Security Study of Telematics Box in Intelligent Connected Vehicles 智能网联汽车车载信息箱的内生安全研究
IF 1.7 4区 计算机科学 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE Pub Date : 2024-07-23 DOI: 10.1109/LES.2024.3432593
Zhen Zhang;Yuezhong Zhang;Jinfeng Zhang;Jichao Xie;Shaoxun Liu
Intelligent connected vehicles (ICVs) are the result of technological advancements in the new era, greatly enhancing the driving experience. However, due to the complex nature of the system, the intelligence of devices, and the connectivity of data, a complex physical fusion system has been created. The in-vehicle Telematics Box (T-Box), serving as the central communication and data hub, faces challenges, such as network vulnerabilities, data privacy, and malicious attacks through untrusted software updates. Therefore, an in-vehicle T-Box with high reliability, security, and performance is an urgent product in the era of the Internet of Vehicles. This article investigates the endogenous security of the T-Box in ICV, with a focus on the integration of dynamic heterogeneous redundancy (DHR) architecture. The underlying idea is to transform the original system into multiple heterogeneous systems, where some of them handle the same business functions. By applying a consensus mechanism to detect malicious nodes and dynamically scheduling healthy nodes into the working mode, a self-purifying defense system with intrinsic security is formed. This design approach endows the T-Box with inherent defense capabilities against unknown vulnerabilities. Meanwhile, the in-vehicle T-Box is redesigned in the software and hardware implementation scheme. Experimental results demonstrate that the new design notably enhances and ensures the robust stability and elevated reliability of the in-vehicle T-Box. Evidently, the upgraded T-Box ensures the safe processing of in-vehicle CAN bus data.
智能网联汽车(ICVs)是新时代技术进步的结果,极大地提高了驾驶体验。然而,由于系统的复杂性、设备的智能化和数据的连通性,形成了一个复杂的物理融合系统。作为中央通信和数据集线器的车载远程信息处理箱(T-Box)面临着网络漏洞、数据隐私以及通过不受信任的软件更新进行恶意攻击等挑战。因此,高可靠性、高安全性、高性能的车载T-Box是车联网时代急需的产品。本文研究了ICV中T-Box的内生性安全性,重点研究了动态异构冗余(DHR)架构的集成。其基本思想是将原始系统转换为多个异构系统,其中一些系统处理相同的业务功能。采用共识机制检测恶意节点,动态调度健康节点进入工作模式,形成具有内在安全性的自净化防御系统。这种设计方法赋予T-Box针对未知漏洞的固有防御能力。同时,对车载T-Box进行了软硬件实现方案的重新设计。实验结果表明,新设计显著增强和保证了车载T-Box的鲁棒稳定性和高可靠性。显然,升级后的T-Box确保了车载CAN总线数据的安全处理。
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引用次数: 0
Analysis of Outdoor Air Quality Using Low-Cost MEMS-Based Electronic Nose and Gas Analyzer 利用低成本 MEMS 电子鼻和气体分析仪分析室外空气质量
IF 1.6 4区 计算机科学 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE Pub Date : 2024-07-18 DOI: 10.1109/les.2024.3431214
Tushar Gawande, Raghavendra Deshmukh, Sharvari Deshmukh
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引用次数: 0
A Co-Optimization of Software and Hardware for PCIe-Based Small Packet DMA Transfer 基于 PCIe 的小数据包 DMA 传输的软硬件协同优化
IF 1.6 4区 计算机科学 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE Pub Date : 2024-07-17 DOI: 10.1109/les.2024.3429544
Xiaotian Gu, Lisong Shao, Ningfeng Bai, Guosheng Zhang, Xinyi Zhang
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引用次数: 0
Securing Binarized Neural Networks via PUF-Based Key Management in Memristive Crossbar Arrays 通过 Memristive Crossbar 阵列中基于 PUF 的密钥管理确保二值化神经网络的安全
IF 1.6 4区 计算机科学 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE Pub Date : 2024-07-02 DOI: 10.1109/les.2024.3422294
Gokulnath Rajendran, Debajit Basak, Suman Deb, Anupam Chattopadhyay
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引用次数: 0
A Dependable and Low-Cost CCSDS 123 Hyperspectral Image Compressor 可靠、低成本的 CCSDS 123 高光谱图像压缩器
IF 1.6 4区 计算机科学 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE Pub Date : 2024-07-01 DOI: 10.1109/les.2024.3420934
Wesley Grignani, Douglas A. Santos, Felipe Viel, Luigi Dilillo, Douglas R. Melo
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引用次数: 0
Boosting AES Intrinsic Resilience Using Split SubBytes Round Function Against Power Attacks 利用分拆子字节轮函数提升 AES 固有弹性,抵御功率攻击
IF 1.6 4区 计算机科学 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE Pub Date : 2024-06-27 DOI: 10.1109/les.2024.3420226
Vishnu Padmakumar, Titu Mary Ignatius, Thockchom Birjit Singha, Roy Paily Palathinkal, Shaik Rafi Ahamed
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引用次数: 0
Software Implementation of Fast List Decoder for PAC Codes PAC 码快速列表解码器的软件实现
IF 1.6 4区 计算机科学 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE Pub Date : 2024-06-20 DOI: 10.1109/les.2024.3417413
Hang Yin, Jingxin Dai, Yansong Lv, Yuhuan Wang, Rui Lv
{"title":"Software Implementation of Fast List Decoder for PAC Codes","authors":"Hang Yin, Jingxin Dai, Yansong Lv, Yuhuan Wang, Rui Lv","doi":"10.1109/les.2024.3417413","DOIUrl":"https://doi.org/10.1109/les.2024.3417413","url":null,"abstract":"","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"18 1","pages":""},"PeriodicalIF":1.6,"publicationDate":"2024-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141508766","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Functional Validation of the RISC-V Unlimited Vector Extension RISC-V 无限矢量扩展的功能验证
IF 1.6 4区 计算机科学 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE Pub Date : 2024-06-19 DOI: 10.1109/les.2024.3416820
Ana Fernandes, Luís Crespo, Nuno Neves, Pedro Tomás, Nuno Roma, Gabriel Falcao
{"title":"Functional Validation of the RISC-V Unlimited Vector Extension","authors":"Ana Fernandes, Luís Crespo, Nuno Neves, Pedro Tomás, Nuno Roma, Gabriel Falcao","doi":"10.1109/les.2024.3416820","DOIUrl":"https://doi.org/10.1109/les.2024.3416820","url":null,"abstract":"","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"5 1","pages":""},"PeriodicalIF":1.6,"publicationDate":"2024-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141937440","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
M-HLS: Malevolent High-Level Synthesis for Watermarked Hardware IPs M-HLS:针对带水印硬件 IP 的恶意高级合成
IF 1.7 4区 计算机科学 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE Pub Date : 2024-06-19 DOI: 10.1109/LES.2024.3416422
Anirban Sengupta;Aditya Anshul;Vishal Chourasia;Nitish Kumar
Hardware Trojan insertion in high-level synthesis (HLS) generated intellectual property (IP) designs can pose strong security concern for the designers. Backdoor hardware Trojans can be inserted in the HLS design flow to compromise the produced register transfer level (RTL) IP design. This letter presents a novel malevolent HLS (M-HLS) framework introducing the possibility of two different hardware Trojan insertion [i.e., performance degradation hardware Trojan (PD-HT) and Denial of Service hardware Trojan (DoS-HT)] in multiplexer (mux)-based interconnect stage of HLS generated watermarked IP design. The proposed framework is validated on the watermarked MESA Horner Bezier’s IP, which indicates strong performance degradation and DoS achievable by an attacker at minimal area and power overhead.
在高级合成(HLS)生成的知识产权(IP)设计中插入硬件木马会给设计者带来严重的安全问题。后门硬件木马可以插入到HLS设计流程中,以破坏生成的寄存器传输级别(RTL) IP设计。本文提出了一种新的恶意HLS (M-HLS)框架,引入了两种不同硬件木马插入的可能性[即性能下降硬件木马(PD-HT)和拒绝服务硬件木马(DoS-HT)]在基于多路复用器(mux)的HLS生成水印IP设计的互连阶段。该框架在带有水印的MESA Horner Bezier IP上进行了验证,表明攻击者可以在最小的面积和功耗开销下实现较强的性能下降和DoS。
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引用次数: 0
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IEEE Embedded Systems Letters
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