Pub Date : 2025-03-21DOI: 10.1109/LES.2025.3572046
Maria C. Moreno;Fabian E. Casares;Juana Martinez;Emily R. Ellis;Oscar J. Suarez
Latin American agriculture encounters significant challenges, such as inefficient land use and vulnerability to climate change, with smallholder farmers being particularly affected. This letter proposes a modular Internet of Things (IoT)-based system that integrates embedded systems, environmental sensors, and artificial intelligence (AI) for real-time monitoring and adaptive control. The system utilizes a Raspberry Pi coupled with advanced sensors measuring temperature, humidity, potential of hydrogen (pH), liquid level, light intensity, air quality, and electrical current. Actuators regulate nutrient delivery in response to pH levels, while intelligent lighting systems enhance plant growth conditions. Remote monitoring facilitated by a vision-equipped camera system allows the detection of anomalies and the tracking of plant growth. Experimental results demonstrated temperature stability of ±1°C, humidity variation within ±5%, 92% accuracy in anomaly detection, and response times of less than 10 s.
{"title":"IoT-Driven Smart Embedded System for Efficient Quality Food Production in Controlled Environments","authors":"Maria C. Moreno;Fabian E. Casares;Juana Martinez;Emily R. Ellis;Oscar J. Suarez","doi":"10.1109/LES.2025.3572046","DOIUrl":"https://doi.org/10.1109/LES.2025.3572046","url":null,"abstract":"Latin American agriculture encounters significant challenges, such as inefficient land use and vulnerability to climate change, with smallholder farmers being particularly affected. This letter proposes a modular Internet of Things (IoT)-based system that integrates embedded systems, environmental sensors, and artificial intelligence (AI) for real-time monitoring and adaptive control. The system utilizes a Raspberry Pi coupled with advanced sensors measuring temperature, humidity, potential of hydrogen (pH), liquid level, light intensity, air quality, and electrical current. Actuators regulate nutrient delivery in response to pH levels, while intelligent lighting systems enhance plant growth conditions. Remote monitoring facilitated by a vision-equipped camera system allows the detection of anomalies and the tracking of plant growth. Experimental results demonstrated temperature stability of ±1°C, humidity variation within ±5%, 92% accuracy in anomaly detection, and response times of less than 10 s.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"17 6","pages":"411-414"},"PeriodicalIF":2.0,"publicationDate":"2025-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145778237","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-19DOI: 10.1109/LES.2025.3571040
Sourav Roy;Nikhil Jain;Neha Srivastava;Ravinder Dasila;Prokash Ghosh;Ajay Sharma;Afshan Anjum;Jeff Scott
With the advent of modular and independent zonal processing in Software-Defined-Vehicles (SDV), the processor in an automotive system is expected to handle complex exception scenarios elegantly. This letter addresses the need for comprehensive exception coverage during the verification of the automotive processor. Unlike prior research focusing on only two simultaneous exceptions, our work extends to all combinations of simultaneous exceptions. The proposed methodology involves the systematic grouping of exceptions into subcategories based on similarity while maintaining priority, followed by targeted coverage assessment for each group. A two-pass simulation technique is used to drive multiple external events like interrupts in the second pass to create high-activity time windows with simultaneous exceptions. This hierarchical approach allows for the creation of a manageable and effective exception list, facilitating thorough verification without overwhelming computational resources. Applied to a 32-bit RISC-V processor, our methodology shows a large improvement of 7X in efficiency compared to traditional methods, highlighting its advantage in enhancing safety and trustworthiness of automotive systems. This work takes a major step toward the verification of all combinations of simultaneous exceptions in processors.
{"title":"Exception Coverage on Automotive Processors","authors":"Sourav Roy;Nikhil Jain;Neha Srivastava;Ravinder Dasila;Prokash Ghosh;Ajay Sharma;Afshan Anjum;Jeff Scott","doi":"10.1109/LES.2025.3571040","DOIUrl":"https://doi.org/10.1109/LES.2025.3571040","url":null,"abstract":"With the advent of modular and independent zonal processing in Software-Defined-Vehicles (SDV), the processor in an automotive system is expected to handle complex exception scenarios elegantly. This letter addresses the need for comprehensive exception coverage during the verification of the automotive processor. Unlike prior research focusing on only two simultaneous exceptions, our work extends to all combinations of simultaneous exceptions. The proposed methodology involves the systematic grouping of exceptions into subcategories based on similarity while maintaining priority, followed by targeted coverage assessment for each group. A two-pass simulation technique is used to drive multiple external events like interrupts in the second pass to create high-activity time windows with simultaneous exceptions. This hierarchical approach allows for the creation of a manageable and effective exception list, facilitating thorough verification without overwhelming computational resources. Applied to a 32-bit RISC-V processor, our methodology shows a large improvement of 7X in efficiency compared to traditional methods, highlighting its advantage in enhancing safety and trustworthiness of automotive systems. This work takes a major step toward the verification of all combinations of simultaneous exceptions in processors.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"18 1","pages":"27-30"},"PeriodicalIF":2.0,"publicationDate":"2025-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146162232","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-19DOI: 10.1109/LES.2025.3571323
Luis Alejandro Pérez-Sarmiento;Cuauhtemoc Mancillas-López
Message authentication codes (MACs) and authentication encryption algorithms (AEs) are widely used cryptographic primitives. Offset codebook (OCB), OCB random access (OCBRA), PMACRA, and EliMAC are cryptographic schemes based on AES and reduced-round AES. This letter compares the schemes mentioned in a 32-bit ARM microcontroller. For efficiency, we implemented the AES round using a fixslicing technique, which processes two blocks in parallel. Such characteristics are essential when the schemes allow parallelization between the AES calls. OCB and OCBRA were compared for authentication and encryption. OCBRA and EliMAC obtain similar performance for authentication, while OCB needs more clock cycles due to its initialization process. For encryption, OCBRA and OCB were practically identical.
{"title":"Performance of Some AES-Based AE and MAC Schemes Using Fixslicing on STM32 Microcontrollers","authors":"Luis Alejandro Pérez-Sarmiento;Cuauhtemoc Mancillas-López","doi":"10.1109/LES.2025.3571323","DOIUrl":"https://doi.org/10.1109/LES.2025.3571323","url":null,"abstract":"Message authentication codes (MACs) and authentication encryption algorithms (AEs) are widely used cryptographic primitives. Offset codebook (OCB), OCB random access (OCBRA), PMACRA, and EliMAC are cryptographic schemes based on AES and reduced-round AES. This letter compares the schemes mentioned in a 32-bit ARM microcontroller. For efficiency, we implemented the AES round using a fixslicing technique, which processes two blocks in parallel. Such characteristics are essential when the schemes allow parallelization between the AES calls. OCB and OCBRA were compared for authentication and encryption. OCBRA and EliMAC obtain similar performance for authentication, while OCB needs more clock cycles due to its initialization process. For encryption, OCBRA and OCB were practically identical.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"17 6","pages":"394-397"},"PeriodicalIF":2.0,"publicationDate":"2025-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11006872","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145778313","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-17DOI: 10.1109/LES.2025.3551734
Jangwon Lee;Jiwon Yoo;Dami Ko;Gyeonghwan Kim
Gaze estimation is a commonly used task in human-computer interaction, with its applications ranging from driver monitoring systems to human assistive technologies. However, achieving robust, real-time performance on edge devices remains a challenge due to limited computational resources and the need for high energy efficiency. In this letter, we present a novel gaze estimation model optimized for NVIDIA Jetson platforms, leveraging the unique capabilities of deep learning accelerators (DLAs) for enhanced efficiency. Our model includes a calibration module designed for DLA execution, incorporating convolutional spatial and channel attention to improve robustness after face detection stage. By strategically distributing computational tasks across GPU and DLA, our approach achieves up to an 88% increase in energy efficiency compared to a system without calibration module, making it well suited for real-time, edge-based applications in resource-constrained environments.
{"title":"Optimizing Gaze Estimation With a DLA-Based Calibration Module on NVIDIA Jetson Platforms","authors":"Jangwon Lee;Jiwon Yoo;Dami Ko;Gyeonghwan Kim","doi":"10.1109/LES.2025.3551734","DOIUrl":"https://doi.org/10.1109/LES.2025.3551734","url":null,"abstract":"Gaze estimation is a commonly used task in human-computer interaction, with its applications ranging from driver monitoring systems to human assistive technologies. However, achieving robust, real-time performance on edge devices remains a challenge due to limited computational resources and the need for high energy efficiency. In this letter, we present a novel gaze estimation model optimized for NVIDIA Jetson platforms, leveraging the unique capabilities of deep learning accelerators (DLAs) for enhanced efficiency. Our model includes a calibration module designed for DLA execution, incorporating convolutional spatial and channel attention to improve robustness after face detection stage. By strategically distributing computational tasks across GPU and DLA, our approach achieves up to an 88% increase in energy efficiency compared to a system without calibration module, making it well suited for real-time, edge-based applications in resource-constrained environments.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"18 1","pages":"56-59"},"PeriodicalIF":2.0,"publicationDate":"2025-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146162244","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-11DOI: 10.1109/LES.2025.3550171
S. Shakeera;N. Sreyas;V. B. N. Jyothi;H. Venkataraman
Accurate navigation in global positioning system (GPS) denied environments, such as tunnels, rural areas and underwater regions is a critical challenge for autonomous vehicles (AVs). Traditional position estimation methods face challenges due to their computational complexity and inability to consider external factors like sensor drift and human input errors. This letter introduces a global-local–global (GLG) position estimation method that integrates advanced inertial sensors with navigation sensors, utilizing kalman filter (KF) and extended KF (EKF) to enhance trajectory accuracy. The proposed mechanism is validated through analysis and real-time tests using custom-built hardware in terrestrial and underwater environments. It demonstrates effectiveness during GPS outages lasting 5–60 s, achieving position drifts of 2.84 m for GLG, 1.35 m for GLG + KF, and 1.27 m for GLG + EKF over a total distance travelled of 1.1 km. This method is particularly suited for short-range applications, including aqua farming, tunnel navigation, and dense areas, providing a robust solution for accurate position estimation in challenging scenarios.
{"title":"Navigating the Future: A Kalman Filter-Based Global-Local-Global (GLG) Position Estimation for Autonomous Vehicles in GPS Denied Environments","authors":"S. Shakeera;N. Sreyas;V. B. N. Jyothi;H. Venkataraman","doi":"10.1109/LES.2025.3550171","DOIUrl":"https://doi.org/10.1109/LES.2025.3550171","url":null,"abstract":"Accurate navigation in global positioning system (GPS) denied environments, such as tunnels, rural areas and underwater regions is a critical challenge for autonomous vehicles (AVs). Traditional position estimation methods face challenges due to their computational complexity and inability to consider external factors like sensor drift and human input errors. This letter introduces a global-local–global (GLG) position estimation method that integrates advanced inertial sensors with navigation sensors, utilizing kalman filter (KF) and extended KF (EKF) to enhance trajectory accuracy. The proposed mechanism is validated through analysis and real-time tests using custom-built hardware in terrestrial and underwater environments. It demonstrates effectiveness during GPS outages lasting 5–60 s, achieving position drifts of 2.84 m for GLG, 1.35 m for GLG + KF, and 1.27 m for GLG + EKF over a total distance travelled of 1.1 km. This method is particularly suited for short-range applications, including aqua farming, tunnel navigation, and dense areas, providing a robust solution for accurate position estimation in challenging scenarios.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"18 1","pages":"77-80"},"PeriodicalIF":2.0,"publicationDate":"2025-03-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146162228","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-11DOI: 10.1109/LES.2025.3550393
Sadan Saquib Khan;Pratyush Kumar Padhi;Shufali Ashraf Wani;Meraj Ahmad;Laxmeesha Somappa;Shahid Malik
Optical sensors play a critical role in biomedical monitoring systems, enabling noninvasive measurement of physiological parameters. However, these systems face a persistent challenge: the small amplitude of physiological signals is often overshadowed by a dominant DC offset current. This offset combines the dark current, ambient light, and reflections from fat and skull. This limits the amplification of signals and degrades the sensitivity of PPG/fNIRS systems. This letter presents a mixed-signal auto-calibrated offset compensation technique using dual discrete loops for PPG and fNIRS systems. Two specialized prototypes—a dedicated PPG system and an fNIRS system—were validated using a 3.3 V supply. The results show that the proposed system can effectively compensate for the offset currents within a range of 1 to $100~mu $ A. We have recorded PPG and fNIRS signals and performed breathing experiments to validate the results. The results show that the proposed system is able to record the signal accurately.
{"title":"An Embedded Auto-Calibrated Offset Current Compensation Technique for PPG/fNIRS System","authors":"Sadan Saquib Khan;Pratyush Kumar Padhi;Shufali Ashraf Wani;Meraj Ahmad;Laxmeesha Somappa;Shahid Malik","doi":"10.1109/LES.2025.3550393","DOIUrl":"https://doi.org/10.1109/LES.2025.3550393","url":null,"abstract":"Optical sensors play a critical role in biomedical monitoring systems, enabling noninvasive measurement of physiological parameters. However, these systems face a persistent challenge: the small amplitude of physiological signals is often overshadowed by a dominant DC offset current. This offset combines the dark current, ambient light, and reflections from fat and skull. This limits the amplification of signals and degrades the sensitivity of PPG/fNIRS systems. This letter presents a mixed-signal auto-calibrated offset compensation technique using dual discrete loops for PPG and fNIRS systems. Two specialized prototypes—a dedicated PPG system and an fNIRS system—were validated using a 3.3 V supply. The results show that the proposed system can effectively compensate for the offset currents within a range of 1 to <inline-formula> <tex-math>$100~mu $ </tex-math></inline-formula> A. We have recorded PPG and fNIRS signals and performed breathing experiments to validate the results. The results show that the proposed system is able to record the signal accurately.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"18 1","pages":"60-63"},"PeriodicalIF":2.0,"publicationDate":"2025-03-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146162248","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-07DOI: 10.1109/LES.2025.3567918
Yanze Wu;Md Tanvir Arafin
Kolmogorov–Arnold networks (KANs) are promising for explainable machine learning (ML) on embedded devices. Although KANs require fewer model parameters and are smaller than traditional deep neural networks, their applicability is limited by the complexity of the basis-spline (B-spline) functions used at every neuron. Hence, this letter presents acceleration techniques for KANs on dataflow-processing-based accelerators implemented in AMD-Xilinx Versal adaptive system on chips. Our experiments on the VCK-190 devices demonstrate that for large batch sizes, the average B-spline computation on systolic and wavefront architectures outperforms standard CPU implementation by $11times $ and $60times $ . On the other hand, wavefront accelerators demonstrate more than $3times $ improvement over GPUs (RTX 3090) in terms of energy consumption. Thus, this letter opens new opportunities for spatial accelerators in nonconventional ML algorithms on embedded systems. This letter’s code and experimental artifacts are available at https://github.com/SPIRE-GMU/SPIRE-ARKANE.
{"title":"ArKANe: Accelerating Kolmogorov–Arnold Networks on Reconfigurable Spatial Architectures","authors":"Yanze Wu;Md Tanvir Arafin","doi":"10.1109/LES.2025.3567918","DOIUrl":"https://doi.org/10.1109/LES.2025.3567918","url":null,"abstract":"Kolmogorov–Arnold networks (KANs) are promising for explainable machine learning (ML) on embedded devices. Although KANs require fewer model parameters and are smaller than traditional deep neural networks, their applicability is limited by the complexity of the basis-spline (B-spline) functions used at every neuron. Hence, this letter presents acceleration techniques for KANs on dataflow-processing-based accelerators implemented in AMD-Xilinx Versal adaptive system on chips. Our experiments on the VCK-190 devices demonstrate that for large batch sizes, the average B-spline computation on systolic and wavefront architectures outperforms standard CPU implementation by <inline-formula> <tex-math>$11times $ </tex-math></inline-formula> and <inline-formula> <tex-math>$60times $ </tex-math></inline-formula>. On the other hand, wavefront accelerators demonstrate more than <inline-formula> <tex-math>$3times $ </tex-math></inline-formula> improvement over GPUs (RTX 3090) in terms of energy consumption. Thus, this letter opens new opportunities for spatial accelerators in nonconventional ML algorithms on embedded systems. This letter’s code and experimental artifacts are available at <uri>https://github.com/SPIRE-GMU/SPIRE-ARKANE</uri>.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"18 1","pages":"44-47"},"PeriodicalIF":2.0,"publicationDate":"2025-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146162229","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The widespread adoption of 32-bit and 64-bit processors and ample memory resources in modern embedded systems has led to designs that prioritize performance and functionality over die area. This abundance has resulted in solutions that may not be optimal for applications where power and resource conservation are critical. To address this oversight, we introduce hyper-embedded computing, a paradigm that reinvigorates minimalistic embedded system design by integrating sophisticated multiprocessing capabilities into ultracompact embedded architectures with fixed silicon configurations. This approach is particularly well-suited for mission-critical, area-constrained applications that demand long-term reliability and sustainability. We build on this concept with the Turbo9, a 16-bit microprocessor optimized for minimal logic area, and TurbOS, a real-time embedded operating system that delivers UNIX-like features within a constrained memory area. TurbOS features a modular architecture, a preemptive multitasking kernel, a unified input/output architecture, and efficient memory utilization. Compared to currently used microprocessors and real-time operating systems, our approach achieves similar functionality while reducing memory area by approximately 75%, making it an ideal choice for sustainable and high-reliability embedded applications.
{"title":"Hyper-Embedded Computing: An Optimized System Architecture for Area-Constrained Applications","authors":"Boisy Gene Pitre;Martin Margala;Kevin Phillipson;Michael Rywalt","doi":"10.1109/LES.2025.3548955","DOIUrl":"https://doi.org/10.1109/LES.2025.3548955","url":null,"abstract":"The widespread adoption of 32-bit and 64-bit processors and ample memory resources in modern embedded systems has led to designs that prioritize performance and functionality over die area. This abundance has resulted in solutions that may not be optimal for applications where power and resource conservation are critical. To address this oversight, we introduce hyper-embedded computing, a paradigm that reinvigorates minimalistic embedded system design by integrating sophisticated multiprocessing capabilities into ultracompact embedded architectures with fixed silicon configurations. This approach is particularly well-suited for mission-critical, area-constrained applications that demand long-term reliability and sustainability. We build on this concept with the Turbo9, a 16-bit microprocessor optimized for minimal logic area, and TurbOS, a real-time embedded operating system that delivers UNIX-like features within a constrained memory area. TurbOS features a modular architecture, a preemptive multitasking kernel, a unified input/output architecture, and efficient memory utilization. Compared to currently used microprocessors and real-time operating systems, our approach achieves similar functionality while reducing memory area by approximately 75%, making it an ideal choice for sustainable and high-reliability embedded applications.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"17 6","pages":"435-438"},"PeriodicalIF":2.0,"publicationDate":"2025-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145778292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
True random number generator (TRNG) is widely used in the field of hardware security as a key component that can enhance system security. In this letter, a TRNG with multiple entropy sources is proposed based on random telegraph noise (RTN) and ring oscillator (RO) jitter. The proposed TRNG utilizes a direct digital synthesizer (DDS) to realize the phase control and frequency control for generating random sequences, which is implemented on field programmable gate array (FPGA). By using the NIST randomness test suite, the resilience and randomness characteristics are verified with the compact cell design of four RO and one RTN source. Moreover, the proposed TRNG achieves random sequence output with a maximum frequency of 200 MHz and low energy consumption of 5 pJ/bit. Our findings may provide great potential for developing high-performance and security hardware devices and systems.
{"title":"High-Speed True Random Number Generator With Multiple Entropy Sources: Ring Oscillator Jitter and Random Telegraph Noise","authors":"Yizhi Liu;Yifan Wu;Bo Chen;Pengpeng Sang;Jixuan Wu;Xiangye Wei;Xuepeng Zhan;Jiezhi Chen","doi":"10.1109/LES.2025.3549110","DOIUrl":"https://doi.org/10.1109/LES.2025.3549110","url":null,"abstract":"True random number generator (TRNG) is widely used in the field of hardware security as a key component that can enhance system security. In this letter, a TRNG with multiple entropy sources is proposed based on random telegraph noise (RTN) and ring oscillator (RO) jitter. The proposed TRNG utilizes a direct digital synthesizer (DDS) to realize the phase control and frequency control for generating random sequences, which is implemented on field programmable gate array (FPGA). By using the NIST randomness test suite, the resilience and randomness characteristics are verified with the compact cell design of four RO and one RTN source. Moreover, the proposed TRNG achieves random sequence output with a maximum frequency of 200 MHz and low energy consumption of 5 pJ/bit. Our findings may provide great potential for developing high-performance and security hardware devices and systems.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"18 1","pages":"48-51"},"PeriodicalIF":2.0,"publicationDate":"2025-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146162218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-03-06DOI: 10.1109/LES.2025.3567317
Titu Mary Ignatius;Roy Paily Palathinkal
The growth of IoT across industries, has made secure communication crucial, especially in resource-limited, power-constrained SoCs. The major contributions of this work are the design of an area and power efficient cryptographic RISC-V SoC by integrating AES hardware accelerator IP with RISC-V, and the development of a secure cryptographic RISC-V SoC using the random clock self complementary (RCSC) countermeasure against power analysis attack (PAA). RCSC enhances security by introducing amplitude and timing variability through complementary operations on random numbers and utilizing variable number of clock cycles per encryption. The design is tested and power traces for PAA were generated on both ASIC and FPGA platforms. The design achieves minimal power overhead of 0.407%and hardware costs of 7.33%, with strong resilience to PAA. It is evidenced by an MTD greater than one million, SNR below 0.5, MI in milli-range, and TVLA within +/-4.5, allowing the SoC to withstand attacks with over one million power traces.
{"title":"Securing RISC-V SoC With Random Clock Self Complementary Countermeasure","authors":"Titu Mary Ignatius;Roy Paily Palathinkal","doi":"10.1109/LES.2025.3567317","DOIUrl":"https://doi.org/10.1109/LES.2025.3567317","url":null,"abstract":"The growth of IoT across industries, has made secure communication crucial, especially in resource-limited, power-constrained SoCs. The major contributions of this work are the design of an area and power efficient cryptographic RISC-V SoC by integrating AES hardware accelerator IP with RISC-V, and the development of a secure cryptographic RISC-V SoC using the random clock self complementary (RCSC) countermeasure against power analysis attack (PAA). RCSC enhances security by introducing amplitude and timing variability through complementary operations on random numbers and utilizing variable number of clock cycles per encryption. The design is tested and power traces for PAA were generated on both ASIC and FPGA platforms. The design achieves minimal power overhead of 0.407%and hardware costs of 7.33%, with strong resilience to PAA. It is evidenced by an MTD greater than one million, SNR below 0.5, MI in milli-range, and TVLA within +/-4.5, allowing the SoC to withstand attacks with over one million power traces.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"18 1","pages":"52-55"},"PeriodicalIF":2.0,"publicationDate":"2025-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146162219","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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