Low density parity check code (LDPC) is the most popular error correction code (ECC) for current nand flash memory controllers. Next generation flash memory, such as triple-level cell (TLC) and quad-level cell (QLC) with a higher bit error rate, bring up the demand for superior ECC algorithms providing excellent performance and acceptable hardware overhead. This letter proposes turbo product code (TPC) as an alternative to LDPC by exploring embedding of a TPC engine into a solid-state drive (SSD) controller architecture. The implementation of this TPC engine uses 2-D error coding and applies the Bose-Chaudhuri–Hocquenghem (BCH) code in each dimension. The algorithm is further improved by flipping the dedicated bit matrix when the basic TPC decoding algorithm terminates with uncorrectable conditions. This bit-flipping enhanced TPC (BFE-TPC) module is finally integrated into a nonvolatile memory express (NVMe) SSD controller driving eight flash memory channels. This BFE-TPC module illustrates the potential of 2D-TPCs as a replacement for LDPCs due to its high throughput and low hardware overhead.
{"title":"An Embedded Module of Enhanced Turbo Product Code Algorithm","authors":"Jianjun Luo;Yifan Shen;Boming Huang;Michael Etzkorn;Hongqiang Chen;Cong Yu","doi":"10.1109/LES.2024.3464517","DOIUrl":"https://doi.org/10.1109/LES.2024.3464517","url":null,"abstract":"Low density parity check code (LDPC) is the most popular error correction code (ECC) for current nand flash memory controllers. Next generation flash memory, such as triple-level cell (TLC) and quad-level cell (QLC) with a higher bit error rate, bring up the demand for superior ECC algorithms providing excellent performance and acceptable hardware overhead. This letter proposes turbo product code (TPC) as an alternative to LDPC by exploring embedding of a TPC engine into a solid-state drive (SSD) controller architecture. The implementation of this TPC engine uses 2-D error coding and applies the Bose-Chaudhuri–Hocquenghem (BCH) code in each dimension. The algorithm is further improved by flipping the dedicated bit matrix when the basic TPC decoding algorithm terminates with uncorrectable conditions. This bit-flipping enhanced TPC (BFE-TPC) module is finally integrated into a nonvolatile memory express (NVMe) SSD controller driving eight flash memory channels. This BFE-TPC module illustrates the potential of 2D-TPCs as a replacement for LDPCs due to its high throughput and low hardware overhead.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"16 4","pages":"509-512"},"PeriodicalIF":1.7,"publicationDate":"2024-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142777726","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-17DOI: 10.1109/LES.2024.3462638
Subhrangshu Adhikary;Subhayu Dutta
Embedded intelligence is a challenging field in engineering given its resource-constrained environment which regular machine learning algorithms demand. Most embedded intelligence models are trained on a computer and then the learned parameters are transferred to the embedded devices to enable decision making. Although training the model within a microcontroller is possible, the state-of-the-art method requires further optimization. Moreover, federated learning (FL) is used in the state of the art to protect data privacy while training a deep learning model at edge level. Embedded learning models require memory enhancements to improve on-device FL. In this experiment, we have performed memory enhancement of gray wolf optimizer after finding it suitable for the purpose and implemented it to create edge-level, resource-efficient, data privacy preserving on-device federated training of embedded intelligence models. The performances are benchmarked on 13 open-sourced datasets showing a mean 10.8% accuracy enhancement.
{"title":"FedTinyWolf—A Memory Efficient Federated Embedded Learning Mechanism","authors":"Subhrangshu Adhikary;Subhayu Dutta","doi":"10.1109/LES.2024.3462638","DOIUrl":"10.1109/LES.2024.3462638","url":null,"abstract":"Embedded intelligence is a challenging field in engineering given its resource-constrained environment which regular machine learning algorithms demand. Most embedded intelligence models are trained on a computer and then the learned parameters are transferred to the embedded devices to enable decision making. Although training the model within a microcontroller is possible, the state-of-the-art method requires further optimization. Moreover, federated learning (FL) is used in the state of the art to protect data privacy while training a deep learning model at edge level. Embedded learning models require memory enhancements to improve on-device FL. In this experiment, we have performed memory enhancement of gray wolf optimizer after finding it suitable for the purpose and implemented it to create edge-level, resource-efficient, data privacy preserving on-device federated training of embedded intelligence models. The performances are benchmarked on 13 open-sourced datasets showing a mean 10.8% accuracy enhancement.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"16 4","pages":"513-516"},"PeriodicalIF":1.7,"publicationDate":"2024-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142263901","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-12DOI: 10.1109/LES.2024.3459730
Muayad J. Aljafar;Zain Ul Abideen;Adriaan Peetermans;Benedikt Gierlichs;Samuel Pagliarini
This letter presents a technique that enables very fine tunability of the frequency of ring oscillators (ROs). Multiple ROs with different numbers of tunable elements were designed and fabricated in a 65-nm CMOS technology. A tunable element consists of two inverters under different local layout effects (LLEs) and a multiplexer. LLEs impact the transient response of inverters deterministically and allow to establish a fine tunable mechanism even in the presence of large process variation. The entire RO is digital and its layout is standard-cell compatible. We demonstrate the tunability of multistage ROs with post-silicon measurements of oscillation frequencies in the range of 80–900 MHz and tuning steps of 90 kHz.
{"title":"SCALLER: Standard Cell Assembled and Local Layout Effect-Based Ring Oscillators","authors":"Muayad J. Aljafar;Zain Ul Abideen;Adriaan Peetermans;Benedikt Gierlichs;Samuel Pagliarini","doi":"10.1109/LES.2024.3459730","DOIUrl":"10.1109/LES.2024.3459730","url":null,"abstract":"This letter presents a technique that enables very fine tunability of the frequency of ring oscillators (ROs). Multiple ROs with different numbers of tunable elements were designed and fabricated in a 65-nm CMOS technology. A tunable element consists of two inverters under different local layout effects (LLEs) and a multiplexer. LLEs impact the transient response of inverters deterministically and allow to establish a fine tunable mechanism even in the presence of large process variation. The entire RO is digital and its layout is standard-cell compatible. We demonstrate the tunability of multistage ROs with post-silicon measurements of oscillation frequencies in the range of 80–900 MHz and tuning steps of 90 kHz.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"16 4","pages":"493-496"},"PeriodicalIF":1.7,"publicationDate":"2024-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142199415","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-28DOI: 10.1109/LES.2024.3450576
James Gerrans;R. Simon Sherratt
Javascript object notation (JSON) and extensible markup language (XML) are two data serialization methods that have been compared over many applications, including client-server transmission, Internet communication, and large-scale data storage. Due to the smaller file size, JSON is faster for transmitting data. However, XML is better for sending complex data structures. This letter compares the two data formats in the context of an embedded system, considering factors, such as time, memory, and power to identify efficient characteristics of each method. Programs for each format were written, optimized, and compared for the same dataset. The JSON file was found to be 24.7% smaller than the XML file. This led to a shorter program run-time and less power being consumed when reading and processing the file. However, the program to deserialize the XML file took up 16.7% less flash memory than its JSON counterpart. Overall, JSON was found to be a better choice for systems when collecting large amounts of data, requiring high speed communication, or running for an extended period between battery charges. However, XML is proposed for systems that have limited flash memory.
{"title":"Comparing XML and JSON Characteristics as Formats for Data Serialization Within Ultralow Power Embedded Systems","authors":"James Gerrans;R. Simon Sherratt","doi":"10.1109/LES.2024.3450576","DOIUrl":"10.1109/LES.2024.3450576","url":null,"abstract":"Javascript object notation (JSON) and extensible markup language (XML) are two data serialization methods that have been compared over many applications, including client-server transmission, Internet communication, and large-scale data storage. Due to the smaller file size, JSON is faster for transmitting data. However, XML is better for sending complex data structures. This letter compares the two data formats in the context of an embedded system, considering factors, such as time, memory, and power to identify efficient characteristics of each method. Programs for each format were written, optimized, and compared for the same dataset. The JSON file was found to be 24.7% smaller than the XML file. This led to a shorter program run-time and less power being consumed when reading and processing the file. However, the program to deserialize the XML file took up 16.7% less flash memory than its JSON counterpart. Overall, JSON was found to be a better choice for systems when collecting large amounts of data, requiring high speed communication, or running for an extended period between battery charges. However, XML is proposed for systems that have limited flash memory.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"16 4","pages":"489-492"},"PeriodicalIF":1.7,"publicationDate":"2024-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142199416","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-01DOI: 10.1109/les.2024.3436511
James R. Majok, Mohammed Abo-Zahhad, Koji Inoue, Mohammed S. Sayed
{"title":"Acceleration of an Optimized Kvazaar All Intra Prediction on Embedded Systems Based on the Directional Texture Complexity","authors":"James R. Majok, Mohammed Abo-Zahhad, Koji Inoue, Mohammed S. Sayed","doi":"10.1109/les.2024.3436511","DOIUrl":"https://doi.org/10.1109/les.2024.3436511","url":null,"abstract":"","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"106 1","pages":""},"PeriodicalIF":1.6,"publicationDate":"2024-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141882817","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-07-29DOI: 10.1109/les.2024.3435477
Ricardo Paez Villa, Jorge Rivera, Juan José Raygoza, Edwin Becerra, Susana Ortega
{"title":"Digital Circuit Design for the Square Root Computation by Means of Unfolding Techniques","authors":"Ricardo Paez Villa, Jorge Rivera, Juan José Raygoza, Edwin Becerra, Susana Ortega","doi":"10.1109/les.2024.3435477","DOIUrl":"https://doi.org/10.1109/les.2024.3435477","url":null,"abstract":"","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"213 1","pages":""},"PeriodicalIF":1.6,"publicationDate":"2024-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141871134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-07-29DOI: 10.1109/les.2024.3435388
H. Emmanuel Mu˜ noz, Jorge Rivera, Susana Ortega–Cisneros, Diego H. Gaytàn–Rivas
{"title":"On the Retiming for Register Minimization by Means of Breadth Coefficients Matrix","authors":"H. Emmanuel Mu˜ noz, Jorge Rivera, Susana Ortega–Cisneros, Diego H. Gaytàn–Rivas","doi":"10.1109/les.2024.3435388","DOIUrl":"https://doi.org/10.1109/les.2024.3435388","url":null,"abstract":"","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"159 1","pages":""},"PeriodicalIF":1.6,"publicationDate":"2024-07-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141871021","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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