We explore a relatively lightweight scheme to prevent key recovery by fault attacks on the advanced encryption standard (AES) cipher. We employ a transformed key (derived from the original key through a nonlinear and possibly one-way mapping) for AES encryption hardware. The mapping combines processing using a pseudorandom bitstream generator (the keystream generator of the Grain-128a stream cipher), followed by a self-shrinking generator (SSG). We provide formal proof of security of the scheme, based on the assumed difficulty of inverting the output of the proposed key transformer. The design of the key transformer ensures that it is itself resistant to fault-attack. Our scheme requires a 96-bit secret initial value (IV), a one-time initial latency (approximately 256 clock cycles for a 128-bit key) of generating the transformed key, and a key transformation layer. However, the core AES hardware is left unchanged. We present hardware platform-based experimental results for an FPGA implementation, which incurs less hardware overhead than previously proposed fault attack prevention/detection schemes.
{"title":"A Provably Secure Scheme to Prevent Master Key Recovery by Fault Attack on AES Hardware","authors":"Sneha Swaroopa;Sivappriya Manivannan;Rajat Subhra Chakraborty;Indrajit Chakrabarti","doi":"10.1109/LES.2024.3472673","DOIUrl":"https://doi.org/10.1109/LES.2024.3472673","url":null,"abstract":"We explore a relatively lightweight scheme to prevent key recovery by fault attacks on the advanced encryption standard (AES) cipher. We employ a transformed key (derived from the original key through a nonlinear and possibly one-way mapping) for AES encryption hardware. The mapping combines processing using a pseudorandom bitstream generator (the keystream generator of the Grain-128a stream cipher), followed by a self-shrinking generator (SSG). We provide formal proof of security of the scheme, based on the assumed difficulty of inverting the output of the proposed key transformer. The design of the key transformer ensures that it is itself resistant to fault-attack. Our scheme requires a 96-bit secret initial value (IV), a one-time initial latency (approximately 256 clock cycles for a 128-bit key) of generating the transformed key, and a key transformation layer. However, the core AES hardware is left unchanged. We present hardware platform-based experimental results for an FPGA implementation, which incurs less hardware overhead than previously proposed fault attack prevention/detection schemes.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"16 4","pages":"521-524"},"PeriodicalIF":1.7,"publicationDate":"2024-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142777518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-23DOI: 10.1109/LES.2024.3452551
Phu Khanh Huynh;Ilknur Mustafazade;Francky Catthoor;Nagarajan Kandasamy;Anup Das
Large-scale neuromorphic architectures consist of computing tiles that communicate spikes using a shared interconnect. We propose ADIONA, a dynamic segmented bus interconnect to address design scalability while reducing energy and latency of spike traffic. ADIONA consists of parallel bus lanes arranged in a ladder-shaped structure that allows any tile to connect to another, offers multiple routing options for communication links, and provides a high level of customization for different mapping scenarios and use cases. Each lane in the ladder bus is partitioned into segments using lightweight bufferless switches. Based on compile-time communication information, these switches can be dynamically reconfigured at runtime to execute the target application. Our dynamic segmented bus interconnect substantially enhances hardware utilization, improves fault tolerance, and offers adaptability to execute different applications on a single hardware platform. We evaluate ADIONA using three synthetic and three realistic machine learning workloads on a cycle-accurate neuromorphic simulator. Our results show that ADIONA reduces energy consumption by $2.1times $ , latency by $40times $ , and interconnect area by $2times $ , compared to a state-of-the-art interconnect for neuromorphic systems.
{"title":"A Scalable Dynamic Segmented Bus Interconnect for Neuromorphic Architectures","authors":"Phu Khanh Huynh;Ilknur Mustafazade;Francky Catthoor;Nagarajan Kandasamy;Anup Das","doi":"10.1109/LES.2024.3452551","DOIUrl":"https://doi.org/10.1109/LES.2024.3452551","url":null,"abstract":"Large-scale neuromorphic architectures consist of computing tiles that communicate spikes using a shared interconnect. We propose ADIONA, a dynamic segmented bus interconnect to address design scalability while reducing energy and latency of spike traffic. ADIONA consists of parallel bus lanes arranged in a ladder-shaped structure that allows any tile to connect to another, offers multiple routing options for communication links, and provides a high level of customization for different mapping scenarios and use cases. Each lane in the ladder bus is partitioned into segments using lightweight bufferless switches. Based on compile-time communication information, these switches can be dynamically reconfigured at runtime to execute the target application. Our dynamic segmented bus interconnect substantially enhances hardware utilization, improves fault tolerance, and offers adaptability to execute different applications on a single hardware platform. We evaluate ADIONA using three synthetic and three realistic machine learning workloads on a cycle-accurate neuromorphic simulator. Our results show that ADIONA reduces energy consumption by \u0000<inline-formula> <tex-math>$2.1times $ </tex-math></inline-formula>\u0000, latency by \u0000<inline-formula> <tex-math>$40times $ </tex-math></inline-formula>\u0000, and interconnect area by \u0000<inline-formula> <tex-math>$2times $ </tex-math></inline-formula>\u0000, compared to a state-of-the-art interconnect for neuromorphic systems.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"16 4","pages":"505-508"},"PeriodicalIF":1.7,"publicationDate":"2024-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142777790","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Low density parity check code (LDPC) is the most popular error correction code (ECC) for current nand flash memory controllers. Next generation flash memory, such as triple-level cell (TLC) and quad-level cell (QLC) with a higher bit error rate, bring up the demand for superior ECC algorithms providing excellent performance and acceptable hardware overhead. This letter proposes turbo product code (TPC) as an alternative to LDPC by exploring embedding of a TPC engine into a solid-state drive (SSD) controller architecture. The implementation of this TPC engine uses 2-D error coding and applies the Bose-Chaudhuri–Hocquenghem (BCH) code in each dimension. The algorithm is further improved by flipping the dedicated bit matrix when the basic TPC decoding algorithm terminates with uncorrectable conditions. This bit-flipping enhanced TPC (BFE-TPC) module is finally integrated into a nonvolatile memory express (NVMe) SSD controller driving eight flash memory channels. This BFE-TPC module illustrates the potential of 2D-TPCs as a replacement for LDPCs due to its high throughput and low hardware overhead.
{"title":"An Embedded Module of Enhanced Turbo Product Code Algorithm","authors":"Jianjun Luo;Yifan Shen;Boming Huang;Michael Etzkorn;Hongqiang Chen;Cong Yu","doi":"10.1109/LES.2024.3464517","DOIUrl":"https://doi.org/10.1109/LES.2024.3464517","url":null,"abstract":"Low density parity check code (LDPC) is the most popular error correction code (ECC) for current nand flash memory controllers. Next generation flash memory, such as triple-level cell (TLC) and quad-level cell (QLC) with a higher bit error rate, bring up the demand for superior ECC algorithms providing excellent performance and acceptable hardware overhead. This letter proposes turbo product code (TPC) as an alternative to LDPC by exploring embedding of a TPC engine into a solid-state drive (SSD) controller architecture. The implementation of this TPC engine uses 2-D error coding and applies the Bose-Chaudhuri–Hocquenghem (BCH) code in each dimension. The algorithm is further improved by flipping the dedicated bit matrix when the basic TPC decoding algorithm terminates with uncorrectable conditions. This bit-flipping enhanced TPC (BFE-TPC) module is finally integrated into a nonvolatile memory express (NVMe) SSD controller driving eight flash memory channels. This BFE-TPC module illustrates the potential of 2D-TPCs as a replacement for LDPCs due to its high throughput and low hardware overhead.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"16 4","pages":"509-512"},"PeriodicalIF":1.7,"publicationDate":"2024-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142777726","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-17DOI: 10.1109/LES.2024.3462638
Subhrangshu Adhikary;Subhayu Dutta
Embedded intelligence is a challenging field in engineering given its resource-constrained environment which regular machine learning algorithms demand. Most embedded intelligence models are trained on a computer and then the learned parameters are transferred to the embedded devices to enable decision making. Although training the model within a microcontroller is possible, the state-of-the-art method requires further optimization. Moreover, federated learning (FL) is used in the state of the art to protect data privacy while training a deep learning model at edge level. Embedded learning models require memory enhancements to improve on-device FL. In this experiment, we have performed memory enhancement of gray wolf optimizer after finding it suitable for the purpose and implemented it to create edge-level, resource-efficient, data privacy preserving on-device federated training of embedded intelligence models. The performances are benchmarked on 13 open-sourced datasets showing a mean 10.8% accuracy enhancement.
{"title":"FedTinyWolf—A Memory Efficient Federated Embedded Learning Mechanism","authors":"Subhrangshu Adhikary;Subhayu Dutta","doi":"10.1109/LES.2024.3462638","DOIUrl":"10.1109/LES.2024.3462638","url":null,"abstract":"Embedded intelligence is a challenging field in engineering given its resource-constrained environment which regular machine learning algorithms demand. Most embedded intelligence models are trained on a computer and then the learned parameters are transferred to the embedded devices to enable decision making. Although training the model within a microcontroller is possible, the state-of-the-art method requires further optimization. Moreover, federated learning (FL) is used in the state of the art to protect data privacy while training a deep learning model at edge level. Embedded learning models require memory enhancements to improve on-device FL. In this experiment, we have performed memory enhancement of gray wolf optimizer after finding it suitable for the purpose and implemented it to create edge-level, resource-efficient, data privacy preserving on-device federated training of embedded intelligence models. The performances are benchmarked on 13 open-sourced datasets showing a mean 10.8% accuracy enhancement.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"16 4","pages":"513-516"},"PeriodicalIF":1.7,"publicationDate":"2024-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142263901","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-12DOI: 10.1109/LES.2024.3459730
Muayad J. Aljafar;Zain Ul Abideen;Adriaan Peetermans;Benedikt Gierlichs;Samuel Pagliarini
This letter presents a technique that enables very fine tunability of the frequency of ring oscillators (ROs). Multiple ROs with different numbers of tunable elements were designed and fabricated in a 65-nm CMOS technology. A tunable element consists of two inverters under different local layout effects (LLEs) and a multiplexer. LLEs impact the transient response of inverters deterministically and allow to establish a fine tunable mechanism even in the presence of large process variation. The entire RO is digital and its layout is standard-cell compatible. We demonstrate the tunability of multistage ROs with post-silicon measurements of oscillation frequencies in the range of 80–900 MHz and tuning steps of 90 kHz.
{"title":"SCALLER: Standard Cell Assembled and Local Layout Effect-Based Ring Oscillators","authors":"Muayad J. Aljafar;Zain Ul Abideen;Adriaan Peetermans;Benedikt Gierlichs;Samuel Pagliarini","doi":"10.1109/LES.2024.3459730","DOIUrl":"10.1109/LES.2024.3459730","url":null,"abstract":"This letter presents a technique that enables very fine tunability of the frequency of ring oscillators (ROs). Multiple ROs with different numbers of tunable elements were designed and fabricated in a 65-nm CMOS technology. A tunable element consists of two inverters under different local layout effects (LLEs) and a multiplexer. LLEs impact the transient response of inverters deterministically and allow to establish a fine tunable mechanism even in the presence of large process variation. The entire RO is digital and its layout is standard-cell compatible. We demonstrate the tunability of multistage ROs with post-silicon measurements of oscillation frequencies in the range of 80–900 MHz and tuning steps of 90 kHz.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"16 4","pages":"493-496"},"PeriodicalIF":1.7,"publicationDate":"2024-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142199415","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-28DOI: 10.1109/LES.2024.3450576
James Gerrans;R. Simon Sherratt
Javascript object notation (JSON) and extensible markup language (XML) are two data serialization methods that have been compared over many applications, including client-server transmission, Internet communication, and large-scale data storage. Due to the smaller file size, JSON is faster for transmitting data. However, XML is better for sending complex data structures. This letter compares the two data formats in the context of an embedded system, considering factors, such as time, memory, and power to identify efficient characteristics of each method. Programs for each format were written, optimized, and compared for the same dataset. The JSON file was found to be 24.7% smaller than the XML file. This led to a shorter program run-time and less power being consumed when reading and processing the file. However, the program to deserialize the XML file took up 16.7% less flash memory than its JSON counterpart. Overall, JSON was found to be a better choice for systems when collecting large amounts of data, requiring high speed communication, or running for an extended period between battery charges. However, XML is proposed for systems that have limited flash memory.
{"title":"Comparing XML and JSON Characteristics as Formats for Data Serialization Within Ultralow Power Embedded Systems","authors":"James Gerrans;R. Simon Sherratt","doi":"10.1109/LES.2024.3450576","DOIUrl":"10.1109/LES.2024.3450576","url":null,"abstract":"Javascript object notation (JSON) and extensible markup language (XML) are two data serialization methods that have been compared over many applications, including client-server transmission, Internet communication, and large-scale data storage. Due to the smaller file size, JSON is faster for transmitting data. However, XML is better for sending complex data structures. This letter compares the two data formats in the context of an embedded system, considering factors, such as time, memory, and power to identify efficient characteristics of each method. Programs for each format were written, optimized, and compared for the same dataset. The JSON file was found to be 24.7% smaller than the XML file. This led to a shorter program run-time and less power being consumed when reading and processing the file. However, the program to deserialize the XML file took up 16.7% less flash memory than its JSON counterpart. Overall, JSON was found to be a better choice for systems when collecting large amounts of data, requiring high speed communication, or running for an extended period between battery charges. However, XML is proposed for systems that have limited flash memory.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"16 4","pages":"489-492"},"PeriodicalIF":1.7,"publicationDate":"2024-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142199416","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This letter proposes a novel kind of HT design named multidimensional HTs (MDHTs) and develops a method to generate configurable MDHT benchmark platform. The proposed MDHT circuits include multiple net(s) as trigger signals from each of the rarely activated, highly activated, and partially activated categories to increase MDHT’s adverse effects. The generated MDHT-infected circuits are tested by an unsupervised machine learning-based HT detection technique-controllability and observability for HT detection (COTD). Experimentation on ISCAS benchmarks ensures that the detection method is unable to detect the developed MDHT circuits as the nets belong to higher and partial activities are creating at least 50% and at most 80% false negative rate which validates the MDHT insertion framework in addition to the available HT benchmarks.
{"title":"A Multidimensional Hardware Trojan Design Platform to Enhance Hardware Security","authors":"Nilanjana Das;Mattis Hasler;Friedrich Pauls;Sebastian Haas","doi":"10.1109/LES.2024.3436701","DOIUrl":"10.1109/LES.2024.3436701","url":null,"abstract":"This letter proposes a novel kind of HT design named multidimensional HTs (MDHTs) and develops a method to generate configurable MDHT benchmark platform. The proposed MDHT circuits include multiple net(s) as trigger signals from each of the rarely activated, highly activated, and partially activated categories to increase MDHT’s adverse effects. The generated MDHT-infected circuits are tested by an unsupervised machine learning-based HT detection technique-controllability and observability for HT detection (COTD). Experimentation on ISCAS benchmarks ensures that the detection method is unable to detect the developed MDHT circuits as the nets belong to higher and partial activities are creating at least 50% and at most 80% false negative rate which validates the MDHT insertion framework in addition to the available HT benchmarks.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"17 1","pages":"46-49"},"PeriodicalIF":1.7,"publicationDate":"2024-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141882816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-01DOI: 10.1109/LES.2024.3436511
James R. Majok;Mohammed Abo-Zahhad;Koji Inoue;Mohammed S. Sayed
The high growth of real-time video applications on embedded systems poses challenges for practical encoders aiming to deliver high quality and high speed simultaneously. In real-world video applications, the slower preset in Kvazaar HEVC encoder can achieve impressive quality, with a penalty of extensive computational time. This is ultimately due to rate-distortion optimization that involves a comprehensive analysis of all possible quad-tree partitioning within the coding tree unit (CTU) structure, resulting in unpleasant encoding complexity. This letter proposes a method of accelerating All Intraprediction on Nvidia Jetson TX1 using early termination of CTU partitioning and a method of selecting only eight modes for intraframe search. The proposed technique reduces the running time of an optimized Kvazaar all intraprediction by 48.4% and 40.24% at slower and higher presets, respectively, with an average BD rate lost of 1.5% and 0.682% compared to the optimized Kvazaar running under the same coding configuration.
{"title":"Acceleration of an Optimized Kvazaar All Intra Prediction on Embedded Systems Based on the Directional Texture Complexity","authors":"James R. Majok;Mohammed Abo-Zahhad;Koji Inoue;Mohammed S. Sayed","doi":"10.1109/LES.2024.3436511","DOIUrl":"10.1109/LES.2024.3436511","url":null,"abstract":"The high growth of real-time video applications on embedded systems poses challenges for practical encoders aiming to deliver high quality and high speed simultaneously. In real-world video applications, the slower preset in Kvazaar HEVC encoder can achieve impressive quality, with a penalty of extensive computational time. This is ultimately due to rate-distortion optimization that involves a comprehensive analysis of all possible quad-tree partitioning within the coding tree unit (CTU) structure, resulting in unpleasant encoding complexity. This letter proposes a method of accelerating All Intraprediction on Nvidia Jetson TX1 using early termination of CTU partitioning and a method of selecting only eight modes for intraframe search. The proposed technique reduces the running time of an optimized Kvazaar all intraprediction by 48.4% and 40.24% at slower and higher presets, respectively, with an average BD rate lost of 1.5% and 0.682% compared to the optimized Kvazaar running under the same coding configuration.","PeriodicalId":56143,"journal":{"name":"IEEE Embedded Systems Letters","volume":"17 1","pages":"38-41"},"PeriodicalIF":1.7,"publicationDate":"2024-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141882817","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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