Pub Date : 2021-05-14DOI: 10.33180/INFMIDEM2021.106
Natchanai Roongmuanpha, W. Tangsrirat
A practical realization of a tunable floating capacitance multiplier using commercially available integrated circuits, namely LT1228 is proposed. The synthetic capacitor utilizes only two IC LT1228s along with two passive components (one resistor and one capacitor). The capacitance multiplication factor is electronically controllable through the transconductance gain of the LT1228. The effects of non-ideal transfer gains and parasitic elements of the LT1228 on the circuit performance have been evaluated in detail. The applicability of the proposed floating capacitance multiplier as a second-order band-pass filter is also presented. The claimed theory is verified by several PSPICE simulations and experimental test results.
{"title":"Practical Floating Capacitance Multiplier Implementation with Commercially Available IC LT1228s","authors":"Natchanai Roongmuanpha, W. Tangsrirat","doi":"10.33180/INFMIDEM2021.106","DOIUrl":"https://doi.org/10.33180/INFMIDEM2021.106","url":null,"abstract":"A practical realization of a tunable floating capacitance multiplier using commercially available integrated circuits, namely LT1228 is proposed. The synthetic capacitor utilizes only two IC LT1228s along with two passive components (one resistor and one capacitor). The capacitance multiplication factor is electronically controllable through the transconductance gain of the LT1228. The effects of non-ideal transfer gains and parasitic elements of the LT1228 on the circuit performance have been evaluated in detail. The applicability of the proposed floating capacitance multiplier as a second-order band-pass filter is also presented. The claimed theory is verified by several PSPICE simulations and experimental test results.","PeriodicalId":56293,"journal":{"name":"Informacije Midem-Journal of Microelectronics Electronic Components and Materials","volume":"7 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2021-05-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87449987","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-01-27DOI: 10.33180/INFMIDEM2020.406
Kasthuri Palanichamy, Prakash Poornachari, M. Ganeshmadhan
Optical communication is an effective system to achieve the high-speed data transmission for long distance. The main factor that affects the optical communication is dispersion. Dispersion leads to reduction of the system performance and Q-factor. Dispersion can be compensated using various techniques. Major techniques are compensation using Dispersion Compensating Fiber (DCF), Fiber grating technique, and Delay Line Filter (DLF). Analysis has been performed on the Bit Error Rate and Q factor of various schemes based on Eye Opening Penalty (EOP) with BER analyzer for dispersion compensation.
{"title":"Performance Analysis of Dispersion Compensation Schemes with Delay Line Filter","authors":"Kasthuri Palanichamy, Prakash Poornachari, M. Ganeshmadhan","doi":"10.33180/INFMIDEM2020.406","DOIUrl":"https://doi.org/10.33180/INFMIDEM2020.406","url":null,"abstract":"Optical communication is an effective system to achieve the high-speed data transmission for long distance. The main factor that affects the optical communication is dispersion. Dispersion leads to reduction of the system performance and Q-factor. Dispersion can be compensated using various techniques. Major techniques are compensation using Dispersion Compensating Fiber (DCF), Fiber grating technique, and Delay Line Filter (DLF). Analysis has been performed on the Bit Error Rate and Q factor of various schemes based on Eye Opening Penalty (EOP) with BER analyzer for dispersion compensation.","PeriodicalId":56293,"journal":{"name":"Informacije Midem-Journal of Microelectronics Electronic Components and Materials","volume":"7 1","pages":"285-292"},"PeriodicalIF":1.2,"publicationDate":"2021-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87443252","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-01-27DOI: 10.33180/INFMIDEM2020.403
L. F. Rahman, L. Alam, M. Marufuzzaman
Charge pump (CP) circuit is an essential part of a radio frequency identification electrically-erasable-programmable-read-only memory (RFID-EEPROM). A CP circuit generates boosted output voltage than the power supply voltage. However, the performance of the diode configured CP circuits is strongly affected by the extra power dissipation and the parasitic capacitance. The parasitic capacitors of the CP circuit are also responsible for consuming more power. In this research, an improved CP circuit is designed for achieving higher output voltage gain by reducing the parasitic capacitances. Moreover, the proposed circuit is consumed lower power, which made it more suitable for low power applications like RFID transponder. The proposed CP circuit is using the internal boosted voltage for backward control where active controls are applied to the charge transfer switch (CTS) to eradicate the reverse charge sharing trends. Simulated results showed that by using 1 pF pumping capacitor to drive the capacitive output load, the proposed circuit generates 9.56 V under 1.2 V power supply. In comparison with other research, works this CP circuit is consumed much lower power only 15.26 µW, which is lower than previous research works. Moreover, the proposed CTS CP circuit can produce a higher efficiency of 79.3%, which is found higher compared to other research works. Thus, the proposed design will be an essential module for low power applications like RFID transponder EEPROM.
{"title":"Design of a Low Power and High-Efficiency Charge Pump Circuit for RFID Transponder EEPROM","authors":"L. F. Rahman, L. Alam, M. Marufuzzaman","doi":"10.33180/INFMIDEM2020.403","DOIUrl":"https://doi.org/10.33180/INFMIDEM2020.403","url":null,"abstract":"Charge pump (CP) circuit is an essential part of a radio frequency identification electrically-erasable-programmable-read-only memory (RFID-EEPROM). A CP circuit generates boosted output voltage than the power supply voltage. However, the performance of the diode configured CP circuits is strongly affected by the extra power dissipation and the parasitic capacitance. The parasitic capacitors of the CP circuit are also responsible for consuming more power. In this research, an improved CP circuit is designed for achieving higher output voltage gain by reducing the parasitic capacitances. Moreover, the proposed circuit is consumed lower power, which made it more suitable for low power applications like RFID transponder. The proposed CP circuit is using the internal boosted voltage for backward control where active controls are applied to the charge transfer switch (CTS) to eradicate the reverse charge sharing trends. Simulated results showed that by using 1 pF pumping capacitor to drive the capacitive output load, the proposed circuit generates 9.56 V under 1.2 V power supply. In comparison with other research, works this CP circuit is consumed much lower power only 15.26 µW, which is lower than previous research works. Moreover, the proposed CTS CP circuit can produce a higher efficiency of 79.3%, which is found higher compared to other research works. Thus, the proposed design will be an essential module for low power applications like RFID transponder EEPROM.","PeriodicalId":56293,"journal":{"name":"Informacije Midem-Journal of Microelectronics Electronic Components and Materials","volume":"14 1","pages":"255-262"},"PeriodicalIF":1.2,"publicationDate":"2021-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77722049","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-01-27DOI: 10.33180/INFMIDEM2020.405
A. Chaabane, O. Mahri, Djelloul Aissaoui, N. Guebgoub
In this paper, a novel design of a coplanar waveguide fed (CPW) triple-band antenna is introduced. An ultra-wideband (UWB) characteristic is achieved by the initial design through the cut of a stepped shape from the lower part of the initial radiating patch and through the use of a truncated ground plane. A transition from the UWB to multiband function is assured by etching a simple ring inside the radiating patch. The antenna is printed on the low-cost FR4-substrate having a compact size of 0.162λ0×0.123λ0×0.008λ0 at 1.57 GHz. The design and the analysis of the antenna were done using the commercially software CST Microwave StudioTM while the fabricated prototype was tested and measured by using a R&S®ZNB Vector Network Analyzer. The measurements show that the fabricated prototype resonates between 1.57-2.33 GHz (38.97%), 5.84-6.41 GHz (9.31%), and 7.93-10.88 GHz (31.37%). Besides, the proposed antenna has consistent measured radiation patterns characteristics and it also reveals an acceptable realized gain and a high efficiency over the working ranges. Hence, the designed antenna can be a good candidate for many wireless communication systems.
{"title":"Multiband Stepped Antenna for Wireless Communication Applications","authors":"A. Chaabane, O. Mahri, Djelloul Aissaoui, N. Guebgoub","doi":"10.33180/INFMIDEM2020.405","DOIUrl":"https://doi.org/10.33180/INFMIDEM2020.405","url":null,"abstract":"In this paper, a novel design of a coplanar waveguide fed (CPW) triple-band antenna is introduced. An ultra-wideband (UWB) characteristic is achieved by the initial design through the cut of a stepped shape from the lower part of the initial radiating patch and through the use of a truncated ground plane. A transition from the UWB to multiband function is assured by etching a simple ring inside the radiating patch. The antenna is printed on the low-cost FR4-substrate having a compact size of 0.162λ0×0.123λ0×0.008λ0 at 1.57 GHz. The design and the analysis of the antenna were done using the commercially software CST Microwave StudioTM while the fabricated prototype was tested and measured by using a R&S®ZNB Vector Network Analyzer. The measurements show that the fabricated prototype resonates between 1.57-2.33 GHz (38.97%), 5.84-6.41 GHz (9.31%), and 7.93-10.88 GHz (31.37%). Besides, the proposed antenna has consistent measured radiation patterns characteristics and it also reveals an acceptable realized gain and a high efficiency over the working ranges. Hence, the designed antenna can be a good candidate for many wireless communication systems.","PeriodicalId":56293,"journal":{"name":"Informacije Midem-Journal of Microelectronics Electronic Components and Materials","volume":"35 1","pages":"275-285"},"PeriodicalIF":1.2,"publicationDate":"2021-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88434860","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-01-27DOI: 10.33180/INFMIDEM2020.401
Islombek Mamatov
Carbon nanotube field effect transistor (CNTFET) is strong candidate to replace existing silicon based transistors. The ballistic transport of electrons in CNTFET channel leads to ultra-low power or high frequency devices. Since, lot of digital applications of CNCTFET were presented. However, much less work was done in analog applications of CNTFETs. This paper presents analog applications of CNTFET and CNTFET implementation of voltage differencing transconductance amplifier (VDTA). The CNTFET VDTA based filters and oscillators were proposed. The VDTA circuits are resistorless and can be tuned electronically only by changing transconductance. The proposed CNTFET VDTA show power consumption of 15000 times less than compared to 0.18um TSMC technology and significant reduction in chip area. All simulations were performed using HSPICE and MATLAB simulation tools.
{"title":"Voltage Differencing Transconductance Amplifier based Ultra-Low Power, Universal Filters and Oscillators using 32 nm Carbon Nanotube Field Eff ect Transistor Technology","authors":"Islombek Mamatov","doi":"10.33180/INFMIDEM2020.401","DOIUrl":"https://doi.org/10.33180/INFMIDEM2020.401","url":null,"abstract":"Carbon nanotube field effect transistor (CNTFET) is strong candidate to replace existing silicon based transistors. The ballistic transport of electrons in CNTFET channel leads to ultra-low power or high frequency devices. Since, lot of digital applications of CNCTFET were presented. However, much less work was done in analog applications of CNTFETs. This paper presents analog applications of CNTFET and CNTFET implementation of voltage differencing transconductance amplifier (VDTA). The CNTFET VDTA based filters and oscillators were proposed. The VDTA circuits are resistorless and can be tuned electronically only by changing transconductance. The proposed CNTFET VDTA show power consumption of 15000 times less than compared to 0.18um TSMC technology and significant reduction in chip area. All simulations were performed using HSPICE and MATLAB simulation tools.","PeriodicalId":56293,"journal":{"name":"Informacije Midem-Journal of Microelectronics Electronic Components and Materials","volume":"6 1","pages":"233-242"},"PeriodicalIF":1.2,"publicationDate":"2021-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79224767","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-01-27DOI: 10.33180/INFMIDEM2020.404
Abolfazl Bijari, Hossein Khosravi, M. Ebrahimipour
low noise amplifier (LNA); concurrent; dual-band; inverter-basedIn this paper, a two-stage concurrent dual-band low noise amplifier (DB-LNA) operating at 2.4/5.2-GHz is presented for Wireless Local Area Network (WLAN) applications. The current-reused structure using resistive shunt-shunt feedback is employed to reduce power dissipation and achieve a wide frequency band from DC to-5.5-GHz in the inverter-based LNA. The second inverter-based stage is employed to increase the gain and obtain a flat gain over the frequency band. An LC network is also inserted at the proposed circuit output to shape the dual-band frequency response. The proposed concurrent DB-LNA is designed by RF-TSMC 0.18-µm CMOS technology, which consumes 10.8 mW from a power supply of 1.5 V. The simulation results show that the proposed DB-LNA achieves a direct power gain (S 21 ) of 13.7/14.1 dB, a noise figure (NF) of 4.2/4.6 dB, and an input return loss (S 11 ) of −12.9/−14.6 dBm at the 2.4/5.2-GHz bands.
{"title":"Concurrent Dual-Band Inverter-Based Low Noise Amplifier (LNA) for WLAN Applications","authors":"Abolfazl Bijari, Hossein Khosravi, M. Ebrahimipour","doi":"10.33180/INFMIDEM2020.404","DOIUrl":"https://doi.org/10.33180/INFMIDEM2020.404","url":null,"abstract":"low noise amplifier (LNA); concurrent; dual-band; inverter-basedIn this paper, a two-stage concurrent dual-band low noise amplifier (DB-LNA) operating at 2.4/5.2-GHz is presented for Wireless Local Area Network (WLAN) applications. The current-reused structure using resistive shunt-shunt feedback is employed to reduce power dissipation and achieve a wide frequency band from DC to-5.5-GHz in the inverter-based LNA. The second inverter-based stage is employed to increase the gain and obtain a flat gain over the frequency band. An LC network is also inserted at the proposed circuit output to shape the dual-band frequency response. The proposed concurrent DB-LNA is designed by RF-TSMC 0.18-µm CMOS technology, which consumes 10.8 mW from a power supply of 1.5 V. The simulation results show that the proposed DB-LNA achieves a direct power gain (S 21 ) of 13.7/14.1 dB, a noise figure (NF) of 4.2/4.6 dB, and an input return loss (S 11 ) of −12.9/−14.6 dBm at the 2.4/5.2-GHz bands.","PeriodicalId":56293,"journal":{"name":"Informacije Midem-Journal of Microelectronics Electronic Components and Materials","volume":"9 1","pages":"263-274"},"PeriodicalIF":1.2,"publicationDate":"2021-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84318271","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-01-27DOI: 10.33180/INFMIDEM2020.402
Ali Murat Garipcan, E. Erdem
In this study, successful real-time implementation of discrete-time chaotic zigzag map as a Random Number Generator on field-programmable gate array (FPGA) environment is presented. For hardware implementation, in addition to ready-use circuit elements defined on 32-bit floating-point numbers, very high-speed integrated circuit hardware description language (VHDL) is used. In the scope of this study, cryptographic critical competencies such as system reliability and randomness quality related to nonlinear dynamic behaviour of zigzag map are examined. H function post - processing technique is used in the system for random numbers with low statistical quality achieved from chaotic system. Also NIST 800-22 standard test technique is used for statistical verification of bit sequences obtained from the generator. In addition to its practical applicability, the results show that the zigzag map can be used as a random number generator for embeded cryptographic applications.
{"title":"Hardware Implementation of Chaotic Zigzag Map Based Bitwise Dynamical PRNG on FPGA","authors":"Ali Murat Garipcan, E. Erdem","doi":"10.33180/INFMIDEM2020.402","DOIUrl":"https://doi.org/10.33180/INFMIDEM2020.402","url":null,"abstract":"In this study, successful real-time implementation of discrete-time chaotic zigzag map as a Random Number Generator on field-programmable gate array (FPGA) environment is presented. For hardware implementation, in addition to ready-use circuit elements defined on 32-bit floating-point numbers, very high-speed integrated circuit hardware description language (VHDL) is used. In the scope of this study, cryptographic critical competencies such as system reliability and randomness quality related to nonlinear dynamic behaviour of zigzag map are examined. H function post - processing technique is used in the system for random numbers with low statistical quality achieved from chaotic system. Also NIST 800-22 standard test technique is used for statistical verification of bit sequences obtained from the generator. In addition to its practical applicability, the results show that the zigzag map can be used as a random number generator for embeded cryptographic applications.","PeriodicalId":56293,"journal":{"name":"Informacije Midem-Journal of Microelectronics Electronic Components and Materials","volume":"18 1","pages":"243-254"},"PeriodicalIF":1.2,"publicationDate":"2021-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87229121","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-01-01DOI: 10.33180/infmidem2021.103
Kamaraj Arunachalam, M. Perumalsamy, Abirami Ramasamy
: Memory and its data communication play a vital role in deciding the performance of a Processor. In order to obtain a high performance computing machine, memory access has to be equally faster. In this paper, Dual port memory with Set/Reset is designed using Majority Voter in Quantum-dot Cellular Automata (QCA). Dual port memory consists of basic functional blocks such as 2 to 4 decoder, Control Logic Block (CLB), Address Checker Block (ACB), Memory Cell (MC), Data Router block and Input/Output block. These functional units are constructed using the 3-input majority voters. QCA is one of the recent technologies for the design of nanometer level digital components. The functionality of Dual Port Memory has been simulated and verified in QCADesigner 2.0.3. A novel crossover method called Logical Crossing is utilized to improve the area of the proposed design. The logical crossing does the data transmission with the support of proper Clock zone assignment. The logical crossing based QCA layouts are optimized in terms of area and number of cell counts. It is observed that 29.81%, 18.27%, 8.32%, 11.57% and 3.69% are the percentage of improvement in the number of cells in Decoder, ACB, CLB, Data Router and Memory Cell respectively. Also, 25.71%, 16.83%, 8.62%, 4.74% and 3.73% of improvement is achieved in the area for Decoder, ACB, CLB, Data Router and Memory Cell respectively. In addition to that the proposed Dual port memory using logical crossing attains improvement in the area by 8.26%; that is made possible due to the 8.65% reduction in the number of cells required for its construction. Moreover, the quantum circuits of the RAM are obtained using the RCViewer+ tool. The quantum cost, constant inputs, the number of gates, garbage output and total cost are estimated as 285, 67, 57, 50 and 516 respectively.
{"title":"Multi-Port Memory Design in Quantum Cellular Automata Using Logical Crossing","authors":"Kamaraj Arunachalam, M. Perumalsamy, Abirami Ramasamy","doi":"10.33180/infmidem2021.103","DOIUrl":"https://doi.org/10.33180/infmidem2021.103","url":null,"abstract":": Memory and its data communication play a vital role in deciding the performance of a Processor. In order to obtain a high performance computing machine, memory access has to be equally faster. In this paper, Dual port memory with Set/Reset is designed using Majority Voter in Quantum-dot Cellular Automata (QCA). Dual port memory consists of basic functional blocks such as 2 to 4 decoder, Control Logic Block (CLB), Address Checker Block (ACB), Memory Cell (MC), Data Router block and Input/Output block. These functional units are constructed using the 3-input majority voters. QCA is one of the recent technologies for the design of nanometer level digital components. The functionality of Dual Port Memory has been simulated and verified in QCADesigner 2.0.3. A novel crossover method called Logical Crossing is utilized to improve the area of the proposed design. The logical crossing does the data transmission with the support of proper Clock zone assignment. The logical crossing based QCA layouts are optimized in terms of area and number of cell counts. It is observed that 29.81%, 18.27%, 8.32%, 11.57% and 3.69% are the percentage of improvement in the number of cells in Decoder, ACB, CLB, Data Router and Memory Cell respectively. Also, 25.71%, 16.83%, 8.62%, 4.74% and 3.73% of improvement is achieved in the area for Decoder, ACB, CLB, Data Router and Memory Cell respectively. In addition to that the proposed Dual port memory using logical crossing attains improvement in the area by 8.26%; that is made possible due to the 8.65% reduction in the number of cells required for its construction. Moreover, the quantum circuits of the RAM are obtained using the RCViewer+ tool. The quantum cost, constant inputs, the number of gates, garbage output and total cost are estimated as 285, 67, 57, 50 and 516 respectively.","PeriodicalId":56293,"journal":{"name":"Informacije Midem-Journal of Microelectronics Electronic Components and Materials","volume":"14 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2021-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78517967","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-11-20DOI: 10.33180/infmidem2020.302
Zhifeng Zhao, Tianyu Yu, Peng Si, Kai Zhang, Weifeng Lyu
In this work, we propose a negative-capacitance double-gate junctionless field-effect transistor (NC-JLFET) with additional source-drain doping for the first time. Superior performance of the NC-JLFET due to source and drain doping concentration is explained in detail. Additionally, the effects of the drain induced barrier lowering (DIBL) and negative differential resistance (NDR) are precisely analyzed in the NC-JLFET. Sentaurus TCAD simulation demonstrates that the additional source-drain-doped NC-JLFET exhibits a higher on/off current ratio ( I ON / I OFF ) and steeper subthreshold swing ( SS < 60 mV/dec) compared to a traditional JLFET. Besides, the negative capacitance effect causes the internal voltage of the gate to be amplified, resulting in negative DIBL and NDR phenomena. Finally, the performance of NC-JLFET can also be optimized by choosing suitable ferroelectric material parameters, such as ferroelectric thickness, coercive field, and remnant polarization. Our simulation study provides theoretical and experimental support for further performance improvement of low-power NCFETs by local structure adjustment.
在这项工作中，我们首次提出了一种具有附加源极漏极掺杂的负电容双栅无结场效应晶体管(NC-JLFET)。详细解释了源极和漏极掺杂浓度对NC-JLFET性能的影响。此外，还对NC-JLFET中漏极诱导势垒降低(DIBL)和负差分电阻(NDR)的影响进行了精确分析。Sentaurus TCAD仿真表明，与传统的JLFET相比，额外掺源漏极的NC-JLFET具有更高的开/关电流比(I on/ I off)和更陡的亚阈值摆幅(SS < 60 mV/dec)。此外，负电容效应使栅极内部电压被放大，产生负DIBL和负NDR现象。最后，通过选择合适的铁电材料参数，如铁电厚度、矫顽力场和残余极化，可以优化NC-JLFET的性能。本文的仿真研究为通过局部结构调整进一步提高低功率ncfet的性能提供了理论和实验支持。
{"title":"Superior Performance of a Negative-capacitance Double-gate Junctionless Field-effect Transistor with Additional Source-drain Doping","authors":"Zhifeng Zhao, Tianyu Yu, Peng Si, Kai Zhang, Weifeng Lyu","doi":"10.33180/infmidem2020.302","DOIUrl":"https://doi.org/10.33180/infmidem2020.302","url":null,"abstract":"In this work, we propose a negative-capacitance double-gate junctionless field-effect transistor (NC-JLFET) with additional source-drain doping for the first time. Superior performance of the NC-JLFET due to source and drain doping concentration is explained in detail. Additionally, the effects of the drain induced barrier lowering (DIBL) and negative differential resistance (NDR) are precisely analyzed in the NC-JLFET. Sentaurus TCAD simulation demonstrates that the additional source-drain-doped NC-JLFET exhibits a higher on/off current ratio ( I ON / I OFF ) and steeper subthreshold swing ( SS < 60 mV/dec) compared to a traditional JLFET. Besides, the negative capacitance effect causes the internal voltage of the gate to be amplified, resulting in negative DIBL and NDR phenomena. Finally, the performance of NC-JLFET can also be optimized by choosing suitable ferroelectric material parameters, such as ferroelectric thickness, coercive field, and remnant polarization. Our simulation study provides theoretical and experimental support for further performance improvement of low-power NCFETs by local structure adjustment.","PeriodicalId":56293,"journal":{"name":"Informacije Midem-Journal of Microelectronics Electronic Components and Materials","volume":"48 1","pages":"169-178"},"PeriodicalIF":1.2,"publicationDate":"2020-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76804124","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-11-20DOI: 10.33180/infmidem2020.306
S. Ramasamy, Ilambirai Raghavan Chandran, Chellammal Nallaperumal
In this paper, a zeta-zeta coupled non-isolated multiport converter is proposed and implemented. The new dc-dc multiport converter discussed here facilitates the access of two renewable energy sources in the input side and a single output. Zeta converter topology facilitates high voltage gain with a reduced output voltage ripple. Multiport converters have become very prominent in recent past due to the prevalent establishments of distributed energy resources. Therefore in research arena there is no literature evidence for Zeta –Zeta converters used in multiport converters. This research work emphasize on suggesting a Zeta-Zeta multiport converter with reduced number of switches. The proposed converter is simulated in MATLAB/ Simulink environment and is also realized as a hardware prototype. The voltage gain and efficiency of the proposed circuit is compared with its counterpart multiport topologies. The simulation and hardware results show that the proposed topology is having a clear edge on its counter parts in voltage gain and efficiency. The proposed converter indisputably assures the utmost use of renewable energy resources.
{"title":"A High Voltage Gain Multiport Zeta-Zeta Converter for Renewable Energy Systems","authors":"S. Ramasamy, Ilambirai Raghavan Chandran, Chellammal Nallaperumal","doi":"10.33180/infmidem2020.306","DOIUrl":"https://doi.org/10.33180/infmidem2020.306","url":null,"abstract":"In this paper, a zeta-zeta coupled non-isolated multiport converter is proposed and implemented. The new dc-dc multiport converter discussed here facilitates the access of two renewable energy sources in the input side and a single output. Zeta converter topology facilitates high voltage gain with a reduced output voltage ripple. Multiport converters have become very prominent in recent past due to the prevalent establishments of distributed energy resources. Therefore in research arena there is no literature evidence for Zeta –Zeta converters used in multiport converters. This research work emphasize on suggesting a Zeta-Zeta multiport converter with reduced number of switches. The proposed converter is simulated in MATLAB/ Simulink environment and is also realized as a hardware prototype. The voltage gain and efficiency of the proposed circuit is compared with its counterpart multiport topologies. The simulation and hardware results show that the proposed topology is having a clear edge on its counter parts in voltage gain and efficiency. The proposed converter indisputably assures the utmost use of renewable energy resources.","PeriodicalId":56293,"journal":{"name":"Informacije Midem-Journal of Microelectronics Electronic Components and Materials","volume":"104 1","pages":"215-230"},"PeriodicalIF":1.2,"publicationDate":"2020-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76004094","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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