Pub Date : 2019-05-07DOI: 10.33180/infmidem2019.102
Hemalatha Raju, R. Mahalakshmi
In optical networks, Routing and Wavelength Assignment (RWA) problem is one of the major optimization problems. This problem can be solved by different algorithms such as Genetic Algorithm (GA), Artificial Bee Colony (ABC), Ant Colony Optimization (ACO), etc. Shuffled Frog Leaping Algorithm (SFLA) is implemented in the proposed work, to solve the RWA problem in long-haul optical networks. The goal is to use minimum number of wavelengths and to reduce the number of connection request rejections. Cost, number of wavelengths, hop count and blocking probability are the performance metrics considered in the analysis. Various wavelength assignment methods such as first fit, random, round robin, wavelength ordering and Four Wave Mixing (FWM) priority based wavelength assignment are used in the analysis using SFLA. Number of wavelengths, hop count, cost and setup time are included in the fitness function. The SFLA algorithm proposed, has been analyzed for different network loads and compared with the performance of genetic algorithm.
{"title":"A Memetic based Approach for Routing and\u0000Wavelength Assignment in Optical Transmission\u0000Systems","authors":"Hemalatha Raju, R. Mahalakshmi","doi":"10.33180/infmidem2019.102","DOIUrl":"https://doi.org/10.33180/infmidem2019.102","url":null,"abstract":"In optical networks, Routing and Wavelength Assignment (RWA) problem is one of the major optimization problems. This\u0000problem can be solved by different algorithms such as Genetic Algorithm (GA), Artificial Bee Colony (ABC), Ant Colony Optimization\u0000(ACO), etc. Shuffled Frog Leaping Algorithm (SFLA) is implemented in the proposed work, to solve the RWA problem in long-haul\u0000optical networks. The goal is to use minimum number of wavelengths and to reduce the number of connection request rejections.\u0000Cost, number of wavelengths, hop count and blocking probability are the performance metrics considered in the analysis. Various\u0000wavelength assignment methods such as first fit, random, round robin, wavelength ordering and Four Wave Mixing (FWM) priority\u0000based wavelength assignment are used in the analysis using SFLA. Number of wavelengths, hop count, cost and setup time are\u0000included in the fitness function. The SFLA algorithm proposed, has been analyzed for different network loads and compared with the\u0000performance of genetic algorithm.","PeriodicalId":56293,"journal":{"name":"Informacije Midem-Journal of Microelectronics Electronic Components and Materials","volume":"144 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2019-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77532507","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-07DOI: 10.33180/INFMIDEM2019.104
Rajeev Pankaj Nelapati, K. Sivasankaran
In this work, the performance of selective buried oxide junction-less (SELBOX-JL) transistor at a FinFET structure is analysed using numerical simulations. The proposed structure exhibits better thermal resistance (RTH), which is the measure of the self-heating effect (SHE). The DC and analog performances of the proposed structure were studied and compared with the conventional and hybrid (or inverted-T) JLFinFETs (JLTs). The ION of the hybrid SELBOX- JLFinFET is 1.43x times better than the ION of the JLT due to the added advantage of different technologies, such as 2D-ultra-thin-body (UTB), 3D-FinFET, and SELBOX. The proposed device is modeled using sprocess and simulation study is carried using sdevice. Various analog parameters, such as transconductance (gm), transconductance generation factor (TGF = gm/IDS), unity current gain frequency (fT), early voltage (VEA), total gate capacitance (Cgg), and intrinsic gain (A0), are evaluated. The proposed device with a minimum feature size of 10nm exhibited better TGF, fT, VEA, and A0 in the deep-inversion region of operation.
{"title":"Design and Performance Analysis of Hybrid\u0000SELBOX Junctionless FinFET","authors":"Rajeev Pankaj Nelapati, K. Sivasankaran","doi":"10.33180/INFMIDEM2019.104","DOIUrl":"https://doi.org/10.33180/INFMIDEM2019.104","url":null,"abstract":"In this work, the performance of selective buried oxide junction-less (SELBOX-JL) transistor at a FinFET structure is analysed\u0000using numerical simulations. The proposed structure exhibits better thermal resistance (RTH), which is the measure of the self-heating\u0000effect (SHE). The DC and analog performances of the proposed structure were studied and compared with the conventional and\u0000hybrid (or inverted-T) JLFinFETs (JLTs). The ION of the hybrid SELBOX- JLFinFET is 1.43x times better than the ION of the JLT due to\u0000the added advantage of different technologies, such as 2D-ultra-thin-body (UTB), 3D-FinFET, and SELBOX. The proposed device is\u0000modeled using sprocess and simulation study is carried using sdevice. Various analog parameters, such as transconductance (gm),\u0000transconductance generation factor (TGF = gm/IDS), unity current gain frequency (fT), early voltage (VEA), total gate capacitance (Cgg), and\u0000intrinsic gain (A0), are evaluated. The proposed device with a minimum feature size of 10nm exhibited better TGF, fT, VEA, and A0 in the\u0000deep-inversion region of operation.","PeriodicalId":56293,"journal":{"name":"Informacije Midem-Journal of Microelectronics Electronic Components and Materials","volume":"31 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2019-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86372127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-07DOI: 10.33180/INFMIDEM2019.105
M. Pirc
Parametric acoustic arrays (PAA) have progressed from specialized niche applications to commercially available audio solutions in the last two decades. Their primary advantage is their incredible directivity and their main disadvantage is low conversion efficiency of the primary ultrasonic waves into audible sound. This paper presents a noise analysis of a practical implementation of a directional audio system. The system is comprised of a modulator, a D-class audio amplifier, and an emitter consisting of 97 commercially available piezoelectric ultrasonic transducers. The designed system exhibited an uncomfortable level of idle noise at the maximum volume level. The analysis of the signal path and all the noise sources revealed that the most critical component was the modulator, and a solution was devised which provided a 16 dB improvement of the carrier to noise ratio.
{"title":"Idle Noise Reduction of a Parametric Acoustic\u0000Array Power Driver","authors":"M. Pirc","doi":"10.33180/INFMIDEM2019.105","DOIUrl":"https://doi.org/10.33180/INFMIDEM2019.105","url":null,"abstract":"Parametric acoustic arrays (PAA) have progressed from specialized niche applications to commercially available audio\u0000solutions in the last two decades. Their primary advantage is their incredible directivity and their main disadvantage is low conversion\u0000efficiency of the primary ultrasonic waves into audible sound. This paper presents a noise analysis of a practical implementation\u0000of a directional audio system. The system is comprised of a modulator, a D-class audio amplifier, and an emitter consisting of 97\u0000commercially available piezoelectric ultrasonic transducers. The designed system exhibited an uncomfortable level of idle noise at the\u0000maximum volume level. The analysis of the signal path and all the noise sources revealed that the most critical component was the\u0000modulator, and a solution was devised which provided a 16 dB improvement of the carrier to noise ratio.","PeriodicalId":56293,"journal":{"name":"Informacije Midem-Journal of Microelectronics Electronic Components and Materials","volume":"72 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2019-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83731677","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-02-01DOI: 10.33180/infmidem2018.404
M. Mojibi, M. Radmehr
The design, which is based on the concept of reliability, is impressive. In power electronic circuits, the reliability design has been shown to be useful over time. Moreover, power loss in switches and diodes plays a permanent role in reliability assessment. This paper presents a reliability evaluation for a buck converter based on thermal analysis of an insulated-gate bipolar transistor (IGBT) and a diode. The provided thermal analysis is used to determine the switch and diode junction temperature. In this study, the effects of switching frequency and duty cycle are considered as criteria for reliability. A limit of 150°C has been set for over-temperature issues. The simulation of a 12 kW buck converter (duty cycle = 42% and switching frequency = 10 kHz) illustrates that the switch and diode junction temperature are 117.29°C and 122.27°C, respectively. The results show that mean time to failure for the buck converter is 32,973 hours.
{"title":"Reliability evaluation of buck converter based on\u0000thermal analysis","authors":"M. Mojibi, M. Radmehr","doi":"10.33180/infmidem2018.404","DOIUrl":"https://doi.org/10.33180/infmidem2018.404","url":null,"abstract":"The design, which is based on the concept of reliability, is impressive. In power electronic circuits, the reliability design has\u0000been shown to be useful over time. Moreover, power loss in switches and diodes plays a permanent role in reliability assessment. This\u0000paper presents a reliability evaluation for a buck converter based on thermal analysis of an insulated-gate bipolar transistor (IGBT) and\u0000a diode. The provided thermal analysis is used to determine the switch and diode junction temperature. In this study, the effects of\u0000switching frequency and duty cycle are considered as criteria for reliability. A limit of 150°C has been set for over-temperature issues.\u0000The simulation of a 12 kW buck converter (duty cycle = 42% and switching frequency = 10 kHz) illustrates that the switch and diode\u0000junction temperature are 117.29°C and 122.27°C, respectively. The results show that mean time to failure for the buck converter is\u000032,973 hours.","PeriodicalId":56293,"journal":{"name":"Informacije Midem-Journal of Microelectronics Electronic Components and Materials","volume":"41 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77293903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-02-01DOI: 10.33180/infmidem2018.405
Vladimir Furlan, S. Glinšek, Tanja Pečnik, M. Vidmar, B. Kmet, Barbara, Malič
A low-profile, compact and frequency-tunable antenna made on ferroelectric substrate is presented. It is designed as a planar dipole antenna with an IDC varactor integrated in the signal line. Antenna is fed through a coplanar waveguide matched to 50 Ω. The center frequency can be tuned from 6.895 GHz to 7.050 GHz. It exhibits elliptical polarization and omnidirectional radiation pattern.
{"title":"Elliptically polarized frequency agile antenna on\u0000ferroelectric substrate","authors":"Vladimir Furlan, S. Glinšek, Tanja Pečnik, M. Vidmar, B. Kmet, Barbara, Malič","doi":"10.33180/infmidem2018.405","DOIUrl":"https://doi.org/10.33180/infmidem2018.405","url":null,"abstract":"A low-profile, compact and frequency-tunable antenna made on ferroelectric substrate is presented. It is designed as a\u0000planar dipole antenna with an IDC varactor integrated in the signal line. Antenna is fed through a coplanar waveguide matched to\u000050 Ω. The center frequency can be tuned from 6.895 GHz to 7.050 GHz. It exhibits elliptical polarization and omnidirectional radiation\u0000pattern.","PeriodicalId":56293,"journal":{"name":"Informacije Midem-Journal of Microelectronics Electronic Components and Materials","volume":"6 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72513270","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-02-01DOI: 10.33180/InfMIDEM2018.403
Zhiyuan Zhu
Temporary bonding using paper inserted polypropylene carbonate (PPC) layer is demonstrated. The inserted paper layer can absorb photo acid generator (PAG)-induced acid and protect the substrate. Large improvements of bonding strength are achieved using paper inserted PPC layer. Especially, the bonding strength is much higher than that of PPC/PAG-PPC bonding for tissue paper. The results show that the paper fibers can absorb decomposed PPC and PAG-induced acid, thus protecting the substrate
{"title":"Temporary Bonding Using Paper Inserted PPC\u0000Layer","authors":"Zhiyuan Zhu","doi":"10.33180/InfMIDEM2018.403","DOIUrl":"https://doi.org/10.33180/InfMIDEM2018.403","url":null,"abstract":"Temporary bonding using paper inserted polypropylene carbonate (PPC) layer is demonstrated. The inserted paper layer\u0000can absorb photo acid generator (PAG)-induced acid and protect the substrate. Large improvements of bonding strength are achieved\u0000using paper inserted PPC layer. Especially, the bonding strength is much higher than that of PPC/PAG-PPC bonding for tissue paper.\u0000The results show that the paper fibers can absorb decomposed PPC and PAG-induced acid, thus protecting the substrate","PeriodicalId":56293,"journal":{"name":"Informacije Midem-Journal of Microelectronics Electronic Components and Materials","volume":"22 41","pages":""},"PeriodicalIF":1.2,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72396202","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-02-01DOI: 10.33180/infmidem2018.408
Miha Gradisek, D. Strle
Most ASIC’s demand signal conditioning sub-circuits to modify various signal parameters; one of the important parameter is the gain. The presented configuration is based on the conventional R-2R structure which mainly suffers from the mismatch imperfections. The study shows possible approach to improve mismatch characteristic or enables us to take the advantage to increase bit resolution without mismatch deteriorations. The approach could be used to even further improve accuracy of the numerous previously described approaches [1], [2] which already eliminate high resolution mismatch imperfections. Paper presents the implementation of the gain stage with digital gain adjustment, in the range from 0.9 to 1.1 in 128 equidistant monotonous steps, nevertheless the approach could be implemented even for higher resolution stages. For robust design in terms of the fabrication process and harsh environment operation, a fully differential amplifier was designed in standard 0.18μm CMOS technology. Designed amplifier in combination with resistive network is presented together with simulation results including the parasitic capacitances.
{"title":"Digitally Adjustable Differential Gain Stage","authors":"Miha Gradisek, D. Strle","doi":"10.33180/infmidem2018.408","DOIUrl":"https://doi.org/10.33180/infmidem2018.408","url":null,"abstract":"Most ASIC’s demand signal conditioning sub-circuits to modify various signal parameters; one of the important parameter\u0000is the gain. The presented configuration is based on the conventional R-2R structure which mainly suffers from the mismatch\u0000imperfections. The study shows possible approach to improve mismatch characteristic or enables us to take the advantage to\u0000increase bit resolution without mismatch deteriorations. The approach could be used to even further improve accuracy of the\u0000numerous previously described approaches [1], [2] which already eliminate high resolution mismatch imperfections. Paper presents\u0000the implementation of the gain stage with digital gain adjustment, in the range from 0.9 to 1.1 in 128 equidistant monotonous steps,\u0000nevertheless the approach could be implemented even for higher resolution stages. For robust design in terms of the fabrication\u0000process and harsh environment operation, a fully differential amplifier was designed in standard 0.18μm CMOS technology. Designed\u0000amplifier in combination with resistive network is presented together with simulation results including the parasitic capacitances.","PeriodicalId":56293,"journal":{"name":"Informacije Midem-Journal of Microelectronics Electronic Components and Materials","volume":"14 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87325308","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-02-01DOI: 10.33180/INFMIDEM2018.406
N. Lokar, V. Kononenko, D. Drobne, D. Vrtacnik
Cholinesterase inhibitors are widely used as pesticides, as chemical warfare agents and as drugs to treat symptoms of Alzheimer’s disease. Therefore, it is a high need to develop methods for their detection which are fast, sensitive, and reliable. This paper reports a preliminary work in the development of an electrochemical biosensor based on acetylcholinesterase (AChE) which is constructed by immobilization layers – cysteamine/glutaraldehyde/AChE on thin layer gold electrode for detection of cholinesterase inhibitors. Eserine (physostigmine) was used as a test inhibitor. The enzyme immobilization efficacy was evaluated by measuring activity of immobilized enzyme via Ellman’s method. The enzyme activity of the initial reduction of 33% in five days remained after that stable for at least one week. Chronoamperometric response to substrate acetylthiocholine chloride (ATCl) was assumed to follow Michaelis-Menten kinetics. After exposure biosensor to 25 mM eserine for 10 min, 70% inhibition of enzyme was detected. Reactivation factor of inhibited AChE was determined as 0.016 min-1.
胆碱酯酶抑制剂被广泛用作杀虫剂、化学战剂和治疗阿尔茨海默病症状的药物。因此，迫切需要开发快速、灵敏、可靠的检测方法。本文报道了在薄层金电极上采用半胱胺/戊二醛/乙酰胆碱酯酶(AChE)固定层构建的用于检测胆碱酯酶抑制剂的电化学生物传感器的初步研制工作。鸢尾碱(蛇毒碱)作为试验抑制剂。采用Ellman法测定固定化酶的活性，评价酶的固定化效果。酶活性在最初的5天内降低33%，此后保持稳定至少一周。假设对底物乙酰硫代氯化胆碱(ATCl)的计时电流响应遵循michaelis - menten动力学。将生物传感器暴露于25 mM eserine中10 min后，检测到70%的酶抑制。测定抑制AChE的再激活因子为0.016 min-1。
{"title":"Electrochemical acetylcholinesterase biosensor for\u0000detection of cholinesterase inhibitors: study with\u0000eserine","authors":"N. Lokar, V. Kononenko, D. Drobne, D. Vrtacnik","doi":"10.33180/INFMIDEM2018.406","DOIUrl":"https://doi.org/10.33180/INFMIDEM2018.406","url":null,"abstract":"Cholinesterase inhibitors are widely used as pesticides, as chemical warfare agents and as drugs to treat symptoms of\u0000Alzheimer’s disease. Therefore, it is a high need to develop methods for their detection which are fast, sensitive, and reliable. This\u0000paper reports a preliminary work in the development of an electrochemical biosensor based on acetylcholinesterase (AChE) which is\u0000constructed by immobilization layers – cysteamine/glutaraldehyde/AChE on thin layer gold electrode for detection of cholinesterase\u0000inhibitors. Eserine (physostigmine) was used as a test inhibitor. The enzyme immobilization efficacy was evaluated by measuring\u0000activity of immobilized enzyme via Ellman’s method. The enzyme activity of the initial reduction of 33% in five days remained after\u0000that stable for at least one week. Chronoamperometric response to substrate acetylthiocholine chloride (ATCl) was assumed to follow\u0000Michaelis-Menten kinetics. After exposure biosensor to 25 mM eserine for 10 min, 70% inhibition of enzyme was detected. Reactivation\u0000factor of inhibited AChE was determined as 0.016 min-1.","PeriodicalId":56293,"journal":{"name":"Informacije Midem-Journal of Microelectronics Electronic Components and Materials","volume":"57 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91001148","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-02-01DOI: 10.33180/INFMIDEM2018.402
D. DavidNeelsPonKumar., Arun Samuel T.S
A verification environment to verify an ARM-based SoC is proposed in this work. This work introduces the design of a Verification Intellectual Property (VIP) of Advanced Microcontroller Bus Architecture (AMBA). AMBA protocols are today the best standards for 32-bit processor because they are well documented and can be used without royalties. The VIP provides Coverage Driven Verification (CDV) which significantly reduces the design verification time. The code coverage verification of the AHB bus master, Icache controller, Dcache controller and APB peripherals such as APB bridge, timer, UART, and ACE is done in this work. The test cases done for the APB peripherals are ACE with the mil_std_protocol, Timers for generation of interrupt and watchdog reset, UART for transmitting and receive messages, and interrupt registers for Reading and Write. The functional verification of AMBA is carried out using the Mentor Graphics Questasim tool with the system Verilog language
{"title":"Implementation of VIP for bus interface logic of\u000032-bit processor using System Verilog","authors":"D. DavidNeelsPonKumar., Arun Samuel T.S","doi":"10.33180/INFMIDEM2018.402","DOIUrl":"https://doi.org/10.33180/INFMIDEM2018.402","url":null,"abstract":"A verification environment to verify an ARM-based SoC is proposed in this work. This work introduces the design of a\u0000Verification Intellectual Property (VIP) of Advanced Microcontroller Bus Architecture (AMBA). AMBA protocols are today the best\u0000standards for 32-bit processor because they are well documented and can be used without royalties. The VIP provides Coverage Driven\u0000Verification (CDV) which significantly reduces the design verification time. The code coverage verification of the AHB bus master,\u0000Icache controller, Dcache controller and APB peripherals such as APB bridge, timer, UART, and ACE is done in this work. The test cases\u0000done for the APB peripherals are ACE with the mil_std_protocol, Timers for generation of interrupt and watchdog reset, UART for\u0000transmitting and receive messages, and interrupt registers for Reading and Write. The functional verification of AMBA is carried out\u0000using the Mentor Graphics Questasim tool with the system Verilog language","PeriodicalId":56293,"journal":{"name":"Informacije Midem-Journal of Microelectronics Electronic Components and Materials","volume":"41 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80108059","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-02-01DOI: 10.33180/INFMIDEM2018.401
M. Ramaswamy
Due to their large storage capacity and small access time static random access memory (SRAM) has become a vital part in numerous VLSI chips. Low power adequate memory configuration is a standout among the most challenging issues in SRAM design. As the technology node scaling down, leakage power utilization has turned into a noteworthy issue. In this paper a novel power gating technique, namely sleepy keeper leakage control transistor technique (SK-LCT) is proposed for a handheld gadget application. The SRAM architecture has two primary components, specifically SRAM cell and sense amplifier. The proposed SK-LCT technique is applied in both SRAM cell and sense amplifier for a new low power high speed SRAM architecture design. The outline of SRAM architecture utilizing pass transistor decoder (PT-Decoder) gives better outcomes in term of power. Simulation is done using Tanner EDA tool in 180nm technology and the results demonstrate a noteworthy change in leakage power utilization and speed.
{"title":"Proficient Static RAM design using Sleepy Keeper Leakage Control Transistor & PT-Decoder for handheld application","authors":"M. Ramaswamy","doi":"10.33180/INFMIDEM2018.401","DOIUrl":"https://doi.org/10.33180/INFMIDEM2018.401","url":null,"abstract":"Due to their large storage capacity and small access time static random access memory (SRAM) has become a vital part in\u0000numerous VLSI chips. Low power adequate memory configuration is a standout among the most challenging issues in SRAM design.\u0000As the technology node scaling down, leakage power utilization has turned into a noteworthy issue. In this paper a novel power\u0000gating technique, namely sleepy keeper leakage control transistor technique (SK-LCT) is proposed for a handheld gadget application.\u0000The SRAM architecture has two primary components, specifically SRAM cell and sense amplifier. The proposed SK-LCT technique\u0000is applied in both SRAM cell and sense amplifier for a new low power high speed SRAM architecture design. The outline of SRAM\u0000architecture utilizing pass transistor decoder (PT-Decoder) gives better outcomes in term of power. Simulation is done using Tanner\u0000EDA tool in 180nm technology and the results demonstrate a noteworthy change in leakage power utilization and speed.","PeriodicalId":56293,"journal":{"name":"Informacije Midem-Journal of Microelectronics Electronic Components and Materials","volume":"14 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2019-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73736384","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：