Pub Date : 2020-11-20DOI: 10.33180/infmidem2020.304
Mohammad Faseehuddin, Musa Ali Albrni, N. Herencsar, J. Sampe, S. Ali
In this paper, a novel electronically tunable biquadratic universal mixed-mode filter is presented. The filter is based on extra X current conveyor transconductance amplifier (EXCCTA), recently introduced by authors. The proposed filter employs two EXCCTAs, two capacitors, a switch, and four resistors. The filter can work in both multi-input-single-output (MISO) and single-input-multi-output (SIMO) configurations without change in its structure. The filter provides low-pass (LP), high-pass (HP), band-pass (BP), band-reject (BR) and all-pass (AP) responses in voltage-mode (VM), current-mode (CM), transimpedance-mode (TIM), and transadmittance-mode (TAM). The attractive features of the filter include (i) ability to operate in both MISO and SIMO configurations in all four modes, (ii) no requirement of capacitive matching, (iii) high output impedance in SIMO (CM & TAM) configuration, (iv) tunability of quality factor ( Q ) independent of natural frequency ( ) in MISO & SIMO configurations, (v) use of grounded capacitors in SIMO configuration, (vi) low output impedance for MISO (VM & TIM), (vii) high output impedance explicit current output for MISO (CM & TAM), and (viii) no requirement for double/negative input signals (voltage/current) in MISO configuration. The non-ideal gain and sensitivity analysis is also carried out to study the effects of process variations and passive components spread on filter performance. The filter is designed in Cadence Virtuoso using Silterra Malaysia 0.18µm PDK. The complete layout of the EXCCTA is designed and the parasitic extraction is done. The filter is tested at a supply voltage of ±1.25 V and the obtained results validate the theoretical findings.
本文提出了一种新型的电子可调谐双二次型通用混合模滤波器。该滤波器基于作者最近介绍的额外X电流输送跨导放大器(EXCCTA)。该滤波器采用两个exccta、两个电容器、一个开关和四个电阻。该滤波器可以在不改变其结构的情况下工作于多输入单输出(MISO)和单输入多输出(SIMO)配置中。该滤波器在电压模式(VM)、电流模式(CM)、跨阻抗模式(TIM)和跨导纳模式(TAM)下提供低通(LP)、高通(HP)、带通(BP)、带阻(BR)和全通(AP)响应。该滤波器的吸引人的特点包括(i)在所有四种模式下都能在MISO和SIMO配置中工作，(ii)不需要电容匹配，(iii) SIMO (CM和TAM)配置中的高输出阻抗，(iv)在MISO和SIMO配置中独立于固有频率的质量因子(Q)可调()在SIMO配置中使用接地电容器，(vi) MISO (VM和TIM)的低输出阻抗，(vii) MISO (CM & TAM)的高输出阻抗显式电流输出，以及(viii) MISO配置中不需要双/负输入信号(电压/电流)。通过非理想增益和灵敏度分析，研究了工艺变化和无源元件扩散对滤波器性能的影响。该滤波器在Cadence Virtuoso中使用Silterra Malaysia 0.18µm PDK设计。设计了EXCCTA的完整布局，并进行了寄生提取。在±1.25 V的电源电压下对该滤波器进行了测试，得到的结果验证了理论结果。
{"title":"Novel Electronically Tunable Biquadratic Mixed- Mode Universal Filter Capable of Operating in MISO and SIMO Configurations","authors":"Mohammad Faseehuddin, Musa Ali Albrni, N. Herencsar, J. Sampe, S. Ali","doi":"10.33180/infmidem2020.304","DOIUrl":"https://doi.org/10.33180/infmidem2020.304","url":null,"abstract":"In this paper, a novel electronically tunable biquadratic universal mixed-mode filter is presented. The filter is based on extra X current conveyor transconductance amplifier (EXCCTA), recently introduced by authors. The proposed filter employs two EXCCTAs, two capacitors, a switch, and four resistors. The filter can work in both multi-input-single-output (MISO) and single-input-multi-output (SIMO) configurations without change in its structure. The filter provides low-pass (LP), high-pass (HP), band-pass (BP), band-reject (BR) and all-pass (AP) responses in voltage-mode (VM), current-mode (CM), transimpedance-mode (TIM), and transadmittance-mode (TAM). The attractive features of the filter include (i) ability to operate in both MISO and SIMO configurations in all four modes, (ii) no requirement of capacitive matching, (iii) high output impedance in SIMO (CM & TAM) configuration, (iv) tunability of quality factor ( Q ) independent of natural frequency ( ) in MISO & SIMO configurations, (v) use of grounded capacitors in SIMO configuration, (vi) low output impedance for MISO (VM & TIM), (vii) high output impedance explicit current output for MISO (CM & TAM), and (viii) no requirement for double/negative input signals (voltage/current) in MISO configuration. The non-ideal gain and sensitivity analysis is also carried out to study the effects of process variations and passive components spread on filter performance. The filter is designed in Cadence Virtuoso using Silterra Malaysia 0.18µm PDK. The complete layout of the EXCCTA is designed and the parasitic extraction is done. The filter is tested at a supply voltage of ±1.25 V and the obtained results validate the theoretical findings.","PeriodicalId":56293,"journal":{"name":"Informacije Midem-Journal of Microelectronics Electronic Components and Materials","volume":"17 1","pages":"189-204"},"PeriodicalIF":1.2,"publicationDate":"2020-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85421953","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-11-20DOI: 10.33180/infmidem2020.305
N. Mitrović, D. Danković, Branislav Ranđelović, Z. Prijić, N. Stojadinovic
Negative bias temperature instability (NBTI) is a phenomenon commonly observed in p-channel metal-oxide semiconductor (MOS) devices simultaneously exposed to elevated temperature and negative gate voltage. This paper studies threshold voltage shift under static stress associated with the NBT stress induced buildup of both interface traps and oxide trapped charge in the commercial p-channel power VDMOSFETs IRF9520, with the goal to design an electrical model. Experiments have done with the goal to obtain data for modeling. Change of threshold voltage follow power law t n , where parameter n is different depending on the stressing phase and stressing conditions. Two modeling circuits are proposed and modeling circuit elements values are analyzed. Values of modeling circuits elements are calculated using least square method approximation conducted on obtained experimental results. Modeling results of both circuits are compared with the measured results and then further discussed.
{"title":"Modeling of Static Negative Bias Temperature Stressing in p-channel VDMOSFETs using Least Square Method","authors":"N. Mitrović, D. Danković, Branislav Ranđelović, Z. Prijić, N. Stojadinovic","doi":"10.33180/infmidem2020.305","DOIUrl":"https://doi.org/10.33180/infmidem2020.305","url":null,"abstract":"Negative bias temperature instability (NBTI) is a phenomenon commonly observed in p-channel metal-oxide semiconductor (MOS) devices simultaneously exposed to elevated temperature and negative gate voltage. This paper studies threshold voltage shift under static stress associated with the NBT stress induced buildup of both interface traps and oxide trapped charge in the commercial p-channel power VDMOSFETs IRF9520, with the goal to design an electrical model. Experiments have done with the goal to obtain data for modeling. Change of threshold voltage follow power law t n , where parameter n is different depending on the stressing phase and stressing conditions. Two modeling circuits are proposed and modeling circuit elements values are analyzed. Values of modeling circuits elements are calculated using least square method approximation conducted on obtained experimental results. Modeling results of both circuits are compared with the measured results and then further discussed.","PeriodicalId":56293,"journal":{"name":"Informacije Midem-Journal of Microelectronics Electronic Components and Materials","volume":"18 1","pages":"205-214"},"PeriodicalIF":1.2,"publicationDate":"2020-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87564929","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-11-20DOI: 10.33180/infmidem2020.303
P. Marinushkin, A. Levitsky, Fyodor Zograf, V. A. Bakhtina
This paper considers issues of modeling ultra-high frequency MEMS resonators based on acoustic Lamb waves. In addition, the analysis of factors that determine whether it is possible to increase resonators working frequency and quality factor is carried out. Influence of resonator excitation scheme and acoustic waveguide thickness for a range of piezoelectric materials (i.e. AlN, ZnO, GaN) on phase velocity for acoustic Lamb wave zero modes is investigated. As a result, we've got estimations determining dependence of resonators electromechanical coupling coefficient on their geometry.
{"title":"On the Finite-Element Analysis of Resonance MEMS Structures based on Acoustic Lamb Waves","authors":"P. Marinushkin, A. Levitsky, Fyodor Zograf, V. A. Bakhtina","doi":"10.33180/infmidem2020.303","DOIUrl":"https://doi.org/10.33180/infmidem2020.303","url":null,"abstract":"This paper considers issues of modeling ultra-high frequency MEMS resonators based on acoustic Lamb waves. In addition, the analysis of factors that determine whether it is possible to increase resonators working frequency and quality factor is carried out. Influence of resonator excitation scheme and acoustic waveguide thickness for a range of piezoelectric materials (i.e. AlN, ZnO, GaN) on phase velocity for acoustic Lamb wave zero modes is investigated. As a result, we've got estimations determining dependence of resonators electromechanical coupling coefficient on their geometry.","PeriodicalId":56293,"journal":{"name":"Informacije Midem-Journal of Microelectronics Electronic Components and Materials","volume":"30 1","pages":""},"PeriodicalIF":1.2,"publicationDate":"2020-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87754478","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-11-20DOI: 10.33180/infmidem2020.301
S. Philip, S. Palaniswami, Harikirubha Sivakumar
A computationally efficient 11 band non-uniform filter bank addressing low or moderately sloping sensorineural hearing loss - the most common type of hearing problem- is proposed. This structure is suitable for low cost, small area implementations of hearing aids. The computational efficiency is achieved by adopting the Frequency Response Masking technique, which uses only two prototype filters with a total of 19 multipliers at 80dB stopband attenuation for the design of entire non-uniform filter bank. The computational complexity analysis shows that the proposed method provides about a 70-90% reduction in computational resources compared to non-FRM methods and about a 40-80% reduction in computational resources compared to the other FRM methods. The audiogram matching performance analysis shows that the matching error of the proposed filter bank is negligible even without optimization. The delay performance of the filter bank is acceptable for both Closed Canal Fittings and Open Canal Fittings.
{"title":"A Computationally Efficient 11 Band Non-Uniform Filter Bank for Hearing Aids Targeting Moderately Sloping Sensorineural Hearing Loss","authors":"S. Philip, S. Palaniswami, Harikirubha Sivakumar","doi":"10.33180/infmidem2020.301","DOIUrl":"https://doi.org/10.33180/infmidem2020.301","url":null,"abstract":"A computationally efficient 11 band non-uniform filter bank addressing low or moderately sloping sensorineural hearing loss - the most common type of hearing problem- is proposed. This structure is suitable for low cost, small area implementations of hearing aids. The computational efficiency is achieved by adopting the Frequency Response Masking technique, which uses only two prototype filters with a total of 19 multipliers at 80dB stopband attenuation for the design of entire non-uniform filter bank. The computational complexity analysis shows that the proposed method provides about a 70-90% reduction in computational resources compared to non-FRM methods and about a 40-80% reduction in computational resources compared to the other FRM methods. The audiogram matching performance analysis shows that the matching error of the proposed filter bank is negligible even without optimization. The delay performance of the filter bank is acceptable for both Closed Canal Fittings and Open Canal Fittings.","PeriodicalId":56293,"journal":{"name":"Informacije Midem-Journal of Microelectronics Electronic Components and Materials","volume":"11 1","pages":"153-168"},"PeriodicalIF":1.2,"publicationDate":"2020-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87133110","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-09-22DOI: 10.33180/infmidem2020.204
Ali Rahnamaei
In this article, the design fashion of high-speed 5-2 and 6-2 compressors along with their analysis, has been discussed. With the help of combinational logic consisting of the 4-2 compressor and 3-2 counter structures, a high-performance structure for 6-2 compressor has been obtained which shows significant speed improvement over previous architectures. The optimization is achieved by reducing the carry rippling issue between adjacent compressor blocks. Also, the proposed 6-2 compressor with some modifications will turn into a 5-2 compressor in which latency of the critical path has considerably been reduced, illustrating the superiority of designed circuits. The delay of proposed 5-2 and 6-2 structures is equal to 3.5 and 4 XOR logic gates, respectively, demonstrating speed boosting of 15% and 20% compared to the best-reported architectures. In addition, the power consumption and transistor count of proposed circuits are in reasonable level. Therefore, by considering the Power-Delay Product (PDP), our work will be a good choice for high-speed parallel multiplier design. Post-layout simulation results based on TSMC 90nm standard CMOS process and 0.9V power supply have been presented to confirm the correct functionality of the implemented compressors. These results have also been used as a fair comparison infrastructure between the proposed works and redesignated architectures of previously reported schemes.
{"title":"CMOS High-Performance 5-2 and 6-2 Compressors for High-Speed Parallel Multipliers","authors":"Ali Rahnamaei","doi":"10.33180/infmidem2020.204","DOIUrl":"https://doi.org/10.33180/infmidem2020.204","url":null,"abstract":"In this article, the design fashion of high-speed 5-2 and 6-2 compressors along with their analysis, has been discussed. With the help of combinational logic consisting of the 4-2 compressor and 3-2 counter structures, a high-performance structure for 6-2 compressor has been obtained which shows significant speed improvement over previous architectures. The optimization is achieved by reducing the carry rippling issue between adjacent compressor blocks. Also, the proposed 6-2 compressor with some modifications will turn into a 5-2 compressor in which latency of the critical path has considerably been reduced, illustrating the superiority of designed circuits. The delay of proposed 5-2 and 6-2 structures is equal to 3.5 and 4 XOR logic gates, respectively, demonstrating speed boosting of 15% and 20% compared to the best-reported architectures. In addition, the power consumption and transistor count of proposed circuits are in reasonable level. Therefore, by considering the Power-Delay Product (PDP), our work will be a good choice for high-speed parallel multiplier design. Post-layout simulation results based on TSMC 90nm standard CMOS process and 0.9V power supply have been presented to confirm the correct functionality of the implemented compressors. These results have also been used as a fair comparison infrastructure between the proposed works and redesignated architectures of previously reported schemes.","PeriodicalId":56293,"journal":{"name":"Informacije Midem-Journal of Microelectronics Electronic Components and Materials","volume":"14 1","pages":"115-124"},"PeriodicalIF":1.2,"publicationDate":"2020-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85354111","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-09-22DOI: 10.33180/infmidem2020.202
Alireza Abolhasani, Morteza Mousazadeh, A. Khoei
In in this study ultrasonic method was applied for measuring blood pressure (BP). First, a novel method is proposed to measure mean arterial pressure (MAP), diastolic blood pressure (DBP) and systolic blood pressure (SBP) using ultrasonic sensors. The proposed algorithm is implemented by measuring the diameter of the artery and the speed of blood flow based on Doppler physical phenomena so the blood pressure can be calculated. The results of the proposed algorithm for MAP, SBP, and DBP hypertension analyses were evaluated with the results of Association for the Advancement of Medical Instrumentation (AAMI standard) for all three cases and their mean error rate for the worst case was -0.233mmHg and the standard deviation for 422 samples taken from individuals in the worst case was 4.53 mmHg that meets the standard requirements. Also, according to the British Hypertension Society (BHS) standard, a proposed algorithm for estimating blood pressure for all three cases of MAP, DBP, and SBP has Grade A, indicating high accuracy in measuring and using the most effective variables in the diagnosis of hypertension in the human body. The proposed algorithm in BP estimation is non-invasive, cuff-less, no calibration, and only based on using the ultrasonic sensor.
{"title":"Real-time, Cuff-less and Non-invasiveBlood Pressure Monitoring","authors":"Alireza Abolhasani, Morteza Mousazadeh, A. Khoei","doi":"10.33180/infmidem2020.202","DOIUrl":"https://doi.org/10.33180/infmidem2020.202","url":null,"abstract":"In in this study ultrasonic method was applied for measuring blood pressure (BP). First, a novel method is proposed to measure mean arterial pressure (MAP), diastolic blood pressure (DBP) and systolic blood pressure (SBP) using ultrasonic sensors. The proposed algorithm is implemented by measuring the diameter of the artery and the speed of blood flow based on Doppler physical phenomena so the blood pressure can be calculated. The results of the proposed algorithm for MAP, SBP, and DBP hypertension analyses were evaluated with the results of Association for the Advancement of Medical Instrumentation (AAMI standard) for all three cases and their mean error rate for the worst case was -0.233mmHg and the standard deviation for 422 samples taken from individuals in the worst case was 4.53 mmHg that meets the standard requirements. Also, according to the British Hypertension Society (BHS) standard, a proposed algorithm for estimating blood pressure for all three cases of MAP, DBP, and SBP has Grade A, indicating high accuracy in measuring and using the most effective variables in the diagnosis of hypertension in the human body. The proposed algorithm in BP estimation is non-invasive, cuff-less, no calibration, and only based on using the ultrasonic sensor.","PeriodicalId":56293,"journal":{"name":"Informacije Midem-Journal of Microelectronics Electronic Components and Materials","volume":"34 1","pages":"87-104"},"PeriodicalIF":1.2,"publicationDate":"2020-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78947114","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-09-22DOI: 10.33180/infmidem2020.203
M. Bhuiyan
The incompatibility between current RFID standards has led to the need for universal and Wi-Fi compatible RFID for IoT applications. Such a universal RFID requires an SPDT and an LNA to direct and amplify the received raw signal by the antenna. The SPDT suffers from low isolation, high insertion loss and low power handling capacity whereas the LNA suffers from bulky die area, lesser Q factor, limited tuning flexibility etc. because of passive inductor usage in current generation of devices. In this research, nano-CMOS inductorless SPDT and LNA designs are proposed. The SPDT adopts a series-shunt topology along with parallel resonant circuits and resistive body floating in order to achieve improved insertion loss and isolation performance whereas the LNA design is implemented with the gyrator concept in which the frequency selective tank circuit is formed with an active inductor accompanied by the buffer circuits. The post-layout simulation results, utilizing 90nm CMOS process of cadence virtuoso, exhibit that our SPDT design accomplishes 0.83dB insertion loss, a 45.3dB isolation, and a 11.3dBm power-handling capacity whereas the LNA achieves a peak gain of 33dB, bandwidth of 30MHz and NF of 6.6dB at 2.45GHz center frequency. Both the SPDT and LNA have very compact layout which are 0.003mm 2 and 127.7 μm 2 , respectively. Such SPDT and LNA design will boost the widespread adaptation of Wi-Fi-compatible IoT RFID technology.
{"title":"CMOS series-shunt single-pole double-throw transmit/receive switch and low noise amplifier design for internet of things based radio frequency identification devices","authors":"M. Bhuiyan","doi":"10.33180/infmidem2020.203","DOIUrl":"https://doi.org/10.33180/infmidem2020.203","url":null,"abstract":"The incompatibility between current RFID standards has led to the need for universal and Wi-Fi compatible RFID for IoT applications. Such a universal RFID requires an SPDT and an LNA to direct and amplify the received raw signal by the antenna. The SPDT suffers from low isolation, high insertion loss and low power handling capacity whereas the LNA suffers from bulky die area, lesser Q factor, limited tuning flexibility etc. because of passive inductor usage in current generation of devices. In this research, nano-CMOS inductorless SPDT and LNA designs are proposed. The SPDT adopts a series-shunt topology along with parallel resonant circuits and resistive body floating in order to achieve improved insertion loss and isolation performance whereas the LNA design is implemented with the gyrator concept in which the frequency selective tank circuit is formed with an active inductor accompanied by the buffer circuits. The post-layout simulation results, utilizing 90nm CMOS process of cadence virtuoso, exhibit that our SPDT design accomplishes 0.83dB insertion loss, a 45.3dB isolation, and a 11.3dBm power-handling capacity whereas the LNA achieves a peak gain of 33dB, bandwidth of 30MHz and NF of 6.6dB at 2.45GHz center frequency. Both the SPDT and LNA have very compact layout which are 0.003mm 2 and 127.7 μm 2 , respectively. Such SPDT and LNA design will boost the widespread adaptation of Wi-Fi-compatible IoT RFID technology.","PeriodicalId":56293,"journal":{"name":"Informacije Midem-Journal of Microelectronics Electronic Components and Materials","volume":"9 1","pages":"105-114"},"PeriodicalIF":1.2,"publicationDate":"2020-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90348406","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-09-22DOI: 10.33180/infmidem2020.206
M. Başak, E. Özer, F. Kaçar, Deniz Ozenli
Analog multiplication circuits are very important block structures which are widely used in analog signal applications. In analog multiplication circuits, low power consumption is expected with wide bandwidth, low nonlinearity and high input range according to supply voltage. In this study, folded Gilbert cell structure was resized using dynamic threshold MOS (DTMOS) transistors and low power consumption and high bandwidth have been obtained. In improver, the bandwidth was obtained at values of 3.63 GHz, temperature variation, total harmonic distortion and intermodulation products of the proposed multiplier were examined. Monte Carlo analysis was performed and error analysis of the dimensioning of the circuit was examined. In summation to the high bandwidth, a low power consumption of 44.5 µW has been achieved and the supply voltage of 0.2 V has been achieved to operate in full-scale input range.
{"title":"DTMOS Based High Bandwidth Four-Quadrant Analog Multiplier","authors":"M. Başak, E. Özer, F. Kaçar, Deniz Ozenli","doi":"10.33180/infmidem2020.206","DOIUrl":"https://doi.org/10.33180/infmidem2020.206","url":null,"abstract":"Analog multiplication circuits are very important block structures which are widely used in analog signal applications. In analog multiplication circuits, low power consumption is expected with wide bandwidth, low nonlinearity and high input range according to supply voltage. In this study, folded Gilbert cell structure was resized using dynamic threshold MOS (DTMOS) transistors and low power consumption and high bandwidth have been obtained. In improver, the bandwidth was obtained at values of 3.63 GHz, temperature variation, total harmonic distortion and intermodulation products of the proposed multiplier were examined. Monte Carlo analysis was performed and error analysis of the dimensioning of the circuit was examined. In summation to the high bandwidth, a low power consumption of 44.5 µW has been achieved and the supply voltage of 0.2 V has been achieved to operate in full-scale input range.","PeriodicalId":56293,"journal":{"name":"Informacije Midem-Journal of Microelectronics Electronic Components and Materials","volume":"1 1","pages":"137-146"},"PeriodicalIF":1.2,"publicationDate":"2020-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88705460","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-09-22DOI: 10.33180/infmidem2020.205
O. Channumsin
This article relates to the realization of voltage-mode and/or current-mode multifunction biquadratic filter and quadrature oscillator circuits each using one voltage differencing gain amplifier (VDGA), two resistors and two grounded capacitors. The proposed dual-mode filter having one output and three inputs can provide the three standard biquadratic transfer functions with both voltage and current output filter responses simultaneously. It also has the independent tuning of the angular resonance frequency and the quality factor . With a slight modification of the proposed filter, a new dual-mode quadrature sinusoidal oscillator can be obtained. The proposed quadrature oscillator provides orthogonal resistive/electronic control of both oscillation condition and oscillation frequency. Non-ideal and parasitic conditions are also examined and their effects on the circuit performance are discussed. In order to confirm the theory, several computer simulation results with PSPICE program are given .
{"title":"Single VDGA-Based Dual-Mode Multifunction Biquadratic Filter and Quadrature Sinusoidal Oscillator","authors":"O. Channumsin","doi":"10.33180/infmidem2020.205","DOIUrl":"https://doi.org/10.33180/infmidem2020.205","url":null,"abstract":"This article relates to the realization of voltage-mode and/or current-mode multifunction biquadratic filter and quadrature oscillator circuits each using one voltage differencing gain amplifier (VDGA), two resistors and two grounded capacitors. The proposed dual-mode filter having one output and three inputs can provide the three standard biquadratic transfer functions with both voltage and current output filter responses simultaneously. It also has the independent tuning of the angular resonance frequency and the quality factor . With a slight modification of the proposed filter, a new dual-mode quadrature sinusoidal oscillator can be obtained. The proposed quadrature oscillator provides orthogonal resistive/electronic control of both oscillation condition and oscillation frequency. Non-ideal and parasitic conditions are also examined and their effects on the circuit performance are discussed. In order to confirm the theory, several computer simulation results with PSPICE program are given .","PeriodicalId":56293,"journal":{"name":"Informacije Midem-Journal of Microelectronics Electronic Components and Materials","volume":"36 1","pages":"125-136"},"PeriodicalIF":1.2,"publicationDate":"2020-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90065784","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-09-20DOI: 10.33180/infmidem2020.201
Elango Sekar, Sampath Palaniswami
The Residue Number System (RNS) characterize large integer numbers into smaller residues using moduli sets to enhance the performance of digital cryptosystems. A parallel Signed Residue Multiplication (SRM) algorithm, VLSI hierarchical array architecture for balanced (2 n -1, 2 n , 2 n +1) and unbalanced (2 k -1, 2 k , 2 k +1) word-length moduli are proposed which is capable of handling signed input numbers. Balanced 2 n -1 SRM is used as a reference to design an unbalanced 2 k -1 and 2 k +1. The synthesized results show that the proposed 2 n -1 SRM architecture achieves 17% of the area, 26% of speed and 24% of Power Delay Product (PDP) improvement compared to the Modified Booth Encoded (MBE) architectures discussed in the literature. The proposed 2 n +1 SRM architecture achieves 23% of the area, 20% of speed and 22% of PDP improvement compared to recent counterparts. There is a significant improvement in the results due to the fully parallel hierarchical approach adopted for the design which is hardly attempted for signed numbers using array architectures. Finally, the proposed SRM modules are used to design {2 n -1, 2 n , 2 n +1} special moduli set based RNS processor and the real-time verification is performed on Zynq (XC7Z020CLG484-1) Field Programmable Gate Array (FPGA).
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