Pub Date : 2007-10-01DOI: 10.1109/ICCD.2007.4601875
Nannan He, M. Hsiao
We present a new verification approach that applies aggressive program slicing and a proof-based abstraction-refinement strategy to enhance the scalability of bounded model checking of embedded software. While many software model-checking tools use program slicing as a separate or optional step, our program slicing is integrated in the model construction and reduction process. And it is combined with the compilation optimization techniques so to compute a more accurate slice. We also explore a proof-based abstraction-refinement strategy using the under/overapproximation on our proposed software model, and propose a heuristic method of deciding new encoding size to refine the under-approximation. Experiments on C programs from wireless cognitive radio systems show this approach can greatly reduce the model size and shorten the solving time by the SAT-solver.
{"title":"Bounded model checking of embedded software in wireless cognitive radio systems","authors":"Nannan He, M. Hsiao","doi":"10.1109/ICCD.2007.4601875","DOIUrl":"https://doi.org/10.1109/ICCD.2007.4601875","url":null,"abstract":"We present a new verification approach that applies aggressive program slicing and a proof-based abstraction-refinement strategy to enhance the scalability of bounded model checking of embedded software. While many software model-checking tools use program slicing as a separate or optional step, our program slicing is integrated in the model construction and reduction process. And it is combined with the compilation optimization techniques so to compute a more accurate slice. We also explore a proof-based abstraction-refinement strategy using the under/overapproximation on our proposed software model, and propose a heuristic method of deciding new encoding size to refine the under-approximation. Experiments on C programs from wireless cognitive radio systems show this approach can greatly reduce the model size and shorten the solving time by the SAT-solver.","PeriodicalId":6306,"journal":{"name":"2007 25th International Conference on Computer Design","volume":"95 1","pages":"19-24"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80541924","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-01DOI: 10.1109/ICCD.2007.4601941
Paul D. Bryan, T. Conte
Microarchitectural simulation is orders of magnitude slower than native execution. As more elements are accurately modeled, problems associated with slow simulation are further exacerbated. Given these issues, many researchers have devised sampling techniques to reduce simulation time. When cluster sampling techniques are used, care must be taken to remove sampling and non-sampling biases. Researchers have devised clever methods for effectively reducing non-sampling bias, but little work has been proposed for efficient reduction of sampling bias (sampling regimen design). Traditionally, sampling regimen design has been an iterative process that required a full workload simulation for error comparison. In this study, a single-pass simulation technique for sampling regimen design is proposed. Using this method, thousands of sampling regimen candidates can be simultaneously evaluated. With this technique, simulation speed was increased by an average factor of 17 with a maximum increase of 73 times relative to the total workload simulation. Additionally, this technique allows the user to effectively estimate the sample error without running the entire workload.
{"title":"Combining cluster sampling with single pass methods for efficient sampling regimen design","authors":"Paul D. Bryan, T. Conte","doi":"10.1109/ICCD.2007.4601941","DOIUrl":"https://doi.org/10.1109/ICCD.2007.4601941","url":null,"abstract":"Microarchitectural simulation is orders of magnitude slower than native execution. As more elements are accurately modeled, problems associated with slow simulation are further exacerbated. Given these issues, many researchers have devised sampling techniques to reduce simulation time. When cluster sampling techniques are used, care must be taken to remove sampling and non-sampling biases. Researchers have devised clever methods for effectively reducing non-sampling bias, but little work has been proposed for efficient reduction of sampling bias (sampling regimen design). Traditionally, sampling regimen design has been an iterative process that required a full workload simulation for error comparison. In this study, a single-pass simulation technique for sampling regimen design is proposed. Using this method, thousands of sampling regimen candidates can be simultaneously evaluated. With this technique, simulation speed was increased by an average factor of 17 with a maximum increase of 73 times relative to the total workload simulation. Additionally, this technique allows the user to effectively estimate the sample error without running the entire workload.","PeriodicalId":6306,"journal":{"name":"2007 25th International Conference on Computer Design","volume":"6 1","pages":"472-479"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91072438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-01DOI: 10.1109/ICCD.2007.4601957
N. Chabini, W. Wolf
An important problem is how to carry out register binding such that any register has to be bound to a set of variables such that the difference between their sizes is as small as possible. For the case of hardware implementations, satisfying this latter constraint will allow to reduce the complexity of the clock generation tree, and saving area occupied by the registers which is very important for the case of system-on-chip and some embedded systems. When registers are already built, satisfying this latter constraint would allow reducing power consumption due to useless switching activities that will happen into any register that is bound to variables with different sizes. Assuming that the size in bits of any variable is known, we propose in this paper exact algorithms to optimally solve this problem for the case of acyclic graphs. An extended version of this problem is how to solve it while controlling the number of variables to be assigned to a same register. We also propose exact algorithms to optimally solve this latter version of the problem. Experimental results are provided. We also test the impact of the proposed approach in the case of a hardware implementation using the design analyzer tool from Synopsys Inc.. Obtained results have shown that both area and power consumption have been reduced.
{"title":"Register binding guided by the size of variables","authors":"N. Chabini, W. Wolf","doi":"10.1109/ICCD.2007.4601957","DOIUrl":"https://doi.org/10.1109/ICCD.2007.4601957","url":null,"abstract":"An important problem is how to carry out register binding such that any register has to be bound to a set of variables such that the difference between their sizes is as small as possible. For the case of hardware implementations, satisfying this latter constraint will allow to reduce the complexity of the clock generation tree, and saving area occupied by the registers which is very important for the case of system-on-chip and some embedded systems. When registers are already built, satisfying this latter constraint would allow reducing power consumption due to useless switching activities that will happen into any register that is bound to variables with different sizes. Assuming that the size in bits of any variable is known, we propose in this paper exact algorithms to optimally solve this problem for the case of acyclic graphs. An extended version of this problem is how to solve it while controlling the number of variables to be assigned to a same register. We also propose exact algorithms to optimally solve this latter version of the problem. Experimental results are provided. We also test the impact of the proposed approach in the case of a hardware implementation using the design analyzer tool from Synopsys Inc.. Obtained results have shown that both area and power consumption have been reduced.","PeriodicalId":6306,"journal":{"name":"2007 25th International Conference on Computer Design","volume":"31 1","pages":"587-594"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90108705","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-01DOI: 10.1109/ICCD.2007.4601904
K. Vandrup
This session will include two invited industry presentations on challenges ahead in the design, manufacturing, and testing of wireless communications devices.
本次会议将包括两场受邀的行业演讲，内容涉及无线通信设备的设计、制造和测试方面的挑战。
{"title":"The challenge in testing MIMO in a Wi-Fi or WiMAX context","authors":"K. Vandrup","doi":"10.1109/ICCD.2007.4601904","DOIUrl":"https://doi.org/10.1109/ICCD.2007.4601904","url":null,"abstract":"This session will include two invited industry presentations on challenges ahead in the design, manufacturing, and testing of wireless communications devices.","PeriodicalId":6306,"journal":{"name":"2007 25th International Conference on Computer Design","volume":"69 1","pages":"215-215"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73443112","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-01DOI: 10.1109/ICCD.2007.4601915
C. Tsen, S. González-Navarro, M. Schulte
Because of the growing importance of decimal floating-point (DFP) arithmetic, specifications for it are included in the IEEE Draft Standard for Floating-point Arithmetic (IEEE P754). In this paper, we present a novel algorithm and hardware design for a DFP adder. The adder performs addition and subtraction on 64-bit operands that use the IEEE P754 binary encoding of DFP numbers, widely known as the binary integer decimal (BID) encoding. The BID adder uses a novel hardware component for decimal digit counting and an enhanced version of a previously published BID rounding unit. By adding more sophisticated control, operations are performed with variable latency to optimize for common cases. We show that a BID-based DFP adder design can be achieved with a modest area increase compared to a single 2-stage pipelined 64-bit fixed-point multiplier. Over 70% of the BID adderpsilas area is due the 64-bit fixed-point multiplier, which can be shared with a binary floating-point multiplier and hardware for other DFP operations. To our knowledge, this is the first hardware design for adding and subtracting IEEE P754 BID-encoded DFP numbers.
{"title":"Hardware design of a Binary Integer Decimal-based floating-point adder","authors":"C. Tsen, S. González-Navarro, M. Schulte","doi":"10.1109/ICCD.2007.4601915","DOIUrl":"https://doi.org/10.1109/ICCD.2007.4601915","url":null,"abstract":"Because of the growing importance of decimal floating-point (DFP) arithmetic, specifications for it are included in the IEEE Draft Standard for Floating-point Arithmetic (IEEE P754). In this paper, we present a novel algorithm and hardware design for a DFP adder. The adder performs addition and subtraction on 64-bit operands that use the IEEE P754 binary encoding of DFP numbers, widely known as the binary integer decimal (BID) encoding. The BID adder uses a novel hardware component for decimal digit counting and an enhanced version of a previously published BID rounding unit. By adding more sophisticated control, operations are performed with variable latency to optimize for common cases. We show that a BID-based DFP adder design can be achieved with a modest area increase compared to a single 2-stage pipelined 64-bit fixed-point multiplier. Over 70% of the BID adderpsilas area is due the 64-bit fixed-point multiplier, which can be shared with a binary floating-point multiplier and hardware for other DFP operations. To our knowledge, this is the first hardware design for adding and subtracting IEEE P754 BID-encoded DFP numbers.","PeriodicalId":6306,"journal":{"name":"2007 25th International Conference on Computer Design","volume":"18 1","pages":"288-295"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78400419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-01DOI: 10.1109/ICCD.2007.4601948
Mingjing Chen, A. Orailoglu
A methodology for constructing circuit-level mismatch models and performing yield optimization is presented for CMOS analog circuits. The methodology combines statistical techniques with direct investigation of circuit behavior, and achieves model simplification and computational efficiency while ensuring sufficient accuracy. The circuit-level mismatch model can be used in performance characterization and yield estimation, both important in providing information for circuit reliability analysis. The proposed yield optimization technique consists of constructing and refining a yield model over the designable parameters, and ensures fast convergence to the global optimal design. The experimental results on two representative circuits confirm the efficiency and effectiveness of the proposed method.
{"title":"Circuit-level mismatch modelling and yield optimization for CMOS analog circuits","authors":"Mingjing Chen, A. Orailoglu","doi":"10.1109/ICCD.2007.4601948","DOIUrl":"https://doi.org/10.1109/ICCD.2007.4601948","url":null,"abstract":"A methodology for constructing circuit-level mismatch models and performing yield optimization is presented for CMOS analog circuits. The methodology combines statistical techniques with direct investigation of circuit behavior, and achieves model simplification and computational efficiency while ensuring sufficient accuracy. The circuit-level mismatch model can be used in performance characterization and yield estimation, both important in providing information for circuit reliability analysis. The proposed yield optimization technique consists of constructing and refining a yield model over the designable parameters, and ensures fast convergence to the global optimal design. The experimental results on two representative circuits confirm the efficiency and effectiveness of the proposed method.","PeriodicalId":6306,"journal":{"name":"2007 25th International Conference on Computer Design","volume":"19 1","pages":"526-532"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78477194","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-01DOI: 10.1109/ICCD.2007.4601882
A. Kahng, S. Kang, Wei Li, Bao Liu
DSM and nanometer VLSI designs are subject to an increasingly significant thermal effect on VLSI circuit lifetime and performance variation, which can be effectively subdued by VLSI placement. We propose analytical placement for accurate and efficient VLSI thermal optimization, and propose minimized maximum on-chip temperature as the thermal optimization objective for improved VLSI lifetime and minimized performance variation. We develop an effective analytical thermal placement technique, as well as an improved analytical placement technique with a new cell spreading function. Our experimental results show that our proposed analytical thermal placement achieves 17.85% and 30.77% maximum on-chip temperature variation reduction as well as 4.61% and 0.45% wirelength reduction respectively for the two industry design test cases compared with thermal-oblivious analytical placement, e.g., APlace.
{"title":"Analytical thermal placement for VLSI lifetime improvement and minimum performance variation","authors":"A. Kahng, S. Kang, Wei Li, Bao Liu","doi":"10.1109/ICCD.2007.4601882","DOIUrl":"https://doi.org/10.1109/ICCD.2007.4601882","url":null,"abstract":"DSM and nanometer VLSI designs are subject to an increasingly significant thermal effect on VLSI circuit lifetime and performance variation, which can be effectively subdued by VLSI placement. We propose analytical placement for accurate and efficient VLSI thermal optimization, and propose minimized maximum on-chip temperature as the thermal optimization objective for improved VLSI lifetime and minimized performance variation. We develop an effective analytical thermal placement technique, as well as an improved analytical placement technique with a new cell spreading function. Our experimental results show that our proposed analytical thermal placement achieves 17.85% and 30.77% maximum on-chip temperature variation reduction as well as 4.61% and 0.45% wirelength reduction respectively for the two industry design test cases compared with thermal-oblivious analytical placement, e.g., APlace.","PeriodicalId":6306,"journal":{"name":"2007 25th International Conference on Computer Design","volume":"22 1","pages":"71-77"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72844951","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-01DOI: 10.1109/ICCD.2007.4601946
E. Acar, S. Ozev
As radio frequency (RF) devices become more complex, the specifications become more stringent. In order to guarantee successful operation and compliance to certain specifications, digital correction techniques that compensate the device impairments are needed. In this paper, we present an analytical digital in-phase (I) and quadrature (Q) imbalance and non-linear compression correction methodology that improves the system bit error rate (BER). The gain and phase imbalances are corrected by using the gain and phase imbalance test data obtained during the product testing. The non-linear compression term is removed using Newton's method. The proposed test methodology is applicable for both burst based systems and continuous systems. Simulation results indicate that the proposed method improves the BER even under harsh noise contamination. The computational overhead of the compensation technique is minimal.
{"title":"Digital calibration of RF transceivers for I-Q imbalances and nonlinearity","authors":"E. Acar, S. Ozev","doi":"10.1109/ICCD.2007.4601946","DOIUrl":"https://doi.org/10.1109/ICCD.2007.4601946","url":null,"abstract":"As radio frequency (RF) devices become more complex, the specifications become more stringent. In order to guarantee successful operation and compliance to certain specifications, digital correction techniques that compensate the device impairments are needed. In this paper, we present an analytical digital in-phase (I) and quadrature (Q) imbalance and non-linear compression correction methodology that improves the system bit error rate (BER). The gain and phase imbalances are corrected by using the gain and phase imbalance test data obtained during the product testing. The non-linear compression term is removed using Newton's method. The proposed test methodology is applicable for both burst based systems and continuous systems. Simulation results indicate that the proposed method improves the BER even under harsh noise contamination. The computational overhead of the compensation technique is minimal.","PeriodicalId":6306,"journal":{"name":"2007 25th International Conference on Computer Design","volume":"113 1","pages":"512-517"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84356835","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-01DOI: 10.1109/ICCD.2007.4601886
J. Wong, A. Davoodi, Vishal Khandelwal, Ankur Srivastava, M. Potkonjak
We have developed a new statistical timing analysis approach that does not impose any assumptions on the nature of manufacturing variability and takes into account an arbitrary model of spatial correlation as well as all types of functional correlations (e.g. reconvergence-based correlations). The starting point for statistical timing analysis is small scale Monte Carlo (MC) simulation. In order to speed-up the MC simulation process we use stratified balanced sampling and postprocessing of the simulation data using non-parametric kernel estimation. The MC simulation and the statistical analysis procedure are interleaved with the calculation of the critical paths. In order to speed up simulation, we identify and simulate only gates relevant for calculation of the clock cycle time. The application of statistical techniques enable not only accurate statistical timing analysis, but also stability and scalability analysis. The approach is evaluated using MCNC benchmarks and yields more than six orders of magnitude speed improvement compared with the standard MC simulation.
{"title":"Statistical timing analysis using Kernel smoothing","authors":"J. Wong, A. Davoodi, Vishal Khandelwal, Ankur Srivastava, M. Potkonjak","doi":"10.1109/ICCD.2007.4601886","DOIUrl":"https://doi.org/10.1109/ICCD.2007.4601886","url":null,"abstract":"We have developed a new statistical timing analysis approach that does not impose any assumptions on the nature of manufacturing variability and takes into account an arbitrary model of spatial correlation as well as all types of functional correlations (e.g. reconvergence-based correlations). The starting point for statistical timing analysis is small scale Monte Carlo (MC) simulation. In order to speed-up the MC simulation process we use stratified balanced sampling and postprocessing of the simulation data using non-parametric kernel estimation. The MC simulation and the statistical analysis procedure are interleaved with the calculation of the critical paths. In order to speed up simulation, we identify and simulate only gates relevant for calculation of the clock cycle time. The application of statistical techniques enable not only accurate statistical timing analysis, but also stability and scalability analysis. The approach is evaluated using MCNC benchmarks and yields more than six orders of magnitude speed improvement compared with the standard MC simulation.","PeriodicalId":6306,"journal":{"name":"2007 25th International Conference on Computer Design","volume":"13 1","pages":"97-102"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87579038","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-01DOI: 10.1109/ICCD.2007.4601927
Chong Zhao, S. Dey
This paper addresses the aggregated effects of two types of variations that contribute to the reliability degradation. The first one is the increasing level of process variation; the second one is one particular type of environmental variation - the radiation-induced soft error. Their simultaneous presence can cause large negative performance impact. We present a statistical approach to model the generation and propagation of a transient soft error inside combinational circuits considering the existence of inter-die channel length variation in CMOS digital circuits. Experiment results have demonstrated that channel length variation can significantly aggravate the soft error effect, which can be accurately evaluated using the proposed methodology.
{"title":"Modeling soft error effects considering process variations","authors":"Chong Zhao, S. Dey","doi":"10.1109/ICCD.2007.4601927","DOIUrl":"https://doi.org/10.1109/ICCD.2007.4601927","url":null,"abstract":"This paper addresses the aggregated effects of two types of variations that contribute to the reliability degradation. The first one is the increasing level of process variation; the second one is one particular type of environmental variation - the radiation-induced soft error. Their simultaneous presence can cause large negative performance impact. We present a statistical approach to model the generation and propagation of a transient soft error inside combinational circuits considering the existence of inter-die channel length variation in CMOS digital circuits. Experiment results have demonstrated that channel length variation can significantly aggravate the soft error effect, which can be accurately evaluated using the proposed methodology.","PeriodicalId":6306,"journal":{"name":"2007 25th International Conference on Computer Design","volume":"122 1","pages":"376-381"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82675353","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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