Pub Date : 2012-11-05DOI: 10.1109/TEST.2012.6401528
P. Nigh
A key issue is how advanced technologies are changing the way we do Testing and the Test Industry in general. There are many reports that the failure mechanisms are changing — and therefore Test much change also in response. For example, it has been reported that systematic feature-driven failures are more prevalent than physical spot defectswhich have historically been targeted during Testing. Advanced technologies are expected to drive Testing to fundamental changes in the Test process. For example, Test will assume more responsibility over time in “product personalization” — customizing each chip based on repair/redundant elements, power/performance tuning and new types of fee-dforward data. (e.g., inline test results, optical inspection data) “Adaptive Testing” will enable automated data-driven methods to optimize Quality/Reliability/Yield Loss/Test Time trad-e offs in real-time during production Testing. There are also emerging changes due to the foundry / fables semiconductor model where Testing requirements may be jointly defined among foundries, IP providers, the chip design/integrator and manufacturing test engineerin. g Clearly, there must be more data shared across companies in the End-to-End supply chain … how will this change testing? In this panel, a set of industry experts will describe their experience with advanced technoloyg nodes (32nm/28nm) and how Testing is changing for these nodes. The discussion will range from specific examples of new failures modes … to changes in Test to detect these failure modes … to broader Test process changes. The panel will also address questions like the following: · What are 1–2 examples of new failure mechanisms that you found at 32nm/28nm ? · How did you change testing because of these new defect types/failure mechanisms ? · What new method of “statistical testing” (Adaptive Testing) have you recently started using ? · 3DIC testing — is it really different ? If so, why ? · Product personalization — is this becoming more prevalent ? If so, what are the new drivers & methods ? · Power/performance optimization — is this driving major changes to the Testing process ? If so, what changes ? · Reliability defect screening — are high voltage & high temperature accelerating still effective & required ? · How should the Test industry change to drive improvements to the End-to-End Test process ? · e.g., more rapid, more detailed, real-time cross-company data sharing?
{"title":"How are failure modes, defect types and test methods changing for 32nm/28nm technologies and beyond?","authors":"P. Nigh","doi":"10.1109/TEST.2012.6401528","DOIUrl":"https://doi.org/10.1109/TEST.2012.6401528","url":null,"abstract":"A key issue is how advanced technologies are changing the way we do Testing and the Test Industry in general. There are many reports that the failure mechanisms are changing — and therefore Test much change also in response. For example, it has been reported that systematic feature-driven failures are more prevalent than physical spot defectswhich have historically been targeted during Testing. Advanced technologies are expected to drive Testing to fundamental changes in the Test process. For example, Test will assume more responsibility over time in “product personalization” — customizing each chip based on repair/redundant elements, power/performance tuning and new types of fee-dforward data. (e.g., inline test results, optical inspection data) “Adaptive Testing” will enable automated data-driven methods to optimize Quality/Reliability/Yield Loss/Test Time trad-e offs in real-time during production Testing. There are also emerging changes due to the foundry / fables semiconductor model where Testing requirements may be jointly defined among foundries, IP providers, the chip design/integrator and manufacturing test engineerin. g Clearly, there must be more data shared across companies in the End-to-End supply chain … how will this change testing? In this panel, a set of industry experts will describe their experience with advanced technoloyg nodes (32nm/28nm) and how Testing is changing for these nodes. The discussion will range from specific examples of new failures modes … to changes in Test to detect these failure modes … to broader Test process changes. The panel will also address questions like the following: · What are 1–2 examples of new failure mechanisms that you found at 32nm/28nm ? · How did you change testing because of these new defect types/failure mechanisms ? · What new method of “statistical testing” (Adaptive Testing) have you recently started using ? · 3DIC testing — is it really different ? If so, why ? · Product personalization — is this becoming more prevalent ? If so, what are the new drivers & methods ? · Power/performance optimization — is this driving major changes to the Testing process ? If so, what changes ? · Reliability defect screening — are high voltage & high temperature accelerating still effective & required ? · How should the Test industry change to drive improvements to the End-to-End Test process ? · e.g., more rapid, more detailed, real-time cross-company data sharing?","PeriodicalId":6403,"journal":{"name":"2007 IEEE International Test Conference","volume":"2 2 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2012-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80898930","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-09-01DOI: 10.1109/TEST.2011.6139195
Xinli Gu
Today, more and more electronic manufacturing is being done in Asia. Test, as one of the important functions of manufacturing, is critical to guarantee the product quality and as a monitor of the manufacturing process. Through presenting the gap between the test challenges the Asia companies are facing and the tools they have today, we hope give the ITC community an opportunity to better understand the needs of innovation for test technologies and tools. This panel invites speakers from companies in Asia to present their test challenges and current solutions. It covers both design for test challenges and the complexities of the production test challenges. The focus is on the gap between what they need with today's challenges and the current capabilities.
{"title":"The gap: Test challenges in Asia manufacturing field","authors":"Xinli Gu","doi":"10.1109/TEST.2011.6139195","DOIUrl":"https://doi.org/10.1109/TEST.2011.6139195","url":null,"abstract":"Today, more and more electronic manufacturing is being done in Asia. Test, as one of the important functions of manufacturing, is critical to guarantee the product quality and as a monitor of the manufacturing process. Through presenting the gap between the test challenges the Asia companies are facing and the tools they have today, we hope give the ITC community an opportunity to better understand the needs of innovation for test technologies and tools. This panel invites speakers from companies in Asia to present their test challenges and current solutions. It covers both design for test challenges and the complexities of the production test challenges. The focus is on the gap between what they need with today's challenges and the current capabilities.","PeriodicalId":6403,"journal":{"name":"2007 IEEE International Test Conference","volume":"243 1","pages":"1"},"PeriodicalIF":0.0,"publicationDate":"2011-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84281581","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-09-01DOI: 10.1109/TEST.2011.6139193
Jing Zeng
Which is better for the debug of root causes for post-silicon issues with functionality, performance, or power: functional test on ATE, system-level test, or structural test? The panel will discuss pros and cons of the different approaches. Functional or system tests have traditionally been used for debugging functionality, performance and power related issues for high performance microprocessors or complex Systems-on-Chip. The functional approach can be expensive in infrastructure investment and in resources. Much of the infrastructure may not be usable from product to product. Results may not provide all the information for an effective post-silicon design optimization strategy. Structural tests such as scan or different forms of BIST can provide greater coverage, but does not know if a design is correct. Scan-based tests can be used for performance debug and is easier to automate. Scan takes advantage of existing architectures in a design and the automated test pattern generation process. Due to the limited number of at-speed capture cycles, scan tests can be easier to debug as more information of the chip behavior at the point of failure is available. However, scan can also test non-functional paths or easily generate over-kill or over stress conditions. How can scan be used if it can cause a false performance issue? Diagnosing power related issues can be a complex problem. Besides characterizing the power consumption during system testing, parametric tests and test-structure assisted test-based learning often could provide a quick read into potential power issues. The panel will analyze pro's and con's of various types and combinations of advance silicon debug to highlight the challenges and best practices available. Panelists represent years of experience in Silicon debug in Chip, Board, and System test and debug as well as EDA.
{"title":"Challenges and best practices in advanced silicon debug","authors":"Jing Zeng","doi":"10.1109/TEST.2011.6139193","DOIUrl":"https://doi.org/10.1109/TEST.2011.6139193","url":null,"abstract":"Which is better for the debug of root causes for post-silicon issues with functionality, performance, or power: functional test on ATE, system-level test, or structural test? The panel will discuss pros and cons of the different approaches. Functional or system tests have traditionally been used for debugging functionality, performance and power related issues for high performance microprocessors or complex Systems-on-Chip. The functional approach can be expensive in infrastructure investment and in resources. Much of the infrastructure may not be usable from product to product. Results may not provide all the information for an effective post-silicon design optimization strategy. Structural tests such as scan or different forms of BIST can provide greater coverage, but does not know if a design is correct. Scan-based tests can be used for performance debug and is easier to automate. Scan takes advantage of existing architectures in a design and the automated test pattern generation process. Due to the limited number of at-speed capture cycles, scan tests can be easier to debug as more information of the chip behavior at the point of failure is available. However, scan can also test non-functional paths or easily generate over-kill or over stress conditions. How can scan be used if it can cause a false performance issue? Diagnosing power related issues can be a complex problem. Besides characterizing the power consumption during system testing, parametric tests and test-structure assisted test-based learning often could provide a quick read into potential power issues. The panel will analyze pro's and con's of various types and combinations of advance silicon debug to highlight the challenges and best practices available. Panelists represent years of experience in Silicon debug in Chip, Board, and System test and debug as well as EDA.","PeriodicalId":6403,"journal":{"name":"2007 IEEE International Test Conference","volume":"26 1","pages":"1"},"PeriodicalIF":0.0,"publicationDate":"2011-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87972776","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-09-01DOI: 10.1109/TEST.2011.6139194
Bailarico Balangue
The objective of the panel is to have a good honest discussion from the board test industry experts about the future of ICT. The panel will consist of experts from various part of the industry and group them according to the following: 1. Board Test Managers/Experts from the Original Equipment Manufacturing (OEM), Contract Manufacturing (CM) and Original Design Manufacturing (ODM) side who strongly believe that the current ICT system is insufficient to test the new generation of PCBA. 2. ICT Marketing Manager/experts from ICT supplier (Agilent/Teradyne/TRI) that believes that the current ICT system has enough capabilities and features to maintain test coverage and cost needs for new generation of PCBA. 3. Board test Managers/Expert at OEM/CM/ODM who are dependent on ICT system as their main board test manufacturing strategy and has invested substantial ICT equipment and infrastructure in their manufacturing.
{"title":"In circuit test (ICT): The king is dead; long live the king!","authors":"Bailarico Balangue","doi":"10.1109/TEST.2011.6139194","DOIUrl":"https://doi.org/10.1109/TEST.2011.6139194","url":null,"abstract":"The objective of the panel is to have a good honest discussion from the board test industry experts about the future of ICT. The panel will consist of experts from various part of the industry and group them according to the following: 1. Board Test Managers/Experts from the Original Equipment Manufacturing (OEM), Contract Manufacturing (CM) and Original Design Manufacturing (ODM) side who strongly believe that the current ICT system is insufficient to test the new generation of PCBA. 2. ICT Marketing Manager/experts from ICT supplier (Agilent/Teradyne/TRI) that believes that the current ICT system has enough capabilities and features to maintain test coverage and cost needs for new generation of PCBA. 3. Board test Managers/Expert at OEM/CM/ODM who are dependent on ICT system as their main board test manufacturing strategy and has invested substantial ICT equipment and infrastructure in their manufacturing.","PeriodicalId":6403,"journal":{"name":"2007 IEEE International Test Conference","volume":"13 1","pages":"1"},"PeriodicalIF":0.0,"publicationDate":"2011-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76075740","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-09-01DOI: 10.1109/TEST.2011.6139192
P. Nigh
Summary Industry test experts will provide their views on how the test is going to change in the next 10 years. Topics will cover the future of Test Equipment, Design-for-Test, EDA software, Foundry Test Support and Test Methods. This panel will describe fundamental changes in the test field and the long-term impacts of these changes. Panelists will also describe how these trends are driving emerging business opportunities. The panelists will make provocative predictions in a way that is never seen in formal papers or presentations.
{"title":"Industry leaders panel - How will testing change in the next 10 years?","authors":"P. Nigh","doi":"10.1109/TEST.2011.6139192","DOIUrl":"https://doi.org/10.1109/TEST.2011.6139192","url":null,"abstract":"Summary Industry test experts will provide their views on how the test is going to change in the next 10 years. Topics will cover the future of Test Equipment, Design-for-Test, EDA software, Foundry Test Support and Test Methods. This panel will describe fundamental changes in the test field and the long-term impacts of these changes. Panelists will also describe how these trends are driving emerging business opportunities. The panelists will make provocative predictions in a way that is never seen in formal papers or presentations.","PeriodicalId":6403,"journal":{"name":"2007 IEEE International Test Conference","volume":"57 1","pages":"1"},"PeriodicalIF":0.0,"publicationDate":"2011-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84158673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-09-01DOI: 10.1109/TEST.2011.6139190
J. Shyu
Scientific discoveries open up new horizons, and technologies based on them can create or transform markets. However, the process of translating scientific discoveries into technologies involves a series of risk steps, resulting in low success rates. In industrial technology research institutes such as ITRI, the planning of such projects typically starts with conceptualizing innovative applications that meet certain needs of consumers or society. Once initiated, the process is forced to be in constant touch with both ends of its range: scientific discovery and market needs; the utmost consideration is the large impact it will have on industries, economy and the society at large. In this talk, examples of industrial technology research from a semiconductor application perspective, along with the collaboration model with the industry and academia, are presented. Crucial factors leading to successful deployment of new technologies such as cost, quality, and reliability are also addressed.
{"title":"A systems perspective on the R&D of industrial technology","authors":"J. Shyu","doi":"10.1109/TEST.2011.6139190","DOIUrl":"https://doi.org/10.1109/TEST.2011.6139190","url":null,"abstract":"Scientific discoveries open up new horizons, and technologies based on them can create or transform markets. However, the process of translating scientific discoveries into technologies involves a series of risk steps, resulting in low success rates. In industrial technology research institutes such as ITRI, the planning of such projects typically starts with conceptualizing innovative applications that meet certain needs of consumers or society. Once initiated, the process is forced to be in constant touch with both ends of its range: scientific discovery and market needs; the utmost consideration is the large impact it will have on industries, economy and the society at large. In this talk, examples of industrial technology research from a semiconductor application perspective, along with the collaboration model with the industry and academia, are presented. Crucial factors leading to successful deployment of new technologies such as cost, quality, and reliability are also addressed.","PeriodicalId":6403,"journal":{"name":"2007 IEEE International Test Conference","volume":"22 1","pages":"13"},"PeriodicalIF":0.0,"publicationDate":"2011-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74377923","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-08DOI: 10.1109/TEST.2008.4700698
B. G. V. Treuren
The SJTAG Initiative Group has been actively analyzing and mining common methods/procedures/interfaces through use case analysis over the domains identified as the SJTAG Universe. This poster summarizes the partitions/interfaces/data found.
{"title":"System JTAG Initiative Group Advancements","authors":"B. G. V. Treuren","doi":"10.1109/TEST.2008.4700698","DOIUrl":"https://doi.org/10.1109/TEST.2008.4700698","url":null,"abstract":"The SJTAG Initiative Group has been actively analyzing and mining common methods/procedures/interfaces through use case analysis over the domains identified as the SJTAG Universe. This poster summarizes the partitions/interfaces/data found.","PeriodicalId":6403,"journal":{"name":"2007 IEEE International Test Conference","volume":"39 1","pages":"1"},"PeriodicalIF":0.0,"publicationDate":"2008-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73543371","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-12-06DOI: 10.1109/TEST.2007.4437567
O. Ginez, P. Girard, C. Landrault, S. Pravossoudovitch, A. Virazel, J. Daga
The evolution of system-on-chip (SoC) designs involves the development of non-volatile memory technologies like Flash. As any kind of memories, embedded Flash (eFlash) can be subjected to complex functional faults that are related to their particular technological process and to their integration density. In this paper, we address a major issue during eFlash testing, namely the test of Address decoder Faults (AFs), which is generally very time consuming with ad-hoc solutions presently used in industry. In the first part of the paper, we show the impact of AFs on the functional behavior of an eFlash. Next, we use an analogy with RAM memory testing to classify AFs with respect to their functional behavior. We then obtain AFs acting either as stuck-at faults or as state coupling faults. In the fourth part of the paper, we propose a concurrent approach for testing AFs acting on either the word line decoder or the bit line decoder. The proposed approach allows using a minimal number of programming operations during test application. Finally, we propose a compaction procedure to further reduce the test time of AFs. As a result, huge reductions in test time can be achieved; experiments on a 4 Mbits eFlash have shown that a test time reduction factor of 34x can be obtained when compared to the global eFlash test flow presently used in industry. An additional important feature of the proposed strategy is that it allows testing 100% of other critical faults in eFlashs (stuck-at, transition and state coupling faults) beside full coverage of AFs.
{"title":"A concurrent approach for testing address decoder faults in eFlash memories","authors":"O. Ginez, P. Girard, C. Landrault, S. Pravossoudovitch, A. Virazel, J. Daga","doi":"10.1109/TEST.2007.4437567","DOIUrl":"https://doi.org/10.1109/TEST.2007.4437567","url":null,"abstract":"The evolution of system-on-chip (SoC) designs involves the development of non-volatile memory technologies like Flash. As any kind of memories, embedded Flash (eFlash) can be subjected to complex functional faults that are related to their particular technological process and to their integration density. In this paper, we address a major issue during eFlash testing, namely the test of Address decoder Faults (AFs), which is generally very time consuming with ad-hoc solutions presently used in industry. In the first part of the paper, we show the impact of AFs on the functional behavior of an eFlash. Next, we use an analogy with RAM memory testing to classify AFs with respect to their functional behavior. We then obtain AFs acting either as stuck-at faults or as state coupling faults. In the fourth part of the paper, we propose a concurrent approach for testing AFs acting on either the word line decoder or the bit line decoder. The proposed approach allows using a minimal number of programming operations during test application. Finally, we propose a compaction procedure to further reduce the test time of AFs. As a result, huge reductions in test time can be achieved; experiments on a 4 Mbits eFlash have shown that a test time reduction factor of 34x can be obtained when compared to the global eFlash test flow presently used in industry. An additional important feature of the proposed strategy is that it allows testing 100% of other critical faults in eFlashs (stuck-at, transition and state coupling faults) beside full coverage of AFs.","PeriodicalId":6403,"journal":{"name":"2007 IEEE International Test Conference","volume":"180 1","pages":"1-10"},"PeriodicalIF":0.0,"publicationDate":"2007-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80152899","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-25DOI: 10.1109/TEST.2007.4437632
X. Wen, K. Miyase, S. Kajihara, Tatsuya Suzuki, Yuta Yamato, P. Girard, Yuji Ohsumi, Laung-Terng Wang
High-quality at-speed scan testing, characterized by high small-delay-defect detecting capability, is indispensable to achieve high delay test quality for DSM circuits. However, such testing is susceptible to yield loss due to excessive power supply noise caused by high launch-induced switching activity. This paper addresses this serious problem with a novel and practical post-ATPG X-filling scheme, featuring (1) a test relaxation method, called path keeping X-identification, that finds don't-care bits from a fully-specified transition delay test set while preserving its delay test quality by keeping the longest paths originally sensitized for fault detection, and (2) an X-filling method, called justification-probability-based fill (JP-fill), that is both effective and scalable for reducing launch-induced switching activity. This scheme can be easily implemented into any ATPG flow to effectively reduce power supply noise, without any impact on delay test quality, test data volume, area overhead, and circuit timing.
{"title":"A novel scheme to reduce power supply noise for high-quality at-speed scan testing","authors":"X. Wen, K. Miyase, S. Kajihara, Tatsuya Suzuki, Yuta Yamato, P. Girard, Yuji Ohsumi, Laung-Terng Wang","doi":"10.1109/TEST.2007.4437632","DOIUrl":"https://doi.org/10.1109/TEST.2007.4437632","url":null,"abstract":"High-quality at-speed scan testing, characterized by high small-delay-defect detecting capability, is indispensable to achieve high delay test quality for DSM circuits. However, such testing is susceptible to yield loss due to excessive power supply noise caused by high launch-induced switching activity. This paper addresses this serious problem with a novel and practical post-ATPG X-filling scheme, featuring (1) a test relaxation method, called path keeping X-identification, that finds don't-care bits from a fully-specified transition delay test set while preserving its delay test quality by keeping the longest paths originally sensitized for fault detection, and (2) an X-filling method, called justification-probability-based fill (JP-fill), that is both effective and scalable for reducing launch-induced switching activity. This scheme can be easily implemented into any ATPG flow to effectively reduce power supply noise, without any impact on delay test quality, test data volume, area overhead, and circuit timing.","PeriodicalId":6403,"journal":{"name":"2007 IEEE International Test Conference","volume":"4 1","pages":"1-10"},"PeriodicalIF":0.0,"publicationDate":"2007-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80394030","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-23DOI: 10.1109/TEST.2007.4437653
L. Rolíndez, S. Mir, J. Carbonéro, D. Goguet, Nabil Chouba
In this paper we present a new architecture for audio analog-to-digital converters (ADCs) that includes a Built-in Self-Test (BIST) technique for the test of the signal-to-noise and distortion ratio (SNDR). A periodical binary stream is generated in the chip in order to stimulate the converter. The reuse of the bandgap circuit already existing in the converter allows us to generate the test stimulus with a very small analog area overhead. The output response analysis is performed by means of a sine-wave fitting algorithm. The reuse of the digital filter already existing in the converter allows us to generate a synchronized reference signal necessary for the fitting algorithm. The BIST technique is equivalent to a standard test carried out with a sinusoidal signal at -12 decibels Full-Scale (dBFS). The total test time is 60 ms and the estimated BIST overhead area is 7.5% of the whole stereo converter area in a 0.13 mum CMOS technology. Experimental results show that the correlation between the embedded self-test and a sinusoidal standard test is excellent, with a SNDR error smaller than 1 dB.
在本文中，我们提出了一种用于音频模数转换器(adc)的新架构，其中包括用于测试信噪比和失真比(SNDR)的内置自检(BIST)技术。在芯片中产生周期性的二进制流来激励转换器。转换器中已经存在的带隙电路的重用使我们能够以非常小的模拟面积开销产生测试刺激。输出响应分析采用正弦波拟合算法。转换器中已经存在的数字滤波器的重用使我们能够生成拟合算法所需的同步参考信号。BIST技术相当于用-12分贝(dBFS)的正弦信号进行的标准测试。在0.13 μ m CMOS技术中，总测试时间为60 ms，估计的BIST开销面积为整个立体声转换器面积的7.5%。实验结果表明，嵌入式自检与正弦标准测试具有良好的相关性，SNDR误差小于1 dB。
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