Pub Date : 1999-11-07DOI: 10.1109/ICCAD.1999.810609
V. Sundararajan, S. Sapatnekar, K. Parhi
This paper describes a polynomial time algorithm for min-area retiming for edge-triggered circuits to handle both setup and hold constraints. Given a circuit G and a target clock period c, our algorithm either outputs a retimed version of G satisfying setup and hold constraints or reports that such a solution is not possible, in O(|V/sup 3/|log|V|log(|V|C)) steps, where |V| corresponds to number of gates in the circuit and C is equal to the number of registers in the circuit. This is the first polynomial time algorithm ever reported for min-area retiming with constraints on both long and short-paths. An alternative problem formulation that takes practical issues in to consideration and lowers the problem complexity is also developed. Both the problem formulations have many parallels with the original formulation of long-path only retiming by Leiserson and Saxe and all the speed improvements that have been obtained on that technique are likely to be valid for improving the performance of the technique described in this paper.
{"title":"Marsh:min-area retiming with setup and hold constraints","authors":"V. Sundararajan, S. Sapatnekar, K. Parhi","doi":"10.1109/ICCAD.1999.810609","DOIUrl":"https://doi.org/10.1109/ICCAD.1999.810609","url":null,"abstract":"This paper describes a polynomial time algorithm for min-area retiming for edge-triggered circuits to handle both setup and hold constraints. Given a circuit G and a target clock period c, our algorithm either outputs a retimed version of G satisfying setup and hold constraints or reports that such a solution is not possible, in O(|V/sup 3/|log|V|log(|V|C)) steps, where |V| corresponds to number of gates in the circuit and C is equal to the number of registers in the circuit. This is the first polynomial time algorithm ever reported for min-area retiming with constraints on both long and short-paths. An alternative problem formulation that takes practical issues in to consideration and lowers the problem complexity is also developed. Both the problem formulations have many parallels with the original formulation of long-path only retiming by Leiserson and Saxe and all the speed improvements that have been obtained on that technique are likely to be valid for improving the performance of the technique described in this paper.","PeriodicalId":6414,"journal":{"name":"1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051)","volume":"14 1","pages":"2-6"},"PeriodicalIF":0.0,"publicationDate":"1999-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91274701","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-11-07DOI: 10.1109/ICCAD.1999.810690
M. Beattie, L. Pileggi
The increasing interconnect density and operating frequencies of system-on-a-chip (SOC) designs necessitates extraction of parasitic electromagnetic couplings beyond the localized confines of functional design blocks. In addition, SOC design styles and gridless variable-width routing make it increasingly difficult to use precharacterized library shapes for parasitic extraction. A comprehensive capacitance and inductance extraction solution requires a hierarchical data representation and fast runtime algorithms. We illustrate through examples that both the multipole method and hierarchical refinement, which are the two most successful approaches for parasitic extraction to date, work efficiently only under certain, limiting conditions. To improve this situation we present an approach which combines the best of both methods into a concurrent multipole refinement representation of the electromagnetic interaction which is efficient for arbitrary interconnect configurations. We use a generalized formulation of electromagnetic interactions to exploit the similarities in capacitance and inductance extraction for greater efficiency.
{"title":"Electromagnetic parasitic extraction via a multipole method with hierarchical refinement","authors":"M. Beattie, L. Pileggi","doi":"10.1109/ICCAD.1999.810690","DOIUrl":"https://doi.org/10.1109/ICCAD.1999.810690","url":null,"abstract":"The increasing interconnect density and operating frequencies of system-on-a-chip (SOC) designs necessitates extraction of parasitic electromagnetic couplings beyond the localized confines of functional design blocks. In addition, SOC design styles and gridless variable-width routing make it increasingly difficult to use precharacterized library shapes for parasitic extraction. A comprehensive capacitance and inductance extraction solution requires a hierarchical data representation and fast runtime algorithms. We illustrate through examples that both the multipole method and hierarchical refinement, which are the two most successful approaches for parasitic extraction to date, work efficiently only under certain, limiting conditions. To improve this situation we present an approach which combines the best of both methods into a concurrent multipole refinement representation of the electromagnetic interaction which is efficient for arbitrary interconnect configurations. We use a generalized formulation of electromagnetic interactions to exploit the similarities in capacitance and inductance extraction for greater efficiency.","PeriodicalId":6414,"journal":{"name":"1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051)","volume":"14 1","pages":"437-444"},"PeriodicalIF":0.0,"publicationDate":"1999-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73806061","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-11-07DOI: 10.1109/ICCAD.1999.810691
A. J. Dammers, N. V. D. Meijs
We extend the partial inductance concept by replacing the magnetic interaction between open filaments i and j by that between filament j and a (finite) closed loop, formed by connecting the endpoints of a filament pair (i-i/sup l/). The secondary filament i/sup l/ is constructed by radial projection of filament i onto a cylindrical shell around filament j. We show that, although individual partial inductance values are modified, the inductive behaviour of the full circuit is invariant. Mutual inductances of distant filaments are particularly reduced, because the far field of a conductor loop falls off much faster than that of a single filament. Therefore, it is expected that subsequent removal of such transformed off-diagonal elements from the partial inductance matrix has less effect on the overall inductive properties, so our method provides a tool to enhance robustness under matrix sparsification. We call our method "virtual screening", because the screening filaments (i/sup l/) are not physically present. Symmetry of the inductance matrix is presented for orthogonal networks only. We also present an extension of our method to a more general class of shells. This allows a detailed comparison of the virtual screening method and the "potential shift-truncate method", introduced with spherical equipotential shells (B. Krauter and L.T. Pileggi, 1995) and extended to ellipsoidal equipotential shells (M. Beattie et al., 1998). We find strong similarities, but also differences. An interesting result is the fact that the virtual screening method with tubular shells applied to orthogonal networks can be interpreted as a generalization of the potential shift-truncate method to non-equipotential shells, which also implies that preservation of stability is guaranteed.
{"title":"Virtual screening: a step towards a sparse partial inductance matrix","authors":"A. J. Dammers, N. V. D. Meijs","doi":"10.1109/ICCAD.1999.810691","DOIUrl":"https://doi.org/10.1109/ICCAD.1999.810691","url":null,"abstract":"We extend the partial inductance concept by replacing the magnetic interaction between open filaments i and j by that between filament j and a (finite) closed loop, formed by connecting the endpoints of a filament pair (i-i/sup l/). The secondary filament i/sup l/ is constructed by radial projection of filament i onto a cylindrical shell around filament j. We show that, although individual partial inductance values are modified, the inductive behaviour of the full circuit is invariant. Mutual inductances of distant filaments are particularly reduced, because the far field of a conductor loop falls off much faster than that of a single filament. Therefore, it is expected that subsequent removal of such transformed off-diagonal elements from the partial inductance matrix has less effect on the overall inductive properties, so our method provides a tool to enhance robustness under matrix sparsification. We call our method \"virtual screening\", because the screening filaments (i/sup l/) are not physically present. Symmetry of the inductance matrix is presented for orthogonal networks only. We also present an extension of our method to a more general class of shells. This allows a detailed comparison of the virtual screening method and the \"potential shift-truncate method\", introduced with spherical equipotential shells (B. Krauter and L.T. Pileggi, 1995) and extended to ellipsoidal equipotential shells (M. Beattie et al., 1998). We find strong similarities, but also differences. An interesting result is the fact that the virtual screening method with tubular shells applied to orthogonal networks can be interpreted as a generalization of the potential shift-truncate method to non-equipotential shells, which also implies that preservation of stability is guaranteed.","PeriodicalId":6414,"journal":{"name":"1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051)","volume":"22 1","pages":"445-452"},"PeriodicalIF":0.0,"publicationDate":"1999-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81051382","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-11-07DOI: 10.1109/ICCAD.1999.810632
Ki-Wook Kim, C. Liu, S. Kang
In this paper, we present a new approach to the problem of inverter elimination in domino logic synthesis. A small piece of static CMOS logic is introduced to the circuit to avoid significant area penalty resulting from duplication. To maximize the domino logic part and to minimize the static CMOS logic part, a generalized ATPG based logic transformation is proposed to eliminate or relocate a target inverter. Based on the new concept of dominating set of mandatory assignment (DSMA) and the corresponding implication graph, we propose algorithms to identify a minimum candidate set for a target inverter. Experimental results show that logic transformation based on an implication graph can reduce transistor counts by 25% and power delay product by 25% on average.
{"title":"Implication graph based domino logic synthesis","authors":"Ki-Wook Kim, C. Liu, S. Kang","doi":"10.1109/ICCAD.1999.810632","DOIUrl":"https://doi.org/10.1109/ICCAD.1999.810632","url":null,"abstract":"In this paper, we present a new approach to the problem of inverter elimination in domino logic synthesis. A small piece of static CMOS logic is introduced to the circuit to avoid significant area penalty resulting from duplication. To maximize the domino logic part and to minimize the static CMOS logic part, a generalized ATPG based logic transformation is proposed to eliminate or relocate a target inverter. Based on the new concept of dominating set of mandatory assignment (DSMA) and the corresponding implication graph, we propose algorithms to identify a minimum candidate set for a target inverter. Experimental results show that logic transformation based on an implication graph can reduce transistor counts by 25% and power delay product by 25% on average.","PeriodicalId":6414,"journal":{"name":"1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051)","volume":"2 1","pages":"111-114"},"PeriodicalIF":0.0,"publicationDate":"1999-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83234361","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-11-07DOI: 10.1109/ICCAD.1999.810661
Eui-Young Chung, L. Benini, G. Micheli
Dynamic power management (DPM) is a technique to reduce the power consumption of electronic systems by selectively shutting down idle components. The quality of the shutdown control algorithm (the power management policy) mostly depends on knowledge of the user's behavior, which in many cases is initially unknown or non-stationary. For this reason, DPM policies should be capable of adapting to changes in user behavior. In this paper, we present a novel DPM scheme based on idle period clustering and adaptive learning trees. We also provide a design guide for applying our technique to components with multiple sleep states. Experimental results show that our technique outperforms other advanced DPM schemes as well as simple time-out policies. The proposed approach shows little deviation of efficiency for various workloads having different characteristics, while other policies show that their efficiency changes drastically depending on the trace data characteristics. Furthermore, experimental evidence indicates that our workload learning algorithm is stable and has fast convergence.
{"title":"Dynamic power management using adaptive learning tree","authors":"Eui-Young Chung, L. Benini, G. Micheli","doi":"10.1109/ICCAD.1999.810661","DOIUrl":"https://doi.org/10.1109/ICCAD.1999.810661","url":null,"abstract":"Dynamic power management (DPM) is a technique to reduce the power consumption of electronic systems by selectively shutting down idle components. The quality of the shutdown control algorithm (the power management policy) mostly depends on knowledge of the user's behavior, which in many cases is initially unknown or non-stationary. For this reason, DPM policies should be capable of adapting to changes in user behavior. In this paper, we present a novel DPM scheme based on idle period clustering and adaptive learning trees. We also provide a design guide for applying our technique to components with multiple sleep states. Experimental results show that our technique outperforms other advanced DPM schemes as well as simple time-out policies. The proposed approach shows little deviation of efficiency for various workloads having different characteristics, while other policies show that their efficiency changes drastically depending on the trace data characteristics. Furthermore, experimental evidence indicates that our workload learning algorithm is stable and has fast convergence.","PeriodicalId":6414,"journal":{"name":"1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051)","volume":"40 1","pages":"274-279"},"PeriodicalIF":0.0,"publicationDate":"1999-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74118013","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-11-07DOI: 10.1109/ICCAD.1999.810636
A. Samavedam, K. Mayaram, T. Fiez
A scalable macromodel for substrate noise coupling in heavily doped substrates has been developed. This model is simple since it requires only four parameters which can readily be extracted from a small number of device simulations or measurements. Once these parameters have been determined the model can be used for any spacing between the injection and sensing contacts and for different contact geometries. The scalability of the model with separation and width provides insight into substrate coupling and optimization issues prior to and during the layout phase. The model is validated for a 2 /spl mu/m and a 0.5 /spl mu/m CMOS process where it is shown that the simple model predicts the noise coupling accurately. Measurements from a chip fabricated in a 0.5 /spl mu/m CMOS process show good agreement with the model.
建立了一个可扩展的高掺杂衬底噪声耦合宏观模型。该模型很简单，因为它只需要四个参数，这些参数可以很容易地从少量设备模拟或测量中提取出来。一旦确定了这些参数，该模型就可以用于注射和感应触点之间的任何间距以及不同的触点几何形状。该模型具有分离和宽度的可扩展性，可以在布局阶段之前和期间深入了解基板耦合和优化问题。在2 /spl mu/m和0.5 /spl mu/m的CMOS工艺中验证了该模型，结果表明该简单模型能够准确地预测噪声耦合。在0.5 /spl μ m CMOS工艺中制造的芯片的测量结果与模型吻合良好。
{"title":"A scalable substrate noise coupling model for mixed-signal ICs","authors":"A. Samavedam, K. Mayaram, T. Fiez","doi":"10.1109/ICCAD.1999.810636","DOIUrl":"https://doi.org/10.1109/ICCAD.1999.810636","url":null,"abstract":"A scalable macromodel for substrate noise coupling in heavily doped substrates has been developed. This model is simple since it requires only four parameters which can readily be extracted from a small number of device simulations or measurements. Once these parameters have been determined the model can be used for any spacing between the injection and sensing contacts and for different contact geometries. The scalability of the model with separation and width provides insight into substrate coupling and optimization issues prior to and during the layout phase. The model is validated for a 2 /spl mu/m and a 0.5 /spl mu/m CMOS process where it is shown that the simple model predicts the noise coupling accurately. Measurements from a chip fabricated in a 0.5 /spl mu/m CMOS process show good agreement with the model.","PeriodicalId":6414,"journal":{"name":"1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051)","volume":"10 1","pages":"128-131"},"PeriodicalIF":0.0,"publicationDate":"1999-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73145603","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-11-07DOI: 10.1109/ICCAD.1999.810671
D. Rhodes, W. Wolf
We describe the first co-design technique aimed at heterogeneous systems employing arbitrated communication. Arbitrated system design is especially difficult because communication scheduling is directly tied to task allocation. The method provides a complete co-design-i.e. generation of a hardware configuration along with an allocation and schedule for the execution of hard real-time data-dependent tasks. By using an actual scheduling analysis in the inner co-design loop, the method is readily able to address realistic system effects including various communication models like arbitration, as in PCI-based systems.
{"title":"Co-synthesis of heterogeneous multiprocessor systems using arbitrated communication","authors":"D. Rhodes, W. Wolf","doi":"10.1109/ICCAD.1999.810671","DOIUrl":"https://doi.org/10.1109/ICCAD.1999.810671","url":null,"abstract":"We describe the first co-design technique aimed at heterogeneous systems employing arbitrated communication. Arbitrated system design is especially difficult because communication scheduling is directly tied to task allocation. The method provides a complete co-design-i.e. generation of a hardware configuration along with an allocation and schedule for the execution of hard real-time data-dependent tasks. By using an actual scheduling analysis in the inner co-design loop, the method is readily able to address realistic system effects including various communication models like arbitration, as in PCI-based systems.","PeriodicalId":6414,"journal":{"name":"1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051)","volume":"1 1","pages":"339-342"},"PeriodicalIF":0.0,"publicationDate":"1999-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83812938","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper addresses the copyright protection problem of integrated circuits designed with blocks which are originated from multiple design sources. The process consists of two phases. First, a compact signature is generated from every block independently and made public. Utilizing such signatures, a design can be decomposed into its original building blocks, regardless of multiple hierarchies. Then, a map of all the blocks can be built, thus allowing to reconstruct the original copyright dependencies. The proposed methodology can be used by foundries to verify that designs submitted for fabrication contain blocks traceable to a legal source of intellectual property. The verification process is also useful to intellectual property providers and integrators, as it reduces the likelihood of infringement, thus ultimately minimizing the risk of litigation.
{"title":"Copyright protection of designs based on multi source IPs","authors":"E. Charbon, I. Torunoglu","doi":"10.5555/339492.340082","DOIUrl":"https://doi.org/10.5555/339492.340082","url":null,"abstract":"This paper addresses the copyright protection problem of integrated circuits designed with blocks which are originated from multiple design sources. The process consists of two phases. First, a compact signature is generated from every block independently and made public. Utilizing such signatures, a design can be decomposed into its original building blocks, regardless of multiple hierarchies. Then, a map of all the blocks can be built, thus allowing to reconstruct the original copyright dependencies. The proposed methodology can be used by foundries to verify that designs submitted for fabrication contain blocks traceable to a legal source of intellectual property. The verification process is also useful to intellectual property providers and integrators, as it reduces the likelihood of infringement, thus ultimately minimizing the risk of litigation.","PeriodicalId":6414,"journal":{"name":"1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051)","volume":"52 1","pages":"591-595"},"PeriodicalIF":0.0,"publicationDate":"1999-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83797916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-11-07DOI: 10.1109/ICCAD.1999.810638
P. Tafertshofer, A. Ganz
In this paper we present new methods for fast justification and propagation in the implication graph (IG) which is the core data structure of our SAT based implication engine. As the IG model represents all information on the implemented logic function as well as the topology of a circuit, the proposed techniques inherit all advantages of both general SAT based and structure based approaches to justification, propagation, and implication. These three fundamental Boolean problems are the main tasks to be performed during automatic test pattern generation (ATPG) such that the proposed algorithms are incorporated into our ATPG tool TIP which is built on top of the implication engine. Working exclusively in the IG, the complex functional operations of justification, propagation, and implication reduce to significantly simpler graph algorithms. They are easily extended to exploit bit-parallel techniques. As the IG is automatically generated for arbitrary logics the algorithms remain applicable independent of the required logic. This allows processing of various fault models using the same engine. That is, the presented IG based methods offer a complete and versatile framework for rapid development of new ATPG tools that target emerging fault models such as crosstalk, delay or bridging faults. TIP currently handles stuck-at as well as various delay fault models. Furthermore, the proposed methods are used within tools for Boolean equivalence checking, optimization of netlists, timing analysis or retiming (reset state computation).
{"title":"SAT based ATPG using fast justification and propagation in the implication graph","authors":"P. Tafertshofer, A. Ganz","doi":"10.1109/ICCAD.1999.810638","DOIUrl":"https://doi.org/10.1109/ICCAD.1999.810638","url":null,"abstract":"In this paper we present new methods for fast justification and propagation in the implication graph (IG) which is the core data structure of our SAT based implication engine. As the IG model represents all information on the implemented logic function as well as the topology of a circuit, the proposed techniques inherit all advantages of both general SAT based and structure based approaches to justification, propagation, and implication. These three fundamental Boolean problems are the main tasks to be performed during automatic test pattern generation (ATPG) such that the proposed algorithms are incorporated into our ATPG tool TIP which is built on top of the implication engine. Working exclusively in the IG, the complex functional operations of justification, propagation, and implication reduce to significantly simpler graph algorithms. They are easily extended to exploit bit-parallel techniques. As the IG is automatically generated for arbitrary logics the algorithms remain applicable independent of the required logic. This allows processing of various fault models using the same engine. That is, the presented IG based methods offer a complete and versatile framework for rapid development of new ATPG tools that target emerging fault models such as crosstalk, delay or bridging faults. TIP currently handles stuck-at as well as various delay fault models. Furthermore, the proposed methods are used within tools for Boolean equivalence checking, optimization of netlists, timing analysis or retiming (reset state computation).","PeriodicalId":6414,"journal":{"name":"1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051)","volume":"23 1","pages":"139-146"},"PeriodicalIF":0.0,"publicationDate":"1999-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80778902","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-11-07DOI: 10.1109/ICCAD.1999.810718
A. Kahng, D. Kirovski, S. Mantik, M. Potkonjak, J. Wong
We give the first study of copy detection techniques for VLSI CAD applications; these techniques are complementary to previous watermarking-based IP protection methods in finding and proving improper use of design IP. After reviewing related literature (notably in the text processing domain), we propose a generic methodology for copy detection based on determining basic elements within structural representations of solutions (IPs), calculating (context-independent) signatures for such elements, and performing fast comparisons to identify potential violators of IP rights. We give example implementations of this methodology in the domains of scheduling, graph coloring and gate-level layout; experimental results show the effectiveness of our copy detection schemes as well as the low overhead of implementation. We remark on open research areas, notably the potentially deep and complementary interaction between watermarking and copy detection.
{"title":"Copy detection for intellectual property protection of VLSI designs","authors":"A. Kahng, D. Kirovski, S. Mantik, M. Potkonjak, J. Wong","doi":"10.1109/ICCAD.1999.810718","DOIUrl":"https://doi.org/10.1109/ICCAD.1999.810718","url":null,"abstract":"We give the first study of copy detection techniques for VLSI CAD applications; these techniques are complementary to previous watermarking-based IP protection methods in finding and proving improper use of design IP. After reviewing related literature (notably in the text processing domain), we propose a generic methodology for copy detection based on determining basic elements within structural representations of solutions (IPs), calculating (context-independent) signatures for such elements, and performing fast comparisons to identify potential violators of IP rights. We give example implementations of this methodology in the domains of scheduling, graph coloring and gate-level layout; experimental results show the effectiveness of our copy detection schemes as well as the low overhead of implementation. We remark on open research areas, notably the potentially deep and complementary interaction between watermarking and copy detection.","PeriodicalId":6414,"journal":{"name":"1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051)","volume":"28 1","pages":"600-604"},"PeriodicalIF":0.0,"publicationDate":"1999-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88300778","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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