Pub Date : 2010-06-13DOI: 10.1109/SNW.2010.5562563
T. Hayashida, K. Endo, Y. Liu, T. Kamei, T. Matsukawa, S. Ouchi, K. Sakamoto, J. Tsukada, Y. Ishikawa, H. Yamauchi, A. Ogura, M. Masahara
We have demonstrated the effect of the resistivity reduction of the ALD-TiN film using TDMAT precursor by modifying the NH3 process (both initial exposure and PDA processes). It was found that the resistivity of the ALD TiN was significantly reduced by extending tNH3 and increasing TPDA by 700°C. Moreover, by employing the NH3 PDA, an increase in TiN peak intensity was detected from Ti 2p by XPS analysis and Ti : N ratio of approximately 1∶1 was achieved. As a result of the evaluation of the electrical characteristics of TiN-gate MOSFETs, superior performance was achieved in the case of ALD TiN.
{"title":"Low resistive ALD TiN metal gate using TDMAT precursor for high performance MOSFET","authors":"T. Hayashida, K. Endo, Y. Liu, T. Kamei, T. Matsukawa, S. Ouchi, K. Sakamoto, J. Tsukada, Y. Ishikawa, H. Yamauchi, A. Ogura, M. Masahara","doi":"10.1109/SNW.2010.5562563","DOIUrl":"https://doi.org/10.1109/SNW.2010.5562563","url":null,"abstract":"We have demonstrated the effect of the resistivity reduction of the ALD-TiN film using TDMAT precursor by modifying the NH3 process (both initial exposure and PDA processes). It was found that the resistivity of the ALD TiN was significantly reduced by extending tNH3 and increasing TPDA by 700°C. Moreover, by employing the NH3 PDA, an increase in TiN peak intensity was detected from Ti 2p by XPS analysis and Ti : N ratio of approximately 1∶1 was achieved. As a result of the evaluation of the electrical characteristics of TiN-gate MOSFETs, superior performance was achieved in the case of ALD TiN.","PeriodicalId":6433,"journal":{"name":"2010 Silicon Nanoelectronics Workshop","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84529602","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-13DOI: 10.1109/SNW.2010.5562561
H. Shin, Se-Kyung Oh, Min-Ho Kang, I. Han, H. Kwon, Sang-Uk Park, Byung-Seok Park, J. Bok, Ga-Won Lee, H. Lee
In this study, thermal stability of Ni silicide on boron, BF2, and B18H22 implanted junctions is improved using Ni-Pd(5%) alloy target. The proposed Ni-Pd(5%)/TiN structure enabled the maintenance of low sheet resistance during the RTP and post silicidation annealing than conventional Ni/TiN structure. The improvement of Ni silicide properties is analyzed to be due to the formation of Pd2Si of which peaks were confirmed by XRD data, which indicates the reaction has substantially occurred during the RTP and post silicidation annealing. Moreover, it is also shown that the proposed Ni-Pd(5%)/TiN is efficient in reducing the reverse leakage current as well as improving the thermal stability of ultra shallow junction with B18H22 implantation.
{"title":"Improvement of junction characteristics of ultra shallow junction with boron-cluster implantation and Ni-silicide for nano-scale CMOS technology","authors":"H. Shin, Se-Kyung Oh, Min-Ho Kang, I. Han, H. Kwon, Sang-Uk Park, Byung-Seok Park, J. Bok, Ga-Won Lee, H. Lee","doi":"10.1109/SNW.2010.5562561","DOIUrl":"https://doi.org/10.1109/SNW.2010.5562561","url":null,"abstract":"In this study, thermal stability of Ni silicide on boron, BF2, and B18H22 implanted junctions is improved using Ni-Pd(5%) alloy target. The proposed Ni-Pd(5%)/TiN structure enabled the maintenance of low sheet resistance during the RTP and post silicidation annealing than conventional Ni/TiN structure. The improvement of Ni silicide properties is analyzed to be due to the formation of Pd2Si of which peaks were confirmed by XRD data, which indicates the reaction has substantially occurred during the RTP and post silicidation annealing. Moreover, it is also shown that the proposed Ni-Pd(5%)/TiN is efficient in reducing the reverse leakage current as well as improving the thermal stability of ultra shallow junction with B18H22 implantation.","PeriodicalId":6433,"journal":{"name":"2010 Silicon Nanoelectronics Workshop","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81150891","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-13DOI: 10.1109/SNW.2010.5562558
Min-Ho Kang, Se-Kyung Oh, H. Shin, J. Yoo, Ga-Won Lee, Jin-Suk Wang, Jungwoo Oh, P. Majhi, R. Jammy, H. Lee
Co-sputtering of Ni and Pt was proposed for thermal stable Ge MOSFETs on a Ge-on-Si substrate. The thermal stability of Ni germanide was considerably improved compared to the pure Ni germanide by the co-sputtering of Pt along with Ni, because Pt atoms distributed uniformly in the Ni germanide layer, which suppressed the agglomeration of Ni germanide. Therefore, the proposed Ni-Pt co-sputtering method is promising for high performance Ge MOSFET applications.
{"title":"Novel Ni germanide technology with co-sputtering of Ni and Pt for thermally stable Ge MOSFETs on Ge-on-Si substrate","authors":"Min-Ho Kang, Se-Kyung Oh, H. Shin, J. Yoo, Ga-Won Lee, Jin-Suk Wang, Jungwoo Oh, P. Majhi, R. Jammy, H. Lee","doi":"10.1109/SNW.2010.5562558","DOIUrl":"https://doi.org/10.1109/SNW.2010.5562558","url":null,"abstract":"Co-sputtering of Ni and Pt was proposed for thermal stable Ge MOSFETs on a Ge-on-Si substrate. The thermal stability of Ni germanide was considerably improved compared to the pure Ni germanide by the co-sputtering of Pt along with Ni, because Pt atoms distributed uniformly in the Ni germanide layer, which suppressed the agglomeration of Ni germanide. Therefore, the proposed Ni-Pt co-sputtering method is promising for high performance Ge MOSFET applications.","PeriodicalId":6433,"journal":{"name":"2010 Silicon Nanoelectronics Workshop","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76519347","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-13DOI: 10.1109/SNW.2010.5562571
Yongjin Park, K. Kong, Hyunju Chang, M. Shin
The first principle calculations based on density functional theory were performed to determine the band gap profiles and dielectric constants along the Si-Dielectric interface of CMOS device. The band gap changes almost linearly between Si and SiO2 interfaces with transition depth of 5 Å. The calculated dielectric constants change almost abruptly at Si/SiO2 interface. Thus-obtained band gap profile and dielectric constants were used in electron transport simulation of ultra-thin-body n-type double-gate MOSFETs. The self-consistent potential profile in the channel and gate leakage current were calculated accurately using the non-equilibrium Green's function approach. The effect of the band gap transition across the Si/SiO2 interface on the device performance is investigated.
{"title":"Device characteristics of double-gate MOSFETs with Si-dielectric interface model from first principle calculations","authors":"Yongjin Park, K. Kong, Hyunju Chang, M. Shin","doi":"10.1109/SNW.2010.5562571","DOIUrl":"https://doi.org/10.1109/SNW.2010.5562571","url":null,"abstract":"The first principle calculations based on density functional theory were performed to determine the band gap profiles and dielectric constants along the Si-Dielectric interface of CMOS device. The band gap changes almost linearly between Si and SiO2 interfaces with transition depth of 5 Å. The calculated dielectric constants change almost abruptly at Si/SiO2 interface. Thus-obtained band gap profile and dielectric constants were used in electron transport simulation of ultra-thin-body n-type double-gate MOSFETs. The self-consistent potential profile in the channel and gate leakage current were calculated accurately using the non-equilibrium Green's function approach. The effect of the band gap transition across the Si/SiO2 interface on the device performance is investigated.","PeriodicalId":6433,"journal":{"name":"2010 Silicon Nanoelectronics Workshop","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82640826","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-13DOI: 10.1109/SNW.2010.5562593
K. Ikeda, Y. Kamimuta, N. Taoka, Y. Moriyama, M. Oda, T. Tezuka
SBH and Tsilicide reduction is found to be beneficial for improving the current drive of a metal S/D FinFET especially for a SBH higher than around 0.2 eV by the simulation. The precise control of NiSi thickness with keeping smooth interface was demonstrated by the nitrogen pre-implanted silicidation technique adopted for the strained-Si channel tri-gated MOSFETs having dopant-segregated NiSi contacts. The MOSFETs exhibited lower leakage current and on-resistance than those fabricated without using this technique due to the suppression of the encroachment defects and over silicidation. The present results suggest that this technique can be a solution of silicide formation for multi-gate MOSFET.
{"title":"Precise thickness control of NiSi by nitrogen ion-implantation for multi-gate strained Si channel metal S/D MOSFETs","authors":"K. Ikeda, Y. Kamimuta, N. Taoka, Y. Moriyama, M. Oda, T. Tezuka","doi":"10.1109/SNW.2010.5562593","DOIUrl":"https://doi.org/10.1109/SNW.2010.5562593","url":null,"abstract":"SBH and Tsilicide reduction is found to be beneficial for improving the current drive of a metal S/D FinFET especially for a SBH higher than around 0.2 eV by the simulation. The precise control of NiSi thickness with keeping smooth interface was demonstrated by the nitrogen pre-implanted silicidation technique adopted for the strained-Si channel tri-gated MOSFETs having dopant-segregated NiSi contacts. The MOSFETs exhibited lower leakage current and on-resistance than those fabricated without using this technique due to the suppression of the encroachment defects and over silicidation. The present results suggest that this technique can be a solution of silicide formation for multi-gate MOSFET.","PeriodicalId":6433,"journal":{"name":"2010 Silicon Nanoelectronics Workshop","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84900975","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We study the characteristic variability in high-к metal-gate CMOS device and circuit induced by various intrinsic fluctuation sources. Using an experimentally calibrated 3D device-and-circuit coupled simulation; we estimate the effect of metal-gate work-function fluctuation, oxide-thickness fluctuation, process-variation effect, and random-dopant fluctuation on device DC/AC characteristics. We then predict their impacts on transfer and dynamic properties of digital and analog circuits. Finally, variability suppression techniques are demonstrated from device engineering viewpoints.
{"title":"Electrical characteristic fluctuation and suppression in emerging CMOS device and circuit","authors":"Hui-Wen Cheng, Ming-Hung Han, Yiming Li, Kuo-Fu Lee, C. Yiu, Thet-Thet Khaing","doi":"10.1109/SNW.2010.5562560","DOIUrl":"https://doi.org/10.1109/SNW.2010.5562560","url":null,"abstract":"We study the characteristic variability in high-к metal-gate CMOS device and circuit induced by various intrinsic fluctuation sources. Using an experimentally calibrated 3D device-and-circuit coupled simulation; we estimate the effect of metal-gate work-function fluctuation, oxide-thickness fluctuation, process-variation effect, and random-dopant fluctuation on device DC/AC characteristics. We then predict their impacts on transfer and dynamic properties of digital and analog circuits. Finally, variability suppression techniques are demonstrated from device engineering viewpoints.","PeriodicalId":6433,"journal":{"name":"2010 Silicon Nanoelectronics Workshop","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79410818","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-13DOI: 10.1109/SNW.2010.5562557
T. Mizutani, Ashok Kumar, T. Tsunomura, A. Nishida, K. Takeuchi, S. Inaba, S. Kamohara, K. Terada, T. Hiramoto
We report statistic characteristics of a newly found variability component: “current-onset voltage” [1]. It is found that the “current-onset voltage” is hardly correlated with any other parameters such as threshold voltage VTH, transconductance Gm and DIBL. These results indicate that the “current-onset voltage” variability is quite a new type of variation that has never been considered before.
{"title":"Statistic characteristics of “current-onset voltage” in scaled MOSFETs analyzed by 8k DMA TEG","authors":"T. Mizutani, Ashok Kumar, T. Tsunomura, A. Nishida, K. Takeuchi, S. Inaba, S. Kamohara, K. Terada, T. Hiramoto","doi":"10.1109/SNW.2010.5562557","DOIUrl":"https://doi.org/10.1109/SNW.2010.5562557","url":null,"abstract":"We report statistic characteristics of a newly found variability component: “current-onset voltage” [1]. It is found that the “current-onset voltage” is hardly correlated with any other parameters such as threshold voltage V<inf>TH</inf>, transconductance G<inf>m</inf> and DIBL. These results indicate that the “current-onset voltage” variability is quite a new type of variation that has never been considered before.","PeriodicalId":6433,"journal":{"name":"2010 Silicon Nanoelectronics Workshop","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90107282","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-13DOI: 10.1109/SNW.2010.5562582
E. Hamid, Juli Cha Tarido, Sakito Miki, T. Mizuno, D. Moraru, M. Tabe
We investigated single electron charging in few-dopant systems by experiment and simulation. Our simulation results are in good agreement with experimental results. This provides a strong support for understanding the physics of single electron charging in few-dopant systems for future single dopant memory device design rules.
{"title":"Single-dopant memory effect in P-doped Si SOI-MOSFETs","authors":"E. Hamid, Juli Cha Tarido, Sakito Miki, T. Mizuno, D. Moraru, M. Tabe","doi":"10.1109/SNW.2010.5562582","DOIUrl":"https://doi.org/10.1109/SNW.2010.5562582","url":null,"abstract":"We investigated single electron charging in few-dopant systems by experiment and simulation. Our simulation results are in good agreement with experimental results. This provides a strong support for understanding the physics of single electron charging in few-dopant systems for future single dopant memory device design rules.","PeriodicalId":6433,"journal":{"name":"2010 Silicon Nanoelectronics Workshop","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78874015","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-13DOI: 10.1109/SNW.2010.5562570
Hui-Wen Cheng, C. Yiu, Thet-Thet Khaing, Yiming Li
In this study, we examine the dependency of current mirror circuit characteristics on channel-fin aspect-ratio (AR = fin height / the fin width) of 16-nm multi-gate MOSFET and device's intrinsic parameter fluctuation including metal-gate work-function fluctuation (WKF), random-dopant fluctuation (RDF), process-variation effect (PVE), and oxide-thickness fluctuation (OTF). For n- and p-type current mirror circuits, the fluctuations dominated by RDF and WKF, respectively, could be suppressed by high AR of devices due to improved driving current. For n- and p-type current mirror circuits, IOUT fluctuation dominated by RDF and WKF in FinFET (AR = 2) is 2.8 and 2.5 times smaller than that of quasi-planar (AR = 0.5) device, respectively.
在这项研究中，我们研究了电流反射电路特性与16纳米多栅极MOSFET的通道-鳍长比(AR =鳍高/鳍宽)的关系，以及器件的固有参数波动，包括金属栅功函数波动(WKF)、随机掺杂波动(RDF)、工艺变化效应(PVE)和氧化物厚度波动(OTF)。对于n型和p型电流镜像电路，由于驱动电流的提高，器件的高AR可以抑制由RDF和WKF分别主导的波动。对于n型和p型电流镜像电路，FinFET (AR = 2)中以RDF和WKF为主的IOUT波动分别比准平面(AR = 0.5)器件小2.8倍和2.5倍。
{"title":"Intrinsic parameter fluctuations on current mirror circuit with different aspect ratio of 16-nm multi-gate MOSFET","authors":"Hui-Wen Cheng, C. Yiu, Thet-Thet Khaing, Yiming Li","doi":"10.1109/SNW.2010.5562570","DOIUrl":"https://doi.org/10.1109/SNW.2010.5562570","url":null,"abstract":"In this study, we examine the dependency of current mirror circuit characteristics on channel-fin aspect-ratio (AR = fin height / the fin width) of 16-nm multi-gate MOSFET and device's intrinsic parameter fluctuation including metal-gate work-function fluctuation (WKF), random-dopant fluctuation (RDF), process-variation effect (PVE), and oxide-thickness fluctuation (OTF). For n- and p-type current mirror circuits, the fluctuations dominated by RDF and WKF, respectively, could be suppressed by high AR of devices due to improved driving current. For n- and p-type current mirror circuits, IOUT fluctuation dominated by RDF and WKF in FinFET (AR = 2) is 2.8 and 2.5 times smaller than that of quasi-planar (AR = 0.5) device, respectively.","PeriodicalId":6433,"journal":{"name":"2010 Silicon Nanoelectronics Workshop","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77270097","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-13DOI: 10.1109/SNW.2010.5562552
B. Tsui, Chih-Chan Yen, Po-Hsueh Li, Chi-Pei Lu, Jui-Yao Lai
The impact of extreme ultra-violate (EUV) exposure induced damages on the characteristics of Si-Oxide-Nitride-Oxide-Si (SONOS) memory and nano-crystal (NC) memory are investigated. In SONOS memory, the erase speed slows down and the endurance degrades severely due to the EUV induced deep-level traps in the dielectric stack and can not recover after 600°C annealing. The NC memory exhibits much better EUV radiation tolerance than the SONOS memory. This work suggests that the EUV lithography could be a potential solution for advanced NC memories without reliability issue.
研究了极紫外(EUV)辐照对si - oxide -氮化物- oxide - si (SONOS)存储器和纳米晶体(NC)存储器特性的影响。在SONOS存储器中，由于EUV引起的介电层中的深能级陷阱，擦除速度减慢，续航力严重下降，并且在600℃退火后无法恢复。NC存储器比SONOS存储器具有更好的EUV辐射耐受性。这项工作表明，极紫外光刻技术可能是一种没有可靠性问题的先进NC存储器的潜在解决方案。
{"title":"Extreme ultra-violate exposure induced damages on non-volatile memories","authors":"B. Tsui, Chih-Chan Yen, Po-Hsueh Li, Chi-Pei Lu, Jui-Yao Lai","doi":"10.1109/SNW.2010.5562552","DOIUrl":"https://doi.org/10.1109/SNW.2010.5562552","url":null,"abstract":"The impact of extreme ultra-violate (EUV) exposure induced damages on the characteristics of Si-Oxide-Nitride-Oxide-Si (SONOS) memory and nano-crystal (NC) memory are investigated. In SONOS memory, the erase speed slows down and the endurance degrades severely due to the EUV induced deep-level traps in the dielectric stack and can not recover after 600°C annealing. The NC memory exhibits much better EUV radiation tolerance than the SONOS memory. This work suggests that the EUV lithography could be a potential solution for advanced NC memories without reliability issue.","PeriodicalId":6433,"journal":{"name":"2010 Silicon Nanoelectronics Workshop","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87010871","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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