Pub Date : 2010-06-13DOI: 10.1109/SNW.2010.5562583
A. Paul, Gerhard Klimeck
Dimensional scaling provides an alternative route to improve the thermoelectric figure of merit (ZT) by the reduction of the lattice thermal conductivity(кl). However, this method is reaching the scaling limit. Further improvement in ZT can be achieved by improving the thermoelectric power-factor (S2G), the numerator of ZT. In this work we study this part of ZT using a combination of semi-empirical Tight-Binding method and Landauer approach. We study the effect of cross-sectional confinement, wire orientation and uniaxial strain on the power-factor (PF). It is found that any improvement in PF is only achieved for wires with cross-section size less than 6nm × 6nm.
{"title":"Atomistic modeling of the thermoelectric power factor in ultra-scaled Silicon nanowires","authors":"A. Paul, Gerhard Klimeck","doi":"10.1109/SNW.2010.5562583","DOIUrl":"https://doi.org/10.1109/SNW.2010.5562583","url":null,"abstract":"Dimensional scaling provides an alternative route to improve the thermoelectric figure of merit (ZT) by the reduction of the lattice thermal conductivity(кl). However, this method is reaching the scaling limit. Further improvement in ZT can be achieved by improving the thermoelectric power-factor (S2G), the numerator of ZT. In this work we study this part of ZT using a combination of semi-empirical Tight-Binding method and Landauer approach. We study the effect of cross-sectional confinement, wire orientation and uniaxial strain on the power-factor (PF). It is found that any improvement in PF is only achieved for wires with cross-section size less than 6nm × 6nm.","PeriodicalId":6433,"journal":{"name":"2010 Silicon Nanoelectronics Workshop","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84807381","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-13DOI: 10.1109/SNW.2010.5562592
S. Datta, A. Ali, S. Mookerjea, V. Saripalli, L. Liu, S. Eachempati, T. Mayer, V. Narayanan
Continued miniaturization of transistors has resulted in unprecedented increase in device count leading to high compute capability albeit with increase in energy consumption. Here, we present our research on advanced non silicon electronic material systems and novel device architectures — quantum-well FETs, inter-band tunnel FETs and tunnel-coupled nanodot devices - for heterogeneous integration on Si substrate. The goal is to demonstrate a compelling information processing platform that allows very aggressive scaling of supply voltage, thereby reducing energy consumption in future computing systems.
{"title":"Non-silicon logic elements on silicon for extreme voltage scaling","authors":"S. Datta, A. Ali, S. Mookerjea, V. Saripalli, L. Liu, S. Eachempati, T. Mayer, V. Narayanan","doi":"10.1109/SNW.2010.5562592","DOIUrl":"https://doi.org/10.1109/SNW.2010.5562592","url":null,"abstract":"Continued miniaturization of transistors has resulted in unprecedented increase in device count leading to high compute capability albeit with increase in energy consumption. Here, we present our research on advanced non silicon electronic material systems and novel device architectures — quantum-well FETs, inter-band tunnel FETs and tunnel-coupled nanodot devices - for heterogeneous integration on Si substrate. The goal is to demonstrate a compelling information processing platform that allows very aggressive scaling of supply voltage, thereby reducing energy consumption in future computing systems.","PeriodicalId":6433,"journal":{"name":"2010 Silicon Nanoelectronics Workshop","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88141483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-13DOI: 10.1109/SNW.2010.5562578
B. Chen, B. Gao, S. W. Sheng, L.F. Liu, X.Y. Liu, Y.S. Chen, Y. Wang, J. Kang, B. Yu
Based on the new finding on switching behavior, for the first time a new memory operation principle is proposed to control the switching and to achieve improved performance of oxide-based RRAM including device-to-device and cycle-to-cycle uniformity, RESET current, and window of RHRS/RLRS ratio. Furthermore, a numerical simulation method is developed to evaluate the validity of the new operation principle in scaled RRAM devices.
{"title":"Operation-oriented solution to boost key performance of RRAM","authors":"B. Chen, B. Gao, S. W. Sheng, L.F. Liu, X.Y. Liu, Y.S. Chen, Y. Wang, J. Kang, B. Yu","doi":"10.1109/SNW.2010.5562578","DOIUrl":"https://doi.org/10.1109/SNW.2010.5562578","url":null,"abstract":"Based on the new finding on switching behavior, for the first time a new memory operation principle is proposed to control the switching and to achieve improved performance of oxide-based RRAM including device-to-device and cycle-to-cycle uniformity, RESET current, and window of RHRS/RLRS ratio. Furthermore, a numerical simulation method is developed to evaluate the validity of the new operation principle in scaled RRAM devices.","PeriodicalId":6433,"journal":{"name":"2010 Silicon Nanoelectronics Workshop","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82398326","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-13DOI: 10.1109/SNW.2010.5562597
G. Hellings, G. Eneman, G. Brammertz, K. Martens, J. Mitard, Wei-E. Wang, T. Hoffmann, M. Meuris, K. De Meyer
A technique is presented and verified to predict the electrostatic degradation of MOSFET performance, due to interface traps and their energy distribution. It provides an estimate of the technology's sub-threshold slope degradation based on an extracted interface traps spectrum, without the need for transistor fabrication.
{"title":"Influence of interface traps on high-mobility channel performance","authors":"G. Hellings, G. Eneman, G. Brammertz, K. Martens, J. Mitard, Wei-E. Wang, T. Hoffmann, M. Meuris, K. De Meyer","doi":"10.1109/SNW.2010.5562597","DOIUrl":"https://doi.org/10.1109/SNW.2010.5562597","url":null,"abstract":"A technique is presented and verified to predict the electrostatic degradation of MOSFET performance, due to interface traps and their energy distribution. It provides an estimate of the technology's sub-threshold slope degradation based on an extracted interface traps spectrum, without the need for transistor fabrication.","PeriodicalId":6433,"journal":{"name":"2010 Silicon Nanoelectronics Workshop","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72971211","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-13DOI: 10.1109/SNW.2010.5562551
Ju-Wan Lee, M. Jeong, H. Kwon, Byung-Gook Park, Hyungcheol Shin, Jong-Ho Lee
We have proposed new 3-D stacked NAND flash memory structure and investigated key characteristics in various S/D doping concentration, body doping types, body doping concentrations, and stored charge. Thanks to crystalline Si channel, we obtained higher current than that in poly-Si channel. We have shown the interference between adjacent BLs can be removed by using common S-B contact.
{"title":"3-D stacked active layers and vertical gate NAND flash string with single-crystal Si channel by adopting Si/SiGe selective etch process","authors":"Ju-Wan Lee, M. Jeong, H. Kwon, Byung-Gook Park, Hyungcheol Shin, Jong-Ho Lee","doi":"10.1109/SNW.2010.5562551","DOIUrl":"https://doi.org/10.1109/SNW.2010.5562551","url":null,"abstract":"We have proposed new 3-D stacked NAND flash memory structure and investigated key characteristics in various S/D doping concentration, body doping types, body doping concentrations, and stored charge. Thanks to crystalline Si channel, we obtained higher current than that in poly-Si channel. We have shown the interference between adjacent BLs can be removed by using common S-B contact.","PeriodicalId":6433,"journal":{"name":"2010 Silicon Nanoelectronics Workshop","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87090615","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-13DOI: 10.1109/SNW.2010.5562566
A. Hossain, D. Vasileska, S. Goodnick, K. Raleva
Modern technology has enabled the fabrication of materials with characteristic dimensions of a few nanometers. Examples are superlattices, nanowires and quantum dots. Thermal transport in these low-dimensional nanostructures is important for next-generation microelectronic cooling techniques, novel solid-state energy conversion devices, and micro-nanoscale sensors. Thermal transport caused by lattice vibrations or phonons in nanostructures is very complicated due to the comparable phonon mean-free path, phonon wavelength, and the characteristic size of the nanostructures.
{"title":"Modeling self-heating effects in 10nm channel length nanowire transistors","authors":"A. Hossain, D. Vasileska, S. Goodnick, K. Raleva","doi":"10.1109/SNW.2010.5562566","DOIUrl":"https://doi.org/10.1109/SNW.2010.5562566","url":null,"abstract":"Modern technology has enabled the fabrication of materials with characteristic dimensions of a few nanometers. Examples are superlattices, nanowires and quantum dots. Thermal transport in these low-dimensional nanostructures is important for next-generation microelectronic cooling techniques, novel solid-state energy conversion devices, and micro-nanoscale sensors. Thermal transport caused by lattice vibrations or phonons in nanostructures is very complicated due to the comparable phonon mean-free path, phonon wavelength, and the characteristic size of the nanostructures.","PeriodicalId":6433,"journal":{"name":"2010 Silicon Nanoelectronics Workshop","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87854283","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-01DOI: 10.1109/SNW.2010.5562586
Gerhard Klimeck, Mathieu Luiser
Electron transport is computed in 3nm Si nanowires subject to incoherent scattering from phonons. The electronic structure of the nanowire is represented in an atomistic sp3d5s* tight binding basis. Phonon modes are computed in an atomistic valence force field rather than a continuum deformation potential. Atomistic transport and incoherent scattering are coupled through the non-equilibrium Green function formalism (NEGF) in our new OMEN simulator. Energy loss due to phonon emission is shown to lead to a resistive potential drop in the emitter of the nanowire. Phonon absorption is shown to increase the current in a band-to-band-tunneling configuration.
{"title":"Scattering in Si-nanowires — Where does it matter?","authors":"Gerhard Klimeck, Mathieu Luiser","doi":"10.1109/SNW.2010.5562586","DOIUrl":"https://doi.org/10.1109/SNW.2010.5562586","url":null,"abstract":"Electron transport is computed in 3nm Si nanowires subject to incoherent scattering from phonons. The electronic structure of the nanowire is represented in an atomistic sp3d5s* tight binding basis. Phonon modes are computed in an atomistic valence force field rather than a continuum deformation potential. Atomistic transport and incoherent scattering are coupled through the non-equilibrium Green function formalism (NEGF) in our new OMEN simulator. Energy loss due to phonon emission is shown to lead to a resistive potential drop in the emitter of the nanowire. Phonon absorption is shown to increase the current in a band-to-band-tunneling configuration.","PeriodicalId":6433,"journal":{"name":"2010 Silicon Nanoelectronics Workshop","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87822781","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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