Pub Date : 2010-06-13DOI: 10.1109/SNW.2010.5562595
H. Pal, Dmitri E. Nikonov, Raseong Kim, Mark S. Lundstrom
An approach to include elastic and inelastic electron-phonon scattering into the nonequilibrium Green's function (NEGF) framework that is computationally manageable and applicable to planar MOSFETs has been developed. By reformulating the NEGF equations in terms of integrated transverse momentum modes, the computational burden has been significantly reduced. This allows treatment of both quantum mechanics and dissipative electron-phonon scattering processes for device sizes from nanometers to microns. The formalism is rigorously benchmarked against semiclassical Monte Carlo transport.
{"title":"Electron-phonon scattering in planar MOSFETs with NEGF","authors":"H. Pal, Dmitri E. Nikonov, Raseong Kim, Mark S. Lundstrom","doi":"10.1109/SNW.2010.5562595","DOIUrl":"https://doi.org/10.1109/SNW.2010.5562595","url":null,"abstract":"An approach to include elastic and inelastic electron-phonon scattering into the nonequilibrium Green's function (NEGF) framework that is computationally manageable and applicable to planar MOSFETs has been developed. By reformulating the NEGF equations in terms of integrated transverse momentum modes, the computational burden has been significantly reduced. This allows treatment of both quantum mechanics and dissipative electron-phonon scattering processes for device sizes from nanometers to microns. The formalism is rigorously benchmarked against semiclassical Monte Carlo transport.","PeriodicalId":6433,"journal":{"name":"2010 Silicon Nanoelectronics Workshop","volume":"50 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2010-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74597401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-13DOI: 10.1109/SNW.2010.5562572
G. Du, Tiao Lu, Pingwen Zhang, Xiaoyan Liu, R. Han
The lattice scattering is carefully involved in a direct solution of the BTE and Poisson-Schrodinger equation method. Simulating results of a 9nm DG MOSFET shows the lattice scattering effects on the barrier height and the positions of barrier peak are small, but the effects on the carrier drift velocity are strongly. Not only intra-valley scatterings but also the inter-valley scatterings affect the electron energy, drift velocity and density distribution in channel region strongly. Thus the scattering effect must be considered when discussion carrier energy related device characteristics such as reliability, heat generation.
{"title":"Investigating scattering effects in nano-scale double gate MOSFETs by using direct solution of the Boltzmann transport equation and Poisson-Schrodinger equation method","authors":"G. Du, Tiao Lu, Pingwen Zhang, Xiaoyan Liu, R. Han","doi":"10.1109/SNW.2010.5562572","DOIUrl":"https://doi.org/10.1109/SNW.2010.5562572","url":null,"abstract":"The lattice scattering is carefully involved in a direct solution of the BTE and Poisson-Schrodinger equation method. Simulating results of a 9nm DG MOSFET shows the lattice scattering effects on the barrier height and the positions of barrier peak are small, but the effects on the carrier drift velocity are strongly. Not only intra-valley scatterings but also the inter-valley scatterings affect the electron energy, drift velocity and density distribution in channel region strongly. Thus the scattering effect must be considered when discussion carrier energy related device characteristics such as reliability, heat generation.","PeriodicalId":6433,"journal":{"name":"2010 Silicon Nanoelectronics Workshop","volume":"41 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2010-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75037910","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-13DOI: 10.1109/SNW.2010.5562564
J. Ha, Hee-Sung Kang, Ki‐Won Kim, Ki-Sik Im, Dong‐Seok Kim, Eun-Hwan Kwak, Sung-Nam Kim, Sung-Gil Lee, Jung-Hee Lee
A lateral double diffused metal-oxide-semiconductor transistor (LDMOST) with double work function gate (DWG) structure was fabricated by utilizing silicidation of poly-Si layer. The n+ poly-Si gate in the source side was step-etched and the whole surface of the poly-Si gate was covered with Ni film, followed by self-aligned silicide (salicide) process. The step-etched poly-Si layer in the source side was totally converted to Ni-rich silicide which resulted in a higher work function. On the other hand, in the drain side, only the upper part of thick poly-Si layer was silicided and the non-silicided lower part of the poly-Si layer was considered to be a gate with a lower work function. In DWG structure, the average electric field in the channel is enhanced, which increases electron velocity and thus improves the overall carrier transport efficiency. The fabricated DWG-LDMOST exhibited better device performances, such as 16.4 % improvement in field effect mobility and 3.3 % improvement in sub-threshold slope.
{"title":"Improvement of field effect mobility with dual-work function gate in n-LDMOST by using ni-silicidation of poly-Si gate","authors":"J. Ha, Hee-Sung Kang, Ki‐Won Kim, Ki-Sik Im, Dong‐Seok Kim, Eun-Hwan Kwak, Sung-Nam Kim, Sung-Gil Lee, Jung-Hee Lee","doi":"10.1109/SNW.2010.5562564","DOIUrl":"https://doi.org/10.1109/SNW.2010.5562564","url":null,"abstract":"A lateral double diffused metal-oxide-semiconductor transistor (LDMOST) with double work function gate (DWG) structure was fabricated by utilizing silicidation of poly-Si layer. The n+ poly-Si gate in the source side was step-etched and the whole surface of the poly-Si gate was covered with Ni film, followed by self-aligned silicide (salicide) process. The step-etched poly-Si layer in the source side was totally converted to Ni-rich silicide which resulted in a higher work function. On the other hand, in the drain side, only the upper part of thick poly-Si layer was silicided and the non-silicided lower part of the poly-Si layer was considered to be a gate with a lower work function. In DWG structure, the average electric field in the channel is enhanced, which increases electron velocity and thus improves the overall carrier transport efficiency. The fabricated DWG-LDMOST exhibited better device performances, such as 16.4 % improvement in field effect mobility and 3.3 % improvement in sub-threshold slope.","PeriodicalId":6433,"journal":{"name":"2010 Silicon Nanoelectronics Workshop","volume":"41 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2010-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76296033","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-13DOI: 10.1109/SNW.2010.5562554
Sang Wan Kim, Garam Kim, Wonjoo Kim, Hyoungsoo Ko, Byung-Gook Park
In this paper, a capacitor-less 1T DRAM cell transistor with non-overlap structure and recessed channel is presented. Because of the non-overlap structure between gate and source/drain, GIDL (Gate Induced Drain Leakage) current is efficiently suppressed at hold condition. This results in more than 1 s retention time at 25 °C and 100 ms at 85 °C
本文提出了一种无重叠结构、凹槽沟道的无电容1T DRAM单元晶体管。由于栅极和源漏之间的非重叠结构，在保持状态下可以有效地抑制栅极感应漏电流。这导致在25°C下保持时间超过1 s，在85°C下保持时间超过100 ms
{"title":"Investigation of 1T DRAM cell with non-overlap structure and recessed channel","authors":"Sang Wan Kim, Garam Kim, Wonjoo Kim, Hyoungsoo Ko, Byung-Gook Park","doi":"10.1109/SNW.2010.5562554","DOIUrl":"https://doi.org/10.1109/SNW.2010.5562554","url":null,"abstract":"In this paper, a capacitor-less 1T DRAM cell transistor with non-overlap structure and recessed channel is presented. Because of the non-overlap structure between gate and source/drain, GIDL (Gate Induced Drain Leakage) current is efficiently suppressed at hold condition. This results in more than 1 s retention time at 25 °C and 100 ms at 85 °C","PeriodicalId":6433,"journal":{"name":"2010 Silicon Nanoelectronics Workshop","volume":"36 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2010-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87373323","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
By means of the TEM images, the channel width of (001) silicon pMOSFETs is separated into the flat and rounded corner parts. The underlying stress distribution is obtained via a process simulation. Then, a systematic analysis of the measured drain current leads to a remarkable result: The hole mobility in the non-(001) corner is about two times higher than the (001) flat one, valid for all channel widths involved. This is due to the multi-facets around (110) and (111) orientations. The confirmative evidence is also presented: (i) the increased value of the parameter η in effective field to maintain the mobility universality and (ii) the low frequency noise measurement to ensure the corner gate oxide integrity. Therefore, the non-(001) p-channel sidewall corner formed on (001) substrate can constitute a promising narrow device.
{"title":"Enhanced hole mobility in non-(001) oriented sidewall corner of Si pMOSFETs formed on (001) substrate","authors":"Chih-Yu Hsu, Hua-Gang Chang, Shin-Jiun Kuang, Wei Lee, Yu‐Cheng Chen, Chien‐Chih Lee, Ming-Jer Chen","doi":"10.1109/SNW.2010.5562565","DOIUrl":"https://doi.org/10.1109/SNW.2010.5562565","url":null,"abstract":"By means of the TEM images, the channel width of (001) silicon pMOSFETs is separated into the flat and rounded corner parts. The underlying stress distribution is obtained via a process simulation. Then, a systematic analysis of the measured drain current leads to a remarkable result: The hole mobility in the non-(001) corner is about two times higher than the (001) flat one, valid for all channel widths involved. This is due to the multi-facets around (110) and (111) orientations. The confirmative evidence is also presented: (i) the increased value of the parameter η in effective field to maintain the mobility universality and (ii) the low frequency noise measurement to ensure the corner gate oxide integrity. Therefore, the non-(001) p-channel sidewall corner formed on (001) substrate can constitute a promising narrow device.","PeriodicalId":6433,"journal":{"name":"2010 Silicon Nanoelectronics Workshop","volume":"35 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2010-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79360735","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-13DOI: 10.1109/SNW.2010.5562556
Jung-Shik Jang, W. Choi
A new transistor parameter “ambipolarity factor (ν)” has been defined for SOI tunneling field-effect transistors (TFETs) and its usefulness has been discussed. The proposed ν indicates the severity of ambipolarity of TFETs quantitatively. Therefore, it is expected that ν will be helpful to suppressing OFF current for low-power consumption.
{"title":"Ambipolarity characterization of tunneling field-effect transistors","authors":"Jung-Shik Jang, W. Choi","doi":"10.1109/SNW.2010.5562556","DOIUrl":"https://doi.org/10.1109/SNW.2010.5562556","url":null,"abstract":"A new transistor parameter “ambipolarity factor (ν)” has been defined for SOI tunneling field-effect transistors (TFETs) and its usefulness has been discussed. The proposed ν indicates the severity of ambipolarity of TFETs quantitatively. Therefore, it is expected that ν will be helpful to suppressing OFF current for low-power consumption.","PeriodicalId":6433,"journal":{"name":"2010 Silicon Nanoelectronics Workshop","volume":"7 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2010-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74875933","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-13DOI: 10.1109/SNW.2010.5562576
T. Kodera, G. Yamahata, T. Kambara, K. Horibe, K. Uchida, C. Marcus, S. Oda
We realized lithographically-defined electrically-tunable silicon quantum dots (Si QDs) without unintentional localized potentials by improving device structures and fabrication techniques. Carrier density was tuned with a top gate and QD-potentials were controlled with the side gates. We succeeded in observing spin-related tunneling phenomena using the double QD device.
{"title":"Spin-related tunneling in lithographically-defined silicon quantum dots","authors":"T. Kodera, G. Yamahata, T. Kambara, K. Horibe, K. Uchida, C. Marcus, S. Oda","doi":"10.1109/SNW.2010.5562576","DOIUrl":"https://doi.org/10.1109/SNW.2010.5562576","url":null,"abstract":"We realized lithographically-defined electrically-tunable silicon quantum dots (Si QDs) without unintentional localized potentials by improving device structures and fabrication techniques. Carrier density was tuned with a top gate and QD-potentials were controlled with the side gates. We succeeded in observing spin-related tunneling phenomena using the double QD device.","PeriodicalId":6433,"journal":{"name":"2010 Silicon Nanoelectronics Workshop","volume":"9 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2010-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78277869","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-13DOI: 10.1109/SNW.2010.5562545
Jeong-Hoon Oh, K. Ryoo, Sunghun Jung, Kyung Seok Oh, Hyungcheol Shin, Byung-Gook Park
The effects of Al layer and plasma oxidation amount on TiO2 based bipolar RRAM cell are investigated, respectively. In Ir/Al/TiO2/Ir structure, VRESET is slightly lowered and the current ratio is increased. In case of plasma oxidation effect, the device which experienced short-time plasma oxidation has low set/reset voltages and high current and resistance ratios. These results are commonly thought to be induced by more oxygen vacancies.
{"title":"Effects of aluminum layer and oxidation on TiO2 based bipolar resistive random access memory (RRAM)","authors":"Jeong-Hoon Oh, K. Ryoo, Sunghun Jung, Kyung Seok Oh, Hyungcheol Shin, Byung-Gook Park","doi":"10.1109/SNW.2010.5562545","DOIUrl":"https://doi.org/10.1109/SNW.2010.5562545","url":null,"abstract":"The effects of Al layer and plasma oxidation amount on TiO2 based bipolar RRAM cell are investigated, respectively. In Ir/Al/TiO2/Ir structure, VRESET is slightly lowered and the current ratio is increased. In case of plasma oxidation effect, the device which experienced short-time plasma oxidation has low set/reset voltages and high current and resistance ratios. These results are commonly thought to be induced by more oxygen vacancies.","PeriodicalId":6433,"journal":{"name":"2010 Silicon Nanoelectronics Workshop","volume":"42 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2010-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79982415","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-13DOI: 10.1109/SNW.2010.5562575
K. Wada
DWDM should be an enabler of multi Tbps operation of Electronics and Photonics Integrated Circuits. To implement the photonic components into Si LSIs, one of the highest hurdles is temperature fluctuation of the chip leading wavelength fluctuation. Si NEMS Photonics has been proposed to stabilize wavelength in terms of strain.
{"title":"Challenges of Si-LSIs integrated with optical components","authors":"K. Wada","doi":"10.1109/SNW.2010.5562575","DOIUrl":"https://doi.org/10.1109/SNW.2010.5562575","url":null,"abstract":"DWDM should be an enabler of multi Tbps operation of Electronics and Photonics Integrated Circuits. To implement the photonic components into Si LSIs, one of the highest hurdles is temperature fluctuation of the chip leading wavelength fluctuation. Si NEMS Photonics has been proposed to stabilize wavelength in terms of strain.","PeriodicalId":6433,"journal":{"name":"2010 Silicon Nanoelectronics Workshop","volume":"52 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2010-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75870738","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-06-13DOI: 10.1109/SNW.2010.5562559
Yunxiang Yang, Xiaoyan Liu, G. Du, R. Han
Statistical 3D TCAD simulations of 20nm gate SOTB MOSFETs have been done to study the effects of TBox, Vback-gate and WF on LER-induced variability. Our results show that thin box, reverse back-gate bias and high WF are effective ways to control the LER-induced threshold voltage's variations, especially for n-SOTB MOSFETs.
{"title":"Variability induced by Line edge roughness in silicon on thin box (SOTB) MOSFETs","authors":"Yunxiang Yang, Xiaoyan Liu, G. Du, R. Han","doi":"10.1109/SNW.2010.5562559","DOIUrl":"https://doi.org/10.1109/SNW.2010.5562559","url":null,"abstract":"Statistical 3D TCAD simulations of 20nm gate SOTB MOSFETs have been done to study the effects of TBox, Vback-gate and WF on LER-induced variability. Our results show that thin box, reverse back-gate bias and high WF are effective ways to control the LER-induced threshold voltage's variations, especially for n-SOTB MOSFETs.","PeriodicalId":6433,"journal":{"name":"2010 Silicon Nanoelectronics Workshop","volume":"70 1 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2010-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77511880","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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