Pub Date : 2004-05-23DOI: 10.1109/ISCAS.2004.1328277
Zhongjun Yu, Degang Chen, R. Geiger
Analog to digital converter (ADC) is the world's largest volume mixed-signal circuit. It is also a key building block in nearly all system on chip (SoC) solutions involving analog and mixed-signal functionalities. ADC testing is also crucial for built-in-self-test (BIST) solutions of AMS testing in SoC technology which is identified by the ITRS as one of four most daunting SoC challenges. ADC spectral testing is of critical importance to a large class of integrated circuits and is particularly challenging for high speed and/or high resolutions circuits. In this paper we use spectrally related excitations (SRE) to accurately test the spectral performance of ADCs. Unlike standard approaches, the SRE approach uses low-cost imprecise sine signals as input to the ADC and uses the spectral relationship between multiple input signals to separate distortion inherent in the ADC from that in the input. Efficient DSP algorithms are used to determine the true spectral performance of the ADC. This approach works in both production test and BIST environments. Simulation results show two sine waves with < 60 dB purity can be used to accurately test spectral performance of high resolution ADCs with SFDR in excess of 100 dB. The low-cost SRE signals can be readily generated with simple RC filters with lax band edge requirements. Extensive simulation shows that the algorithm is robust to filter errors, to nonstationary in the test environment, and to measurement noise.
{"title":"Accurate testing of ADC's spectral performance using imprecise sinusoidal excitations","authors":"Zhongjun Yu, Degang Chen, R. Geiger","doi":"10.1109/ISCAS.2004.1328277","DOIUrl":"https://doi.org/10.1109/ISCAS.2004.1328277","url":null,"abstract":"Analog to digital converter (ADC) is the world's largest volume mixed-signal circuit. It is also a key building block in nearly all system on chip (SoC) solutions involving analog and mixed-signal functionalities. ADC testing is also crucial for built-in-self-test (BIST) solutions of AMS testing in SoC technology which is identified by the ITRS as one of four most daunting SoC challenges. ADC spectral testing is of critical importance to a large class of integrated circuits and is particularly challenging for high speed and/or high resolutions circuits. In this paper we use spectrally related excitations (SRE) to accurately test the spectral performance of ADCs. Unlike standard approaches, the SRE approach uses low-cost imprecise sine signals as input to the ADC and uses the spectral relationship between multiple input signals to separate distortion inherent in the ADC from that in the input. Efficient DSP algorithms are used to determine the true spectral performance of the ADC. This approach works in both production test and BIST environments. Simulation results show two sine waves with < 60 dB purity can be used to accurately test spectral performance of high resolution ADCs with SFDR in excess of 100 dB. The low-cost SRE signals can be readily generated with simple RC filters with lax band edge requirements. Extensive simulation shows that the algorithm is robust to filter errors, to nonstationary in the test environment, and to measurement noise.","PeriodicalId":6445,"journal":{"name":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)","volume":"14 1","pages":"I-645"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81930988","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-23DOI: 10.1109/ISCAS.2004.1329471
H. Klimach, A. Arnaud, M. C. Schneider, C. Galup-Montoro
This work presents an approach for accurate MOS transistor matching calculation. Our model, which is based on an accurate physics-based MOSFET model, allows the assessment of mismatch from process parameters and valid for any operating region. Experimental results taken on a test set of transistors implemented in a 1.2 /spl mu/m CMOS technology corroborate the theoretical development of this work.
本文提出了一种精确的MOS晶体管匹配计算方法。我们的模型基于精确的基于物理的MOSFET模型，允许评估工艺参数的不匹配，并且对任何操作区域都有效。在1.2 /spl μ m CMOS技术上实现的晶体管测试组上的实验结果证实了本工作的理论发展。
{"title":"Consistent model for drain current mismatch in MOSFETs using the carrier number fluctuation theory","authors":"H. Klimach, A. Arnaud, M. C. Schneider, C. Galup-Montoro","doi":"10.1109/ISCAS.2004.1329471","DOIUrl":"https://doi.org/10.1109/ISCAS.2004.1329471","url":null,"abstract":"This work presents an approach for accurate MOS transistor matching calculation. Our model, which is based on an accurate physics-based MOSFET model, allows the assessment of mismatch from process parameters and valid for any operating region. Experimental results taken on a test set of transistors implemented in a 1.2 /spl mu/m CMOS technology corroborate the theoretical development of this work.","PeriodicalId":6445,"journal":{"name":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)","volume":"88 1","pages":"V-V"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84315283","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-23DOI: 10.1109/ISCAS.2004.1329416
P. Kitsos, O. Koufopavlou
New encryption algorithms have to operate in a variety of current and future applications demanding both high speed and high security. An architecture and VLSI implementation of the newest standard in the hash families, Whirlpool that achieves high-speed performance is presented. The architecture permits a wide variety of implementation tradeoffs. The design was coded using VHDL language and for the hardware implementation a FPGA device was used. While no other previous Whirlpool implementation exist, the comparison with previous hash families' implementations such as MD5, SHA-1, SHA-2 etc are given. These comparisons prove that the Whirlpool implementation is much faster compared with these previous implementations.
{"title":"Whirlpool hash function: architecture and VLSI implementation","authors":"P. Kitsos, O. Koufopavlou","doi":"10.1109/ISCAS.2004.1329416","DOIUrl":"https://doi.org/10.1109/ISCAS.2004.1329416","url":null,"abstract":"New encryption algorithms have to operate in a variety of current and future applications demanding both high speed and high security. An architecture and VLSI implementation of the newest standard in the hash families, Whirlpool that achieves high-speed performance is presented. The architecture permits a wide variety of implementation tradeoffs. The design was coded using VHDL language and for the hardware implementation a FPGA device was used. While no other previous Whirlpool implementation exist, the comparison with previous hash families' implementations such as MD5, SHA-1, SHA-2 etc are given. These comparisons prove that the Whirlpool implementation is much faster compared with these previous implementations.","PeriodicalId":6445,"journal":{"name":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)","volume":"53 1","pages":"II-893"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84346137","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-23DOI: 10.1109/ISCAS.2004.1329052
Andrea Arcangeli, S. Squartini, F. Piazza
This paper proposes a new approach for calculation of derivatives in general multirate systems through a signal flow graph (SFG) technique. The first original aspect consists of the derivation of an adjoint graph without using Lee's theorem. Secondly, such a graph is able to deliver not only the first derivatives but also the full second derivatives of an output of the initial system with respect to the node variables of the starting SFG. Some examples are reported to show the right way of working of the proposed method on derivative calculation in general situations. Hence, the overall algorithm represents a useful tool for determination of Jacobean and Hessian based information in learning systems, as was already done in other related but less general contributions in the literature.
{"title":"Calculation of non-mixed second derivatives in multirate systems through signal flow graph techniques","authors":"Andrea Arcangeli, S. Squartini, F. Piazza","doi":"10.1109/ISCAS.2004.1329052","DOIUrl":"https://doi.org/10.1109/ISCAS.2004.1329052","url":null,"abstract":"This paper proposes a new approach for calculation of derivatives in general multirate systems through a signal flow graph (SFG) technique. The first original aspect consists of the derivation of an adjoint graph without using Lee's theorem. Secondly, such a graph is able to deliver not only the first derivatives but also the full second derivatives of an output of the initial system with respect to the node variables of the starting SFG. Some examples are reported to show the right way of working of the proposed method on derivative calculation in general situations. Hence, the overall algorithm represents a useful tool for determination of Jacobean and Hessian based information in learning systems, as was already done in other related but less general contributions in the literature.","PeriodicalId":6445,"journal":{"name":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)","volume":"60 1","pages":"IV-509"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84474954","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-23DOI: 10.1109/ISCAS.2004.1329934
T. Ensari, S. Arik, V. Tavsanoglu
This work presents a new sufficient condition for the uniqueness and global asymptotic stability (GAS) of the equilibrium point for a larger class of neural networks with time varying delays. It is shown that the use of a more general type of Lyapunov-Krasovskii functional leads to establish global asymptotic stability of a larger class of delayed neural networks that the neural network model considered in some previous papers.
{"title":"Global asymptotic stability of a class of neural networks with time varying delays","authors":"T. Ensari, S. Arik, V. Tavsanoglu","doi":"10.1109/ISCAS.2004.1329934","DOIUrl":"https://doi.org/10.1109/ISCAS.2004.1329934","url":null,"abstract":"This work presents a new sufficient condition for the uniqueness and global asymptotic stability (GAS) of the equilibrium point for a larger class of neural networks with time varying delays. It is shown that the use of a more general type of Lyapunov-Krasovskii functional leads to establish global asymptotic stability of a larger class of delayed neural networks that the neural network model considered in some previous papers.","PeriodicalId":6445,"journal":{"name":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)","volume":"61 1","pages":"V-V"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84901567","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-23DOI: 10.1109/ISCAS.2004.1329932
Juan-juan Gu, L. Tao, H. Kwan
An L2 soft margin support vector machine (L2 SVM) is introduced in this paper. What is unusual for the SVM is that the dual problem for the constrained optimization of the SVM is a convex quadratic problem with simple bound constraints. The active set iteration method for this optimization problem is applied as fast learning algorithm for the SVM, and the selection of the initial active/inactive sets is discussed. For incremental learning and large-scale learning problems, a fast incremental learning algorithm for the SVM is presented. Computational experiments show the efficiency of the proposed algorithm.
{"title":"Fast learning algorithms for new L2 SVM based on active set iteration method","authors":"Juan-juan Gu, L. Tao, H. Kwan","doi":"10.1109/ISCAS.2004.1329932","DOIUrl":"https://doi.org/10.1109/ISCAS.2004.1329932","url":null,"abstract":"An L2 soft margin support vector machine (L2 SVM) is introduced in this paper. What is unusual for the SVM is that the dual problem for the constrained optimization of the SVM is a convex quadratic problem with simple bound constraints. The active set iteration method for this optimization problem is applied as fast learning algorithm for the SVM, and the selection of the initial active/inactive sets is discussed. For incremental learning and large-scale learning problems, a fast incremental learning algorithm for the SVM is presented. Computational experiments show the efficiency of the proposed algorithm.","PeriodicalId":6445,"journal":{"name":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)","volume":"60 1","pages":"V-V"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84947602","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-23DOI: 10.1109/ISCAS.2004.1328117
K. El-Sankary, M. Sawan
A digital background calibration technique to compensate for the finite opamps dc gain in pipelined analog-to-digital converters is presented. By transforming the ADC and measuring the gain ratios between different configurations, a background calibration is possible without interrupting the ADC operation or injecting a calibration signal. A modified multiplying digital-to-analog converter (MDAC) is proposed. This new MDAC allows the ADC to toggle between different configurations to create a reference signal used for the calibration. Simulations results prove the effectiveness of this new method.
{"title":"A new digital background calibration technique for pipelined ADC","authors":"K. El-Sankary, M. Sawan","doi":"10.1109/ISCAS.2004.1328117","DOIUrl":"https://doi.org/10.1109/ISCAS.2004.1328117","url":null,"abstract":"A digital background calibration technique to compensate for the finite opamps dc gain in pipelined analog-to-digital converters is presented. By transforming the ADC and measuring the gain ratios between different configurations, a background calibration is possible without interrupting the ADC operation or injecting a calibration signal. A modified multiplying digital-to-analog converter (MDAC) is proposed. This new MDAC allows the ADC to toggle between different configurations to create a reference signal used for the calibration. Simulations results prove the effectiveness of this new method.","PeriodicalId":6445,"journal":{"name":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)","volume":"23 1","pages":"I-I"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85012279","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-23DOI: 10.1109/ISCAS.2004.1329264
T. Yamanaka, V. Moshnyaga
Design of portable battery operated multimedia devices requires energy-efficient multiplication circuits. This paper proposes a new technique to reduce power consumption of digital multipliers. In contrast to related methods which concentrate on transition activity reduction, we focus on dynamic reduction of supply voltage. Two implementation schemes capable of dynamically adjusting a double voltage supply to input data variation are presented. Simulations show that using these schemes we can reduce energy consumption of 16/spl times/16 bit multiplier in DCT computation by 33.4% and 25.2% on average without any speed degradation and as low as 4.7% area overhead.
{"title":"Reducing multiplier energy by data-driven voltage variation","authors":"T. Yamanaka, V. Moshnyaga","doi":"10.1109/ISCAS.2004.1329264","DOIUrl":"https://doi.org/10.1109/ISCAS.2004.1329264","url":null,"abstract":"Design of portable battery operated multimedia devices requires energy-efficient multiplication circuits. This paper proposes a new technique to reduce power consumption of digital multipliers. In contrast to related methods which concentrate on transition activity reduction, we focus on dynamic reduction of supply voltage. Two implementation schemes capable of dynamically adjusting a double voltage supply to input data variation are presented. Simulations show that using these schemes we can reduce energy consumption of 16/spl times/16 bit multiplier in DCT computation by 33.4% and 25.2% on average without any speed degradation and as low as 4.7% area overhead.","PeriodicalId":6445,"journal":{"name":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)","volume":"27 1","pages":"II-285"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85144087","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-23DOI: 10.1109/ISCAS.2004.1329507
Yang Wang, Yici Cai, Xianlong Hong, Qiang Zhou
As the development of VLSI technique, the critical dimension of IC has become smaller than the exposure wavelength. Due to the diffraction and interaction of optical waves, deformations between the image on wafer and the feature on layout are undeniable. This results in bad performance or even invalid circuits of the chips. OPC is critical compensation technique to correct the deformations on wafer images. This work presents a layout correction and optimization algorithm called MOPC; it's a flexible and efficient core for the model-based OPC system. Since we divide the target features into different types before correction, the OPE between the target features and the environment features and the OPE between the neighboring segments of the inside feature are both considered during the correction.
{"title":"Algorithm for yield driven correction of layout","authors":"Yang Wang, Yici Cai, Xianlong Hong, Qiang Zhou","doi":"10.1109/ISCAS.2004.1329507","DOIUrl":"https://doi.org/10.1109/ISCAS.2004.1329507","url":null,"abstract":"As the development of VLSI technique, the critical dimension of IC has become smaller than the exposure wavelength. Due to the diffraction and interaction of optical waves, deformations between the image on wafer and the feature on layout are undeniable. This results in bad performance or even invalid circuits of the chips. OPC is critical compensation technique to correct the deformations on wafer images. This work presents a layout correction and optimization algorithm called MOPC; it's a flexible and efficient core for the model-based OPC system. Since we divide the target features into different types before correction, the OPE between the target features and the environment features and the OPE between the neighboring segments of the inside feature are both considered during the correction.","PeriodicalId":6445,"journal":{"name":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)","volume":"50 1","pages":"V-V"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85144510","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-23DOI: 10.1109/ISCAS.2004.1329529
C. Kodama, K. Fujiyoshi, Teppei Koga
The sequence-pair was proposed to represent a rectangle packing and a placement, and is used to place modules automatically in VLSI layout design. Several decoding methods of sequence-pair were proposed. However, encoding methods are not found except the original one called "gridding". The gridding requires almost O(n/sup 3/) time for a packing of n rectangular modules and it is hard to implement. Therefore, we propose a novel method to encode a given rectangle packing into a sequence-pair in O(n log n) time. We also propose a linear time method to obtain a sequence-pair from a given rectangular dissection represented by a Q-sequence, a recently proposed representation method of rectangular dissection. The proposed methods can be used for the compaction keeping topology, for example, in the post-process of the force directed relaxation, a method used in module placement, and so on.
{"title":"A novel encoding method into sequence-pair","authors":"C. Kodama, K. Fujiyoshi, Teppei Koga","doi":"10.1109/ISCAS.2004.1329529","DOIUrl":"https://doi.org/10.1109/ISCAS.2004.1329529","url":null,"abstract":"The sequence-pair was proposed to represent a rectangle packing and a placement, and is used to place modules automatically in VLSI layout design. Several decoding methods of sequence-pair were proposed. However, encoding methods are not found except the original one called \"gridding\". The gridding requires almost O(n/sup 3/) time for a packing of n rectangular modules and it is hard to implement. Therefore, we propose a novel method to encode a given rectangle packing into a sequence-pair in O(n log n) time. We also propose a linear time method to obtain a sequence-pair from a given rectangular dissection represented by a Q-sequence, a recently proposed representation method of rectangular dissection. The proposed methods can be used for the compaction keeping topology, for example, in the post-process of the force directed relaxation, a method used in module placement, and so on.","PeriodicalId":6445,"journal":{"name":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)","volume":"20 1","pages":"V-V"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85212826","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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