Pub Date : 2004-05-23DOI: 10.1109/ISCAS.2004.1328769
Che-Hong Chen, Bin-Da Liu, J. Yang
In this paper, the efficient recursive structure for computing arbitrary length M-dimensional (M-D) discrete cosine transform (DCT) is proposed. The M-D DCT are first converted into condensed one-dimensional DCT and discrete sine transform (DST) with a regular preprocess procedure. Using Chebyshev polynomials, the recursive filters for condensed 1-D DCT/DST are then derived to compute M-D DCT without involving any data transposition. The proposed structure requires fewer recursive loops than the traditional 1-D recursive structures, which are realized in M passes and (M-1) data transposition by the so-called row-column approach. With advantages of fewer recursive loops and no transposition memory, the proposed structures attain more accurate results and less power consumption than the existed ones, which are realized in the row-column approach. With regular and modular features, the proposed recursive M-D DCT structure is suitable for VLSI implementation.
{"title":"Condensed recursive structures for computing multi-dimensional DCT with arbitrary length","authors":"Che-Hong Chen, Bin-Da Liu, J. Yang","doi":"10.1109/ISCAS.2004.1328769","DOIUrl":"https://doi.org/10.1109/ISCAS.2004.1328769","url":null,"abstract":"In this paper, the efficient recursive structure for computing arbitrary length M-dimensional (M-D) discrete cosine transform (DCT) is proposed. The M-D DCT are first converted into condensed one-dimensional DCT and discrete sine transform (DST) with a regular preprocess procedure. Using Chebyshev polynomials, the recursive filters for condensed 1-D DCT/DST are then derived to compute M-D DCT without involving any data transposition. The proposed structure requires fewer recursive loops than the traditional 1-D recursive structures, which are realized in M passes and (M-1) data transposition by the so-called row-column approach. With advantages of fewer recursive loops and no transposition memory, the proposed structures attain more accurate results and less power consumption than the existed ones, which are realized in the row-column approach. With regular and modular features, the proposed recursive M-D DCT structure is suitable for VLSI implementation.","PeriodicalId":6445,"journal":{"name":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)","volume":"134 1","pages":"III-405"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80030470","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-23DOI: 10.1109/ISCAS.2004.1328797
R. K. Sande, A. Balasubramanian
This paper describes an efficient structure to implement a system consisting of an M-channel synthesis filterbank followed by an L-channel analysis filterbank (where M is a multiple of L or L is a multiple of M). The structure is very efficient in VLSI, FPGA or parallel processor implementation in terms of requiring less area or logic blocks, lower power consumption and extending the degree of parallelism. The proposed method is applicable in situations where a subband based processing or encoding follows another subband based processing or decoding and the intermediate synthesized signal is not a desired signal in itself.
{"title":"An efficient VLSI/FPGA architecture for combining an analysis filterbank following a synthesis filterbank","authors":"R. K. Sande, A. Balasubramanian","doi":"10.1109/ISCAS.2004.1328797","DOIUrl":"https://doi.org/10.1109/ISCAS.2004.1328797","url":null,"abstract":"This paper describes an efficient structure to implement a system consisting of an M-channel synthesis filterbank followed by an L-channel analysis filterbank (where M is a multiple of L or L is a multiple of M). The structure is very efficient in VLSI, FPGA or parallel processor implementation in terms of requiring less area or logic blocks, lower power consumption and extending the degree of parallelism. The proposed method is applicable in situations where a subband based processing or encoding follows another subband based processing or decoding and the intermediate synthesized signal is not a desired signal in itself.","PeriodicalId":6445,"journal":{"name":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)","volume":"8 1","pages":"III-517"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80038915","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-23DOI: 10.1109/ISCAS.2004.1329326
A. Pappu, A. Apsel
In this paper, we calculate the benefits of electrical isolation for intra-chip optical interconnects. We compare the delay and energy metrics of systems with intra-chip electrical and optical fanout, and from the results obtained, we conclude that optical fanout can be used to improve speeds in electrical fanout systems even at very short on-chip distances.
{"title":"Electrical isolation and fanout in intra-chip optical interconnects","authors":"A. Pappu, A. Apsel","doi":"10.1109/ISCAS.2004.1329326","DOIUrl":"https://doi.org/10.1109/ISCAS.2004.1329326","url":null,"abstract":"In this paper, we calculate the benefits of electrical isolation for intra-chip optical interconnects. We compare the delay and energy metrics of systems with intra-chip electrical and optical fanout, and from the results obtained, we conclude that optical fanout can be used to improve speeds in electrical fanout systems even at very short on-chip distances.","PeriodicalId":6445,"journal":{"name":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)","volume":"54 1","pages":"II-533"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80270116","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-23DOI: 10.1109/ISCAS.2004.1329062
M. Siripruchyanun, P. Koseeyaporn, J. Koseeyaporn, P. Wardkein
In this article, a sinusoidal oscillator, AM and FM signal generator based on translinear current conveyors is introduced. The frequency and amplitude of the proposed circuit can be controlled by the bias currents. When an input current is applied as an information signal to the first and the second CCCII+s (Current Controlled Current Conveyors), the network functions as an FM signal generator. Contrarily, an AM signal is obtained by employing such information signals applied to the third CCCII+. In addition, this network simultaneously produces two signals that are 90/spl deg/ different in phase resulting in quadrature sinusoidal signals. This circuit consists of three CCCII+s and two grounded capacitors where, without any external resistors, this circuit is then suitable for IC architecture. The PSPICE simulation results are depicted. The given results agree well with the theoretical anticipation where the power consumption is approximately 2.4 mW.
{"title":"Fully current controllable AM/FM modulator and quadrature sinusoidal oscillator based on CCCIIs","authors":"M. Siripruchyanun, P. Koseeyaporn, J. Koseeyaporn, P. Wardkein","doi":"10.1109/ISCAS.2004.1329062","DOIUrl":"https://doi.org/10.1109/ISCAS.2004.1329062","url":null,"abstract":"In this article, a sinusoidal oscillator, AM and FM signal generator based on translinear current conveyors is introduced. The frequency and amplitude of the proposed circuit can be controlled by the bias currents. When an input current is applied as an information signal to the first and the second CCCII+s (Current Controlled Current Conveyors), the network functions as an FM signal generator. Contrarily, an AM signal is obtained by employing such information signals applied to the third CCCII+. In addition, this network simultaneously produces two signals that are 90/spl deg/ different in phase resulting in quadrature sinusoidal signals. This circuit consists of three CCCII+s and two grounded capacitors where, without any external resistors, this circuit is then suitable for IC architecture. The PSPICE simulation results are depicted. The given results agree well with the theoretical anticipation where the power consumption is approximately 2.4 mW.","PeriodicalId":6445,"journal":{"name":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)","volume":"113 1","pages":"IV-549"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80531130","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-23DOI: 10.1109/ISCAS.2004.1328287
M. Panovic, A. Demosthenous
This paper describes a low voltage/low power MOS linear transconductor which can be configured to realize a square-law function circuit and a four quadrant analogue multiplier. The compact analogue computation cells described are particularly suited to parallel processing systems. The circuits were fabricated using a 0.8 /spl mu/m CMOS process and operate from a 2 V power supply.
{"title":"Compact CMOS linear transconductor and four-quadrant analogue multiplier","authors":"M. Panovic, A. Demosthenous","doi":"10.1109/ISCAS.2004.1328287","DOIUrl":"https://doi.org/10.1109/ISCAS.2004.1328287","url":null,"abstract":"This paper describes a low voltage/low power MOS linear transconductor which can be configured to realize a square-law function circuit and a four quadrant analogue multiplier. The compact analogue computation cells described are particularly suited to parallel processing systems. The circuits were fabricated using a 0.8 /spl mu/m CMOS process and operate from a 2 V power supply.","PeriodicalId":6445,"journal":{"name":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)","volume":"18 1","pages":"I-685"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79354238","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-23DOI: 10.1109/ISCAS.2004.1329318
K. Parhi
The convolutional codes are widely used in many communication systems due to their excellent error control performance. High speed Viterbi decoders for convolutional codes are of great interest for high data rate applications. In this paper, an improved most-significant-bit (MSB)-first bit-level pipelined add-compare select (ACS) unit structure is proposed. The ACS unit is the main bottleneck on the decoding speed of a Viterbi decoder. By balancing the settling time of different paths in the ACS unit, the length of the critical path is reduced as close as possible to the iteration bound in the ACS unit. With the proposed retimed structure, it is possible to decrease the critical path of the ACS unit by 12 to 15% compared with the conventional MSB-first structures. This reduction in critical path can reduce the level of parallelism (and area) required for a very highspeed (such as 10 Gbps) Viterbi decoder by about 25%.
{"title":"Novel pipelining of MSB-first add-compare select unit structure for Viterbi decoders","authors":"K. Parhi","doi":"10.1109/ISCAS.2004.1329318","DOIUrl":"https://doi.org/10.1109/ISCAS.2004.1329318","url":null,"abstract":"The convolutional codes are widely used in many communication systems due to their excellent error control performance. High speed Viterbi decoders for convolutional codes are of great interest for high data rate applications. In this paper, an improved most-significant-bit (MSB)-first bit-level pipelined add-compare select (ACS) unit structure is proposed. The ACS unit is the main bottleneck on the decoding speed of a Viterbi decoder. By balancing the settling time of different paths in the ACS unit, the length of the critical path is reduced as close as possible to the iteration bound in the ACS unit. With the proposed retimed structure, it is possible to decrease the critical path of the ACS unit by 12 to 15% compared with the conventional MSB-first structures. This reduction in critical path can reduce the level of parallelism (and area) required for a very highspeed (such as 10 Gbps) Viterbi decoder by about 25%.","PeriodicalId":6445,"journal":{"name":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)","volume":"31 1","pages":"II-501"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81275910","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-23DOI: 10.1109/ISCAS.2004.1328688
L. Vesalainen, J. Poikonen, Mikko Pänkäälä, A. Paasio
Analog to digital converters are used in extremely many applications to convert real world signals into digital words. The converter presented in this paper, is designed for a cellular nonlinear network type system, where A/D converters are included in each cell to transform the gray scale value to be stored in a 6 bit SRAM memory bank. Because of this, the converter structure should have small silicon area, low power consumption and easy controlling. Presented ADC fulfills these requirements.
{"title":"A gray-code current-mode ADC for mixed-mode cellular computer","authors":"L. Vesalainen, J. Poikonen, Mikko Pänkäälä, A. Paasio","doi":"10.1109/ISCAS.2004.1328688","DOIUrl":"https://doi.org/10.1109/ISCAS.2004.1328688","url":null,"abstract":"Analog to digital converters are used in extremely many applications to convert real world signals into digital words. The converter presented in this paper, is designed for a cellular nonlinear network type system, where A/D converters are included in each cell to transform the gray scale value to be stored in a 6 bit SRAM memory bank. Because of this, the converter structure should have small silicon area, low power consumption and easy controlling. Presented ADC fulfills these requirements.","PeriodicalId":6445,"journal":{"name":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)","volume":"66 sup6 1","pages":"III-81"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81527015","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-23DOI: 10.1109/ISCAS.2004.1329382
Yongjun Xu, Zuying Luo, Xiaowei Li
As transistor size continues to scale down, leakage power has become a critical issue of integrated circuit design. The maximum total leakage current, which is mainly determined by the sum of subthreshold, gate and reverse biased junction BTBT leakage current, is an important parameter to guide low-leakage and high-performance circuit designs. Up to now, how to estimate the maximum leakage current accurately within endurable time remains unsolved. Precise simulators can calculate leakage current accurately, but are only practical for small circuits. In this paper, a fast maximum leakage current estimation method is introduced accompanied with our gate-level leakage current simulator called iLeakage. Experiments on ISCAS circuit suits show that the simulator is significantly accelerated under acceptable error compared with HSPICE and the algorithm is applicable for large circuits.
{"title":"A maximum total leakage current estimation method","authors":"Yongjun Xu, Zuying Luo, Xiaowei Li","doi":"10.1109/ISCAS.2004.1329382","DOIUrl":"https://doi.org/10.1109/ISCAS.2004.1329382","url":null,"abstract":"As transistor size continues to scale down, leakage power has become a critical issue of integrated circuit design. The maximum total leakage current, which is mainly determined by the sum of subthreshold, gate and reverse biased junction BTBT leakage current, is an important parameter to guide low-leakage and high-performance circuit designs. Up to now, how to estimate the maximum leakage current accurately within endurable time remains unsolved. Precise simulators can calculate leakage current accurately, but are only practical for small circuits. In this paper, a fast maximum leakage current estimation method is introduced accompanied with our gate-level leakage current simulator called iLeakage. Experiments on ISCAS circuit suits show that the simulator is significantly accelerated under acceptable error compared with HSPICE and the algorithm is applicable for large circuits.","PeriodicalId":6445,"journal":{"name":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)","volume":"36 1","pages":"II-757"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81591573","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-23DOI: 10.1109/ISCAS.2004.1329384
Minyi Fu, G. Jullien, V. Dimitrov, M. Ahmadi
This paper discusses the application of a new two dimensional algebraic integer encoding scheme for the design of a DCT processor core for JPEG and MPEG applications. The paper concentrates on the efficient implementation of a 2D algebraic integer encoding procedure. The processor takes advantage of the low complexity, multiplierless, high-precision nature of the algebraic integer encoding scheme to achieve low power consumption. Test results from a proof-of-concept 0.18 /spl mu/m CMOS 8/spl times/8 DCT chip demonstrate a low power dissipation of 7.5 mW at 75 MHz.
{"title":"A low-power DCT IP core based on 2D algebraic integer encoding","authors":"Minyi Fu, G. Jullien, V. Dimitrov, M. Ahmadi","doi":"10.1109/ISCAS.2004.1329384","DOIUrl":"https://doi.org/10.1109/ISCAS.2004.1329384","url":null,"abstract":"This paper discusses the application of a new two dimensional algebraic integer encoding scheme for the design of a DCT processor core for JPEG and MPEG applications. The paper concentrates on the efficient implementation of a 2D algebraic integer encoding procedure. The processor takes advantage of the low complexity, multiplierless, high-precision nature of the algebraic integer encoding scheme to achieve low power consumption. Test results from a proof-of-concept 0.18 /spl mu/m CMOS 8/spl times/8 DCT chip demonstrate a low power dissipation of 7.5 mW at 75 MHz.","PeriodicalId":6445,"journal":{"name":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)","volume":"58 1","pages":"II-765"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81634219","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-23DOI: 10.1109/ISCAS.2004.1329212
X. Lu, Thierry Fernaine, Yao Wang
As video transmission is integrated into wireless communication systems, the theory of power control should also be expanded to consider both signal processing power and transmission power when designing new algorithms, since video coding consumes a significant portion of power. To better understand the interaction between signal processing and transmission, it helps to develop power consumption models for video coding. The goal of this work is to model the power consumption of an H.263 video encoder, in which motion estimation is the most computation intensive component. Different models for algorithms using 1) full search motion estimation; and 2) a fast algorithm using spiral order motion estimation are presented for a software H.263 encoder. We observe that one set of model parameters fits all test sequences for full search, whereas the model parameters are sequence specific for the fast algorithm.
{"title":"Modelling power consumption of a H.263 video encoder","authors":"X. Lu, Thierry Fernaine, Yao Wang","doi":"10.1109/ISCAS.2004.1329212","DOIUrl":"https://doi.org/10.1109/ISCAS.2004.1329212","url":null,"abstract":"As video transmission is integrated into wireless communication systems, the theory of power control should also be expanded to consider both signal processing power and transmission power when designing new algorithms, since video coding consumes a significant portion of power. To better understand the interaction between signal processing and transmission, it helps to develop power consumption models for video coding. The goal of this work is to model the power consumption of an H.263 video encoder, in which motion estimation is the most computation intensive component. Different models for algorithms using 1) full search motion estimation; and 2) a fast algorithm using spiral order motion estimation are presented for a software H.263 encoder. We observe that one set of model parameters fits all test sequences for full search, whereas the model parameters are sequence specific for the fast algorithm.","PeriodicalId":6445,"journal":{"name":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)","volume":"13 1","pages":"II-77"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81831597","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：