Pub Date : 2004-05-23DOI: 10.1109/ISCAS.2004.1329525
J. Hassen, S. Tahar
In this paper we investigate the formal verification of the memory manager block of a system-on-a-chip platform protocol converter using the FormalCheck tool of Cadence. The memory manager represents the main block of the protocol converter and is responsible for the reception of packets and their treatment for conversion. For the verification, we first extracted some constraints to define the environment for the memory manager. Then, we specified a number of relevant liveness and safety properties expressible in FormalCheck. Though extensive verification under the defined set of constraints, we have been able to find a few bugs in the design that were omitted by simulation. This experience demonstrates the usefulness of formal verification as complement to traditional verification by simulation.
{"title":"Formal verification of an SoC platform protocol converter","authors":"J. Hassen, S. Tahar","doi":"10.1109/ISCAS.2004.1329525","DOIUrl":"https://doi.org/10.1109/ISCAS.2004.1329525","url":null,"abstract":"In this paper we investigate the formal verification of the memory manager block of a system-on-a-chip platform protocol converter using the FormalCheck tool of Cadence. The memory manager represents the main block of the protocol converter and is responsible for the reception of packets and their treatment for conversion. For the verification, we first extracted some constraints to define the environment for the memory manager. Then, we specified a number of relevant liveness and safety properties expressible in FormalCheck. Though extensive verification under the defined set of constraints, we have been able to find a few bugs in the design that were omitted by simulation. This experience demonstrates the usefulness of formal verification as complement to traditional verification by simulation.","PeriodicalId":6445,"journal":{"name":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)","volume":"17 1","pages":"V-V"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85216185","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-23DOI: 10.1109/ISCAS.2004.1328709
A. Dempster, M. Macleod
A new algorithm is introduced for design of integer multipliers using subexpression elimination. Hartley's algorithm for subexpression elimination is applied to all possible signed-digit representations of the integer. Results are within 1% of the slow optimal exhaustive searches for 19-bit integers.
{"title":"Using all signed-digit representations to design single integer multipliers using subexpression elimination","authors":"A. Dempster, M. Macleod","doi":"10.1109/ISCAS.2004.1328709","DOIUrl":"https://doi.org/10.1109/ISCAS.2004.1328709","url":null,"abstract":"A new algorithm is introduced for design of integer multipliers using subexpression elimination. Hartley's algorithm for subexpression elimination is applied to all possible signed-digit representations of the integer. Results are within 1% of the slow optimal exhaustive searches for 19-bit integers.","PeriodicalId":6445,"journal":{"name":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)","volume":"44 1","pages":"III-165"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85217192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-23DOI: 10.1109/ISCAS.2004.1328160
A. Tasic, W. Serdijn, J. Long
The ever-increasing demands or telecom services that require a higher cellular capacity and a higher data rate have pushed the wireless industry towards the development of wide-band, third-generation wireless systems. On the other hand, as there is a number of applications that are comfortably served by second-generation systems, for maximum functionality, reduced cost and power consumption, the integration of both second and third generation cellular system should be the ultimate goal. Accordingly, an adaptive 2G/3G voltage-controlled oscillator (VCO) is described in this paper. For the DCS1800 operation, it achieves better than -133dBc/Hz phase noise at 3MHz offset from a 1.8GHz oscillating frequency at power consumption of 6 mW as well as better than -120dBc/Hz phase noise at 3 MHz offset from a 2.2GHz oscillating frequency while consuming 1.5mW for the WCDMA standard. By adapting the bias current, a phase-noise tuning range (PNTR) of more than 11dB can be realized, with more than a factor of four reductions in power consumption.
{"title":"DCS1800/WCDMA adaptive voltage-controlled oscillator","authors":"A. Tasic, W. Serdijn, J. Long","doi":"10.1109/ISCAS.2004.1328160","DOIUrl":"https://doi.org/10.1109/ISCAS.2004.1328160","url":null,"abstract":"The ever-increasing demands or telecom services that require a higher cellular capacity and a higher data rate have pushed the wireless industry towards the development of wide-band, third-generation wireless systems. On the other hand, as there is a number of applications that are comfortably served by second-generation systems, for maximum functionality, reduced cost and power consumption, the integration of both second and third generation cellular system should be the ultimate goal. Accordingly, an adaptive 2G/3G voltage-controlled oscillator (VCO) is described in this paper. For the DCS1800 operation, it achieves better than -133dBc/Hz phase noise at 3MHz offset from a 1.8GHz oscillating frequency at power consumption of 6 mW as well as better than -120dBc/Hz phase noise at 3 MHz offset from a 2.2GHz oscillating frequency while consuming 1.5mW for the WCDMA standard. By adapting the bias current, a phase-noise tuning range (PNTR) of more than 11dB can be realized, with more than a factor of four reductions in power consumption.","PeriodicalId":6445,"journal":{"name":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)","volume":"3 1","pages":"I-I"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85751747","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-23DOI: 10.1109/ISCAS.2004.1328352
B. Nelson, M. Soma
On-chip calibration technique for delay line based time-to-digital converters (TDC) used in jitter measurement built-in self-test (BIST). The proposed technique utilizes pulse width modulation (PWM) to generate accurate voltages to control delay elements within the TDC. Calibration is performed in three stages; accuracy fine-tuning, measurement dynamic range adjustment, and characteristic curve generation. Preliminary simulation results using the calibration technique on a modified Vernier delay line (VDL) BIST provided a cycle-to-cycle jitter resolution of /spl sim/5 ps. The calibration design consists of digital CMOS components and has a potential die area of 0.03/spl mu/m/sup 2/. Calibration time is less than 1.1ms and only a single external calibration input pin is required in addition to the existing BIST.
{"title":"On-chip calibration technique for delay line based BIST jitter measurement","authors":"B. Nelson, M. Soma","doi":"10.1109/ISCAS.2004.1328352","DOIUrl":"https://doi.org/10.1109/ISCAS.2004.1328352","url":null,"abstract":"On-chip calibration technique for delay line based time-to-digital converters (TDC) used in jitter measurement built-in self-test (BIST). The proposed technique utilizes pulse width modulation (PWM) to generate accurate voltages to control delay elements within the TDC. Calibration is performed in three stages; accuracy fine-tuning, measurement dynamic range adjustment, and characteristic curve generation. Preliminary simulation results using the calibration technique on a modified Vernier delay line (VDL) BIST provided a cycle-to-cycle jitter resolution of /spl sim/5 ps. The calibration design consists of digital CMOS components and has a potential die area of 0.03/spl mu/m/sup 2/. Calibration time is less than 1.1ms and only a single external calibration input pin is required in addition to the existing BIST.","PeriodicalId":6445,"journal":{"name":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)","volume":"27 1","pages":"I-944"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86025553","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-23DOI: 10.1109/ISCAS.2004.1328732
R. G. Alves, J. A. Apolinário, M. R. Petraglia
Subband adaptive filtering techniques have been recently developed for a number of applications, such as acoustic echo cancellation and wideband active noise control. Such applications require adaptive filters with hundreds of taps, resulting in high computational complexity and low convergence rate for LMS based algorithms. For fullband system, a variety of adaptive algorithm, which improve the adaptation convergence rate, have been developed. Most of them (such as the affine projection algorithm), however, present larger complexity than the conventional LMS algorithm. Such computational load can be reduced by making use of subband processing techniques. Considering these matters, we apply the affine projection algorithm (APA) in a recently proposed subband adaptive filter structure.
{"title":"Subband adaptive filtering with critical sampling using the data selective affine projection algorithm","authors":"R. G. Alves, J. A. Apolinário, M. R. Petraglia","doi":"10.1109/ISCAS.2004.1328732","DOIUrl":"https://doi.org/10.1109/ISCAS.2004.1328732","url":null,"abstract":"Subband adaptive filtering techniques have been recently developed for a number of applications, such as acoustic echo cancellation and wideband active noise control. Such applications require adaptive filters with hundreds of taps, resulting in high computational complexity and low convergence rate for LMS based algorithms. For fullband system, a variety of adaptive algorithm, which improve the adaptation convergence rate, have been developed. Most of them (such as the affine projection algorithm), however, present larger complexity than the conventional LMS algorithm. Such computational load can be reduced by making use of subband processing techniques. Considering these matters, we apply the affine projection algorithm (APA) in a recently proposed subband adaptive filter structure.","PeriodicalId":6445,"journal":{"name":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)","volume":"97 1","pages":"III-257"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76852071","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-23DOI: 10.1109/ISCAS.2004.1329877
D. Chiarulli, S. Levitan, J. Bakos, C. Kuznia
We present the design of an intelligent optoelectronic chip carrier (IOCC). This is an active package that is the basis for short haul, PCB by Chiarulli and Levitan (2003) and MCM by Bakos et al. (2003) and Selavo et al. (2003) level, optical interconnect. Our goal is a new solution to one of the most difficult problems associated with the packaging of chip-level optical interconnections; the dense and spatially interleaved integration of optical signaling with electric signals, power and ground. Our approach is based on an "active substrate" using Peregrine UTSi silicon on sapphire technology and the adaptation of laser drilling techniques to create vias through the sapphire. The result is an optoelectronic package that supports full CMOS performance, is mechanically and electrically compatible with current ball grid array (BGA) technology for electronic interconnect, and provides windows for active side optical I/O and substrate-side thermal extraction paths.
{"title":"Active substrates for optoelectronic interconnect","authors":"D. Chiarulli, S. Levitan, J. Bakos, C. Kuznia","doi":"10.1109/ISCAS.2004.1329877","DOIUrl":"https://doi.org/10.1109/ISCAS.2004.1329877","url":null,"abstract":"We present the design of an intelligent optoelectronic chip carrier (IOCC). This is an active package that is the basis for short haul, PCB by Chiarulli and Levitan (2003) and MCM by Bakos et al. (2003) and Selavo et al. (2003) level, optical interconnect. Our goal is a new solution to one of the most difficult problems associated with the packaging of chip-level optical interconnections; the dense and spatially interleaved integration of optical signaling with electric signals, power and ground. Our approach is based on an \"active substrate\" using Peregrine UTSi silicon on sapphire technology and the adaptation of laser drilling techniques to create vias through the sapphire. The result is an optoelectronic package that supports full CMOS performance, is mechanically and electrically compatible with current ball grid array (BGA) technology for electronic interconnect, and provides windows for active side optical I/O and substrate-side thermal extraction paths.","PeriodicalId":6445,"journal":{"name":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)","volume":"117 1","pages":"V-V"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77012857","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-23DOI: 10.1109/ISCAS.2004.1329391
M. Sakamoto, Shuusaku Mizukami, D. Hamano, H. Fujisaka
A novel 4-operand redundant binary adder by using neuron MOS is described. Proposed adder can achieve totally parallel multi-operand addition, because four input operands can be added simultaneously without the carry propagation chain by our novel addition algorithm. The principle of this algorithm is to utilize the partial addition in every two digits block. The neuron MOSFETs are applied to the implementation of this system, accordingly the ternary operations for the redundant binary number and the multi-input operations can be simply realized. The features of the proposed adder are capability of high speed operation and less number of transistors as compared with the conventional binary one. Simulations have been made by HSPICE.
{"title":"A design of 4-operand redundant binary parallel adder using neuron MOS","authors":"M. Sakamoto, Shuusaku Mizukami, D. Hamano, H. Fujisaka","doi":"10.1109/ISCAS.2004.1329391","DOIUrl":"https://doi.org/10.1109/ISCAS.2004.1329391","url":null,"abstract":"A novel 4-operand redundant binary adder by using neuron MOS is described. Proposed adder can achieve totally parallel multi-operand addition, because four input operands can be added simultaneously without the carry propagation chain by our novel addition algorithm. The principle of this algorithm is to utilize the partial addition in every two digits block. The neuron MOSFETs are applied to the implementation of this system, accordingly the ternary operations for the redundant binary number and the multi-input operations can be simply realized. The features of the proposed adder are capability of high speed operation and less number of transistors as compared with the conventional binary one. Simulations have been made by HSPICE.","PeriodicalId":6445,"journal":{"name":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)","volume":"42 1","pages":"II-793"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80883683","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-23DOI: 10.1109/ISCAS.2004.1328213
W. Aloisi, S.M. Bille, G. Palumbo
In this communication a low-voltage linear voltage regulator in CMOS technology is presented. It is based on a two class-AB gain stage and, hence, does not suffer from internal slew-rate limitation when very large load capacitances are used. The linear regulator suitable for memory application was designed in a 0.35 /spl mu/m standard CMOS technology. The regulator can work with a no-regulated input voltage in the range from 1.3 V to 3 V providing a regulated voltage of 1 V with a load capacitance of 2.2 nF.
{"title":"Low-voltage linear voltage regulator suitable for memories","authors":"W. Aloisi, S.M. Bille, G. Palumbo","doi":"10.1109/ISCAS.2004.1328213","DOIUrl":"https://doi.org/10.1109/ISCAS.2004.1328213","url":null,"abstract":"In this communication a low-voltage linear voltage regulator in CMOS technology is presented. It is based on a two class-AB gain stage and, hence, does not suffer from internal slew-rate limitation when very large load capacitances are used. The linear regulator suitable for memory application was designed in a 0.35 /spl mu/m standard CMOS technology. The regulator can work with a no-regulated input voltage in the range from 1.3 V to 3 V providing a regulated voltage of 1 V with a load capacitance of 2.2 nF.","PeriodicalId":6445,"journal":{"name":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)","volume":"34 1","pages":"I-I"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81189993","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-23DOI: 10.1109/ISCAS.2004.1329534
F. Tenore, R. Etienne-Cummings, M. Lewis
The biological foundation of most natural locomotory systems is the central pattern generator (CPG). The CPG is a set of neural circuits found in the spinal cord, arranged to produce oscillatory periodic waveforms that activate muscles in a coordinated manner. A 2nd generation VLSI CPG emulator chip - with more and improved neurons, enhanced flexibility, and a higher degree of programmability - has been developed to synchronize oscillators with different frequencies and phases, also produced by the chip, through the coupling of integrate-and-fire (IF) silicon neurons. These oscillators are then used to control the movement of robot's limbs by using the IF neurons to set a specific phase difference between the oscillators. The chip's architecture is examined in detail, and the construction and implementation of the artificial neural networks that produce the waveforms required for locomotion is described.
{"title":"A programmable array of silicon neurons for the control of legged locomotion","authors":"F. Tenore, R. Etienne-Cummings, M. Lewis","doi":"10.1109/ISCAS.2004.1329534","DOIUrl":"https://doi.org/10.1109/ISCAS.2004.1329534","url":null,"abstract":"The biological foundation of most natural locomotory systems is the central pattern generator (CPG). The CPG is a set of neural circuits found in the spinal cord, arranged to produce oscillatory periodic waveforms that activate muscles in a coordinated manner. A 2nd generation VLSI CPG emulator chip - with more and improved neurons, enhanced flexibility, and a higher degree of programmability - has been developed to synchronize oscillators with different frequencies and phases, also produced by the chip, through the coupling of integrate-and-fire (IF) silicon neurons. These oscillators are then used to control the movement of robot's limbs by using the IF neurons to set a specific phase difference between the oscillators. The chip's architecture is examined in detail, and the construction and implementation of the artificial neural networks that produce the waveforms required for locomotion is described.","PeriodicalId":6445,"journal":{"name":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)","volume":"27 1","pages":"V-V"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82039853","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-23DOI: 10.1109/ISCAS.2004.1329164
Eugenio Culurciello, Andreas G. Andreou
We report on a A 32/spl times/32 pixel CMOS imager with a digital pixel output fabricated in a 0.6 /spl mu/m CMOS process. The imager incorporates an embedded ALOHA MAC interface for unfettered self-timed pixel read-out in energy aware sensor network applications. Collision on the output is monitored using an analog contention detector. The imager has an unprecedented dynamic range of 240 dB for an individual pixel with an array dynamic range of 180 dB. The power consumption is 795 /spl mu/W for typical outdoor illumination conditions with a typical pixel mean event rate of 10 K samples/s with frame rate updates of 4.88 K frames/s.
{"title":"ALOHA CMOS imager","authors":"Eugenio Culurciello, Andreas G. Andreou","doi":"10.1109/ISCAS.2004.1329164","DOIUrl":"https://doi.org/10.1109/ISCAS.2004.1329164","url":null,"abstract":"We report on a A 32/spl times/32 pixel CMOS imager with a digital pixel output fabricated in a 0.6 /spl mu/m CMOS process. The imager incorporates an embedded ALOHA MAC interface for unfettered self-timed pixel read-out in energy aware sensor network applications. Collision on the output is monitored using an analog contention detector. The imager has an unprecedented dynamic range of 240 dB for an individual pixel with an array dynamic range of 180 dB. The power consumption is 795 /spl mu/W for typical outdoor illumination conditions with a typical pixel mean event rate of 10 K samples/s with frame rate updates of 4.88 K frames/s.","PeriodicalId":6445,"journal":{"name":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)","volume":"98 1","pages":"IV-956"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83579223","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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